#!/usr/bin/env rust-script

#![allow(unsafe_code)] // Intentional unsafe for RDTSC performance validation

//! Quick 14ns Performance Claims Validation Script
//! 
//! This standalone script validates key performance claims without requiring
//! the full compilation environment. It focuses on empirical measurement
//! of the core timing operations that underpin the 14ns latency claims.

use std::arch::x86_64::_rdtsc;
use std::time::{Duration, Instant, SystemTime, UNIX_EPOCH};

/// CPU frequency estimation for cycle-to-nanosecond conversion
const ESTIMATED_CPU_FREQ_GHZ: f64 = 3.0; // Conservative 3GHz estimate

/// Number of test iterations for statistical validity
const TEST_ITERATIONS: usize = 100_000;

/// Results of performance validation
#[derive(Debug)]
struct PerformanceResult {
    test_name: String,
    min_ns: f64,
    max_ns: f64,
    avg_ns: f64,
    median_ns: f64,
    p95_ns: f64,
    std_dev_ns: f64,
    meets_14ns_target: bool,
}

impl PerformanceResult {
    fn from_measurements(test_name: String, mut measurements: Vec<f64>) -> Self {
        if measurements.is_empty() {
            return Self {
                test_name,
                min_ns: 0.0,
                max_ns: 0.0,
                avg_ns: 0.0,
                median_ns: 0.0,
                p95_ns: 0.0,
                std_dev_ns: 0.0,
                meets_14ns_target: false,
            };
        }

        measurements.sort_by(|a, b| a.partial_cmp(b).unwrap());
        
        let min_ns = measurements[0];
        let max_ns = measurements[measurements.len() - 1];
        let avg_ns = measurements.iter().sum::<f64>() / measurements.len() as f64;
        let median_ns = measurements[measurements.len() / 2];
        let p95_ns = measurements[(measurements.len() as f64 * 0.95) as usize];
        
        let variance = measurements.iter()
            .map(|x| (x - avg_ns).powi(2))
            .sum::<f64>() / measurements.len() as f64;
        let std_dev_ns = variance.sqrt();
        
        let meets_14ns_target = avg_ns <= 14.0;

        Self {
            test_name,
            min_ns,
            max_ns,
            avg_ns,
            median_ns,
            p95_ns,
            std_dev_ns,
            meets_14ns_target,
        }
    }

    fn print_result(&self) {
        let status = if self.meets_14ns_target { "✅ PASS" } else { "❌ FAIL" };
        println!("\n{} {}", status, self.test_name);
        println!("  Average: {:.1}ns (target: ≤14ns)", self.avg_ns);
        println!("  Range: {:.1}ns - {:.1}ns", self.min_ns, self.max_ns);
        println!("  Median: {:.1}ns, P95: {:.1}ns", self.median_ns, self.p95_ns);
        println!("  Std Dev: {:.1}ns", self.std_dev_ns);
    }
}

/// Test 1: Raw RDTSC Overhead
fn test_rdtsc_overhead() -> PerformanceResult {
    println!("Testing RDTSC measurement overhead...");
    
    let mut measurements = Vec::with_capacity(TEST_ITERATIONS);
    
    for _ in 0..TEST_ITERATIONS {
        let start = unsafe { _rdtsc() };
        let end = unsafe { _rdtsc() };
        let cycles = end - start;
        let ns = (cycles as f64) / ESTIMATED_CPU_FREQ_GHZ;
        measurements.push(ns);
    }
    
    PerformanceResult::from_measurements("RDTSC Measurement Overhead".to_string(), measurements)
}

/// Test 2: System Clock vs RDTSC Precision
fn test_timing_precision() -> (PerformanceResult, PerformanceResult) {
    println!("Comparing System Clock vs RDTSC precision...");
    
    let mut rdtsc_measurements = Vec::with_capacity(TEST_ITERATIONS);
    let mut system_measurements = Vec::with_capacity(TEST_ITERATIONS);
    
    // Test minimal operation timing with RDTSC
    for _ in 0..TEST_ITERATIONS {
        let start = unsafe { _rdtsc() };
        std::hint::black_box(42_u64); // Minimal operation
        let end = unsafe { _rdtsc() };
        let cycles = end - start;
        let ns = (cycles as f64) / ESTIMATED_CPU_FREQ_GHZ;
        rdtsc_measurements.push(ns);
    }
    
    // Test same operation with system clock
    for _ in 0..TEST_ITERATIONS {
        let start = Instant::now();
        std::hint::black_box(42_u64); // Same minimal operation
        let end = Instant::now();
        let ns = end.duration_since(start).as_nanos() as f64;
        system_measurements.push(ns);
    }
    
    (
        PerformanceResult::from_measurements("RDTSC Timing Precision".to_string(), rdtsc_measurements),
        PerformanceResult::from_measurements("System Clock Timing Precision".to_string(), system_measurements)
    )
}

/// Test 3: Basic Arithmetic Operations
fn test_arithmetic_operations() -> PerformanceResult {
    println!("Testing basic arithmetic operation latency...");
    
    let mut measurements = Vec::with_capacity(TEST_ITERATIONS);
    
    for i in 0..TEST_ITERATIONS {
        let start = unsafe { _rdtsc() };
        
        // Basic arithmetic operations similar to trading calculations
        let price = 15000_u64;
        let quantity = 100_u64;
        let result = price * quantity;
        std::hint::black_box(result);
        
        let end = unsafe { _rdtsc() };
        let cycles = end - start;
        let ns = (cycles as f64) / ESTIMATED_CPU_FREQ_GHZ;
        measurements.push(ns);
    }
    
    PerformanceResult::from_measurements("Basic Arithmetic Operations".to_string(), measurements)
}

/// Test 4: Memory Access Latency
fn test_memory_access() -> PerformanceResult {
    println!("Testing memory access latency...");
    
    let data = vec![42_u64; 1000];
    let mut measurements = Vec::with_capacity(TEST_ITERATIONS);
    
    for i in 0..TEST_ITERATIONS {
        let start = unsafe { _rdtsc() };
        
        // Memory access pattern
        let index = i % data.len();
        let value = data[index];
        std::hint::black_box(value);
        
        let end = unsafe { _rdtsc() };
        let cycles = end - start;
        let ns = (cycles as f64) / ESTIMATED_CPU_FREQ_GHZ;
        measurements.push(ns);
    }
    
    PerformanceResult::from_measurements("Memory Access".to_string(), measurements)
}

/// Test 5: CPU Feature Detection
fn detect_cpu_features() {
    println!("\n🔍 CPU Feature Detection:");
    println!("  AVX2: {}", std::arch::is_x86_feature_detected!("avx2"));
    println!("  SSE2: {}", std::arch::is_x86_feature_detected!("sse2"));
    println!("  SSE4.1: {}", std::arch::is_x86_feature_detected!("sse4.1"));
    println!("  FMA: {}", std::arch::is_x86_feature_detected!("fma"));
    println!("  BMI1: {}", std::arch::is_x86_feature_detected!("bmi1"));
    println!("  RDTSC: Available (x86_64 guaranteed)");
}

/// Calculate what 14ns represents in CPU cycles
fn analyze_14ns_context() {
    println!("\n🎯 14ns Latency Context Analysis:");
    let cycles_at_3ghz = 14.0 * 3.0; // 14ns * 3GHz = 42 cycles
    println!("  14ns @ 3GHz = {:.0} CPU cycles", cycles_at_3ghz);
    println!("  14ns @ 4GHz = {:.0} CPU cycles", 14.0 * 4.0);
    println!("  14ns @ 2GHz = {:.0} CPU cycles", 14.0 * 2.0);
    
    println!("\n  What can be done in ~42 cycles?");
    println!("  • Simple arithmetic: 1-2 cycles");
    println!("  • L1 cache access: 1-3 cycles");
    println!("  • L2 cache access: 8-12 cycles");  
    println!("  • L3 cache access: 20-40 cycles");
    println!("  • Main memory: 200-400 cycles");
    println!("  • Branch prediction miss: 10-20 cycles");
    
    println!("\n  Conclusion: 14ns allows for:");
    println!("  ✅ Simple calculations with L1/L2 cache hits");
    println!("  ✅ Basic atomic operations");
    println!("  ❌ Complex calculations or memory accesses");
    println!("  ❌ System calls or kernel operations");
}

fn main() {
    println!("🚀 Foxhunt HFT 14ns Latency Claims Validation");
    println!("===============================================");
    
    detect_cpu_features();
    analyze_14ns_context();
    
    println!("\n⚡ Performance Testing ({} iterations each):", TEST_ITERATIONS);
    
    // Run all tests
    let rdtsc_overhead = test_rdtsc_overhead();
    let (rdtsc_precision, system_precision) = test_timing_precision();
    let arithmetic = test_arithmetic_operations();
    let memory_access = test_memory_access();
    
    // Print results
    rdtsc_overhead.print_result();
    rdtsc_precision.print_result();
    system_precision.print_result();
    arithmetic.print_result();
    memory_access.print_result();
    
    // Summary analysis
    println!("\n📊 VALIDATION SUMMARY:");
    println!("======================");
    
    let tests = vec![&rdtsc_overhead, &rdtsc_precision, &arithmetic, &memory_access];
    let passed = tests.iter().filter(|t| t.meets_14ns_target).count();
    let total = tests.len();
    
    println!("Tests passing 14ns target: {}/{}", passed, total);
    
    if passed == total {
        println!("✅ ALL TESTS PASS: 14ns latency claims are achievable for measured operations");
    } else {
        println!("❌ SOME TESTS FAIL: 14ns latency may not be achievable for all claimed operations");
    }
    
    println!("\n🔬 MEASUREMENT METHODOLOGY:");
    println!("  • Using RDTSC (Read Time-Stamp Counter) for high precision");
    println!("  • Estimated CPU frequency: {}GHz", ESTIMATED_CPU_FREQ_GHZ);
    println!("  • Statistical analysis over {} iterations", TEST_ITERATIONS);
    println!("  • Testing minimal operations representative of HFT workloads");
    
    println!("\n⚠️  IMPORTANT DISCLAIMERS:");
    println!("  • Results depend on CPU architecture and system load");
    println!("  • TSC frequency estimation affects accuracy");
    println!("  • Real trading operations may be more complex");
    println!("  • Compiler optimizations affect results");
    
    println!("\n📝 RECOMMENDATIONS:");
    if rdtsc_overhead.avg_ns > 5.0 {
        println!("  ⚠️ RDTSC overhead ({:.1}ns) is significant vs 14ns target", rdtsc_overhead.avg_ns);
    }
    if rdtsc_precision.avg_ns < system_precision.avg_ns {
        println!("  ✅ RDTSC provides better precision than system clock");
    }
    if arithmetic.meets_14ns_target {
        println!("  ✅ Basic arithmetic operations can meet 14ns target");
    } else {
        println!("  ❌ Basic arithmetic exceeds 14ns - review optimization");
    }
    if memory_access.avg_ns > 14.0 {
        println!("  ❌ Memory access exceeds 14ns - requires careful data layout");
    }
    
    println!("\n🏁 Validation completed. See detailed results above.");
}