From 14af4854fbd64dcc2b4102a871c2ca5ca651e86c Mon Sep 17 00:00:00 2001
From: jgrusewski <jgrusewski@localhost>
Date: Sun, 3 May 2026 16:11:23 +0200
Subject: [PATCH] =?UTF-8?q?fix(merge):=20resolve=20sp5=E2=86=92main=20merg?=
 =?UTF-8?q?e=20fixups=20=E2=80=94=20DevicePtrMut=20import=20+=20adam=5Fste?=
 =?UTF-8?q?p=207-arg=20signature?=
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After sp5 merge with -X theirs, two compile errors needed manual fix:
- gpu_her.rs lost the DevicePtrMut trait import
- gpu_tlob.rs Fix 20 regression test used the 4-arg adam_step signature
  before sp5's Pearl 4 added β1/β2/ε params.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
---
 crates/ml/src/cuda_pipeline/gpu_her.rs  | 2 +-
 crates/ml/src/cuda_pipeline/gpu_tlob.rs | 9 ++++++++-
 docs/dqn-wire-up-audit.md               | 9 +++++++++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/crates/ml/src/cuda_pipeline/gpu_her.rs b/crates/ml/src/cuda_pipeline/gpu_her.rs
index 8fc737540..1ef7e0d39 100644
--- a/crates/ml/src/cuda_pipeline/gpu_her.rs
+++ b/crates/ml/src/cuda_pipeline/gpu_her.rs
@@ -29,7 +29,7 @@
 
 use std::sync::Arc;
 
-use cudarc::driver::{CudaFunction, CudaSlice, CudaStream, LaunchConfig, PushKernelArg};
+use cudarc::driver::{CudaFunction, CudaSlice, CudaStream, DevicePtrMut, LaunchConfig, PushKernelArg};
 use tracing::info;
 
 use crate::MLError;
diff --git a/crates/ml/src/cuda_pipeline/gpu_tlob.rs b/crates/ml/src/cuda_pipeline/gpu_tlob.rs
index 74911c680..58b0d3fa9 100644
--- a/crates/ml/src/cuda_pipeline/gpu_tlob.rs
+++ b/crates/ml/src/cuda_pipeline/gpu_tlob.rs
@@ -2212,7 +2212,14 @@ mod tests {
         let max_grad_norm = 1e9_f32;
         let weight_clamp = 0.0_f32;
         let weight_decay = 0.0_f32;
-        tlob.adam_step(lr, max_grad_norm, weight_clamp, weight_decay)
+        // SP5 Layer B: adam_step signature took on Adam β1/β2/ε params from ISV.
+        // Standard Adam defaults — exact β/ε don't affect this test's W_Q/dW_Q
+        // layout assertion; only exercising that Adam runs at all.
+        let attn_beta1 = 0.9_f32;
+        let attn_beta2 = 0.999_f32;
+        let attn_epsilon = 1e-8_f32;
+        tlob.adam_step(lr, max_grad_norm, weight_clamp, weight_decay,
+                       attn_beta1, attn_beta2, attn_epsilon)
             .expect("adam");
         stream.synchronize().expect("sync adam");
 
diff --git a/docs/dqn-wire-up-audit.md b/docs/dqn-wire-up-audit.md
index 3d64bbb45..750730173 100644
--- a/docs/dqn-wire-up-audit.md
+++ b/docs/dqn-wire-up-audit.md
@@ -4122,3 +4122,12 @@ extended. No producer kernel yet — that arrives in the next commit.
   (HEALTH_DIAG label + index, +6 LOC, −5 LOC), this audit entry.
 
 Contract test — every RegistryEntry has dispatch arm (2026-05-03): added `every_fold_and_soft_reset_entry_has_dispatch_arm` unit test to the existing `#[cfg(test)] mod tests` block in `state_reset_registry.rs`. Source-introspection design: `include_str!` both `state_reset_registry.rs` and `trainer/training_loop.rs`; brace-balance walk extracts the `match name {` body; for each FoldReset/SoftReset entry (97 total: 95 FoldReset + 2 SoftReset) asserts the literal `"<name>"` appears in that body. No production-code change. No new dependency (manual brace walk instead of regex). Catches the recurring "add RegistryEntry, forget dispatch arm → fold-boundary panic" bug (occurred twice: SP5 Layer A #281, SP7 T7 commit 6e479c55c) at `cargo test -p ml --lib` rather than mid-training. Test currently passes (all 97 dispatch arms present post SP7 T7 fix). Touched: `trainers/dqn/state_reset_registry.rs` (+59 LOC in cfg-test block).
+
+### Fix 32 — sp5 → main merge resolution fixups (2026-05-03)
+
+After merging `sp5-magnitude-differentiation` into `main` (bringing SP4+SP5+SP6+SP7 + observability + ISV bus fix), `-X theirs` strategy auto-resolved 18 conflicts in 9 files but left two compile errors needing manual fix:
+
+1. `crates/ml/src/cuda_pipeline/gpu_her.rs:32` — the `-X theirs` resolution dropped the `DevicePtrMut` trait import while retaining a `device_ptr_mut` call site at line 188. Re-added the import.
+2. `crates/ml/src/cuda_pipeline/gpu_tlob.rs:2215` — Fix 20's regression test `tlob_dw_layout_alignment_regression_full_chain` called `adam_step(lr, max_grad_norm, weight_clamp, weight_decay)` (4 args), but sp5's evolved Adam signature added 3 more (β1, β2, ε from ISV per SP5 Pearl 4). Added standard-default values; test purpose is layout assertion, not Adam dynamics.
+
+`cargo check -p ml`: clean post-fixup. 19 pre-existing warnings, 0 new.