diff --git a/crates/ml/src/trainers/dqn/state_reset_registry.rs b/crates/ml/src/trainers/dqn/state_reset_registry.rs
index dadae205d..d393e523c 100644
--- a/crates/ml/src/trainers/dqn/state_reset_registry.rs
+++ b/crates/ml/src/trainers/dqn/state_reset_registry.rs
@@ -881,14 +881,16 @@ impl StateResetRegistry {
                 description: "ISV[PNL_REWARD_MAGNITUDE_EMA_INDEX=359] — SP11 Fix 39 PnL-reward magnitude EMA (running `|reward_total|` smoothed with Wiener-α). Produced by the unified-reward kernel chain (existing producer; SP11 wires the EMA output to this slot in A1 alongside the val-sharpe and engagement canaries). Consumed by the SP11 controller as the curiosity-bound scale factor (`curiosity_bound = SP11_CURIOSITY_BOUND_FRACTION=0.3 × this slot`) per `feedback_isv_for_adaptive_bounds.md` §3.4.2. FoldReset sentinel 0; Pearl A bootstraps. Spec §3.3.1, §3.4.2.",
             },
             // SP5 Task A1: Wiener-state companion reset. The wiener_state_buf
-            // now covers SP4 (71 producers × 3 = 213 floats) + SP5 (110 × 3 = 330
-            // floats) = 543 floats total. The SP5 triples start at offset 213.
+            // covers SP4 (SP4_PRODUCER_COUNT=71 producers × 3 = 213 floats) +
+            // SP5 (SP5_PRODUCER_COUNT × 3 floats) = (71 + SP5_PRODUCER_COUNT) × 3
+            // floats total. With SP5_PRODUCER_COUNT=186 (post-SP11 Fix 39) the
+            // buffer is 771 floats; the SP5 triples start at offset 213.
             // Both halves of the Pearl A sentinel contract must reset together per
             // `feedback_no_partial_refactor.md`.
             RegistryEntry {
                 name: "sp5_wiener_state",
                 category: ResetCategory::FoldReset,
-                description: "GpuDqnTrainer.wiener_state_buf SP5 block at offsets [213..(213 + SP5_PRODUCER_COUNT*3)). The total buffer is sized via `SP5_WIENER_TOTAL_FLOATS = (SP4_PRODUCER_COUNT=71 + SP5_PRODUCER_COUNT=156) × 3 = 681` floats post-SP8 Fix 36 (was 543 at SP5 Task A1, 582 post-Layer-D-D3, 663 post-SP7 activation-flag fix). Each producer triple = {sample_var, diff_var, x_lag}. SP5 Pearl D Wiener-EMA state for ALL SP5 producers (Pearls 1, 2, 3, 4, 5, Layer D D1/D2/D3, SP7 T1, SP7 activation-flag fix, SP8 Fix 36). Bulk write_bytes(0) at fold boundary covers the full wiener_state_buf [0..SP5_WIENER_TOTAL_FLOATS) so Pearl A's sentinel branch fires on the new fold's first producer launch. Pearl 6 (slots 280..286) does NOT use this buffer — Pearl 6 is cross-fold-persistent and uses in-kernel EWMA + cumulative-via-max(); the wiener slots [525..543) that Pearl 6 would map to under naive offset arithmetic (213 + (280-174)*3 = 525) are intentionally unused. Both SP4 and SP5 [non-Pearl-6] blocks reset atomically.",
+                description: "GpuDqnTrainer.wiener_state_buf SP5 block at offsets [SP4_PRODUCER_COUNT × 3 .. (SP4_PRODUCER_COUNT + SP5_PRODUCER_COUNT) × 3) = [213..(213 + SP5_PRODUCER_COUNT × 3)). The total buffer is sized via `SP5_WIENER_TOTAL_FLOATS = (SP4_PRODUCER_COUNT=71 + SP5_PRODUCER_COUNT) × 3` floats; with SP5_PRODUCER_COUNT=186 (current value, post-SP11 Fix 39) the buffer is 771 floats and the SP5 block is [213..771). Each producer triple = {sample_var, diff_var, x_lag}. SP5 Pearl D Wiener-EMA state for ALL SP5 producers (Pearls 1, 2, 3, 4, 5, Layer D D1/D2/D3, SP7 T1, SP7 activation-flag fix, SP8 Fix 36, SP9 Kelly cold-start, SP10 eval Thompson temperature, SP11 reward-subsystem controller). Bulk write_bytes(0) at fold boundary covers the full wiener_state_buf [0..SP5_WIENER_TOTAL_FLOATS) so Pearl A's sentinel branch fires on the new fold's first producer launch. Pearl 6 (slots 280..286) does NOT use this buffer — Pearl 6 is cross-fold-persistent and uses in-kernel EWMA + cumulative-via-max(); the wiener slots [525..543) that Pearl 6 would map to under naive offset arithmetic (213 + (280-174)*3 = 525) are intentionally unused. Both SP4 and SP5 [non-Pearl-6] blocks reset atomically.",
             },
             // SP5 Task A6: Pearl 6 cross-fold-persistent Kelly cap signals.
             // ISV[280..286) are EXPLICITLY EXEMPT from this registry.
diff --git a/crates/ml/src/trainers/dqn/trainer/training_loop.rs b/crates/ml/src/trainers/dqn/trainer/training_loop.rs
index d19912a68..f91b3af27 100644
--- a/crates/ml/src/trainers/dqn/trainer/training_loop.rs
+++ b/crates/ml/src/trainers/dqn/trainer/training_loop.rs
@@ -6670,12 +6670,15 @@ impl DQNTrainer {
             }
             "sp5_wiener_state" => {
                 // No-op: `reset_sp4_wiener_state` already bulk-zeros the
-                // FULL `wiener_state_buf [0..543)` which includes the SP5
-                // producer block at offsets [213..543). The registry
-                // entry exists for documentation symmetry with the SP4
-                // entry; the actual byte-zero is performed by the SP4 arm.
-                // Pearl 6 (slots 280..286) is intentionally exempt — its
-                // wiener-state offsets [525..543) are unused by design
+                // FULL `wiener_state_buf [0..(71 + SP5_PRODUCER_COUNT) × 3)`
+                // which includes the SP5 producer block at offsets
+                // [71 × 3 .. (71 + SP5_PRODUCER_COUNT) × 3). Post-SP11
+                // (SP5_PRODUCER_COUNT = 186): buffer is 771 floats, SP5
+                // block at [213..771). The registry entry exists for
+                // documentation symmetry with the SP4 entry; the actual
+                // byte-zero is performed by the SP4 arm. Pearl 6 (slots
+                // 280..286) is intentionally exempt — its wiener-state
+                // offsets [525..543) are unused by design
                 // (apply_pearls_ad_kernel is not called for Pearl 6).
             }
             "sp5_noisy_sigma" => {
diff --git a/docs/isv-slots.md b/docs/isv-slots.md
index c43996507..5e38bd4a6 100644
--- a/docs/isv-slots.md
+++ b/docs/isv-slots.md
@@ -15,7 +15,7 @@ at the head would displace those live signals and require shifting every upstrea
 literal in `experience_kernels.cu`. The fingerprint moves to the new tail each time
 new slots are appended to the bus.
 
-**Current `ISV_TOTAL_DIM`:** 171 (post-SP4 Task A1 reservation extending the bus from 131 → 171 with 40 contiguous magnitude/EMA-rate/regularization-bound slots at `[131..171)`; SP4 slots are reservation-only and zero-initialized until subsequent layer-B/C tasks land producers). Producers and consumers for slots `[0..131)` are wired across Plan 1, Plan 2 (Task 1 C.1, Task 3 D.2 per-branch gamma, Task 6C D.8 TLOB), Plan 3 (Task 1 C.2 reward-component EMAs, Task 3 B.2 trade-attempt novelty, Task 4 B.4 readiness-EMA, Task 7 C.3 state-distribution KL, Task 8 B.3 GPU-only seed warm-start, Task 9 C.5 CQL α ramp), Plan 4 (Task 5 Mode A E.5 attention-focus EMAs, follow-up target-drift EMAs, Task 6 C.A multi-task aux head EMAs, Task 6 / Plan 5 follow-up label-scale EMA, MoE expert-utilisation + gate-entropy EMAs + adaptive-lambda controller, Q-drift-rate diagnostic, fold warmup factor).
+**Current `ISV_TOTAL_DIM`:** 360 (post-SP11 Task A0 reservation extending the bus from 340 → 360 with 20 contiguous reward-subsystem-controller slots at `[340..360)`; SP11 A0 slots are reservation-only and zero-initialized until A1/A2/Layer-B land producers and atomic consumer migration — see the SP11 section at the bottom of this file). Earlier expansions: SP4 Task A1 (131 → 171, 40 slots at `[131..171)`); SP5 Task A0 (173 → 286, 110 slots; producer wave landed across A1–A8 + Layer D); SP6/SP7/SP8/SP9/SP10 incremental allocations onto the SP5 block (286 → 340). Producers and consumers for slots `[0..131)` are wired across Plan 1, Plan 2 (Task 1 C.1, Task 3 D.2 per-branch gamma, Task 6C D.8 TLOB), Plan 3 (Task 1 C.2 reward-component EMAs, Task 3 B.2 trade-attempt novelty, Task 4 B.4 readiness-EMA, Task 7 C.3 state-distribution KL, Task 8 B.3 GPU-only seed warm-start, Task 9 C.5 CQL α ramp), Plan 4 (Task 5 Mode A E.5 attention-focus EMAs, follow-up target-drift EMAs, Task 6 C.A multi-task aux head EMAs, Task 6 / Plan 5 follow-up label-scale EMA, MoE expert-utilisation + gate-entropy EMAs + adaptive-lambda controller, Q-drift-rate diagnostic, fold warmup factor).
 
 | Index | Name constant | Type | Producer | Consumers | Reset-category | Notes |
 |---|---|---|---|---|---|---|