feat(sp17-3.1): A_var_ema per-branch producer + HEALTH_DIAG emit
Phase 3 of SP17 dueling-Q identifiability — first of three diagnostic
producers landed atomically with kernel + launcher + Rust wrapper +
HEALTH_DIAG emit + GPU oracle test per `feedback_wire_everything_up`.
Per branch d ∈ {dir, mag, ord, urg}:
Var_d = (1/(B × n_d × NA)) Σ_{i, a, z} (A[i, a, z] − mean_a A[*, z])²
Block tree-reduce (no atomicAdd, `feedback_no_atomicadd`); 4 blocks ×
256 threads. Pearl-A first-observation bootstrap (sentinel 0.0 →
REPLACE on first launch); steady-state α = WELFORD_ALPHA_MIN=0.4 per
`pearl_wiener_alpha_floor_for_nonstationary` — the structural-control
floor preserves catch-up bandwidth without storing 24 Welford
accumulator slots for a cold-path-cadence diagnostic.
Cold-path emit: single launch per HEALTH_DIAG cadence (epoch boundary)
right after `v_a_means`. New line:
HEALTH_DIAG[N]: dueling [a_var=(d=X m=Y o=Z u=W)]
The line will be extended with V_share + advantage_clip_bound in
Phase 3.2, then finalised in Phase 3.3.
GPU oracle test on RTX 3050 Ti: synthetic A constructed so each branch
d has a closed-form Var(A_centered); kernel readback matches expected
value within ε=1e-4 (f32 rounding budget for ~8×n×51 accumulator
length).
Plan: docs/superpowers/plans/2026-05-08-sp17-dueling-q-network.md
Phase 3.1.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
jgrusewski
@@ -674,6 +674,18 @@ pub(crate) static SP14_Q_DISAGREEMENT_CUBIN: &[u8] =
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pub(crate) static SP17_V_A_MEANS_DIAG_CUBIN: &[u8] =
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include_bytes!(concat!(env!("OUT_DIR"), "/v_a_means_diag_kernel.cubin"));
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/// SP17 Phase 3.1 (2026-05-08): per-branch EMA of the over-actions
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/// variance of `A_centered`. 4 blocks × 256 threads (one block per
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/// branch). Cold-path (epoch boundary) producer for the HEALTH_DIAG
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/// `dueling [a_var=...]` line; signals dueling-Q identifiability health
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/// (Var → 0 = `all actions equivalent, V dominates` = pre-SP17 pathology
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/// re-emerging). Block tree-reduce per `feedback_no_atomicadd`. Pearl-A
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/// first-observation bootstrap on slots 474..478. Loaded from
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/// `sp17_a_var_ema_kernel.cubin`. Consumed by
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/// `read_a_var_ema_per_branch()`.
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pub(crate) static SP17_A_VAR_EMA_CUBIN: &[u8] =
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include_bytes!(concat!(env!("OUT_DIR"), "/sp17_a_var_ema_kernel.cubin"));
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// SP14 Layer C Phase C.1 (2026-05-08): α-machinery cubin statics deleted
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// atomically with the alpha_grad_compute / gradient_hack_detect /
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// sp14_scale_wire_col kernel files. SP14_ALPHA_GRAD_CUBIN,
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@@ -6712,6 +6724,15 @@ pub struct GpuDqnTrainer {
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/// host reads via `read_all()` after a stream sync. Per
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/// `feedback_no_htod_htoh_only_mapped_pinned`.
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sp17_v_a_means_diag_buf: super::mapped_pinned::MappedF32Buffer,
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// ── SP17 Phase 3.1 (2026-05-08): per-branch A_var EMA producer ────────
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/// 4-block × 256-thread kernel computing per-branch
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/// `Var(A_centered)` over (B × n_branch × NA) and writing the EMA
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/// into ISV[A_VAR_EMA_DIR/MAG/ORD/URG_INDEX] (slots 474..478).
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/// Pearl-A first-observation bootstrap on sentinel 0.0; α=0.4
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/// post-bootstrap per `pearl_wiener_alpha_floor_for_nonstationary`.
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/// Loaded from `sp17_a_var_ema_kernel.cubin`. Consumed by
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/// `read_a_var_ema_per_branch()`.
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sp17_a_var_ema_kernel: CudaFunction,
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// SP14 Layer C Phase C.1 (2026-05-08): α-machinery struct fields deleted
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// atomically with the kernel files (alpha_grad_compute_kernel,
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// gradient_hack_detect_kernel, sp14_scale_wire_col_kernel) per
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@@ -9009,6 +9030,112 @@ impl GpuDqnTrainer {
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Ok([host[0], host[1], host[2], host[3], host[4]])
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}
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/// SP17 Phase 3.1 (2026-05-08) — per-branch A_var EMA producer launch.
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///
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/// Cold-path (epoch boundary) launcher for `sp17_a_var_ema_kernel`.
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/// Reads the same online advantage buffer (`on_b_logits_buf`) that
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/// `compute_expected_q` consumes; computes per-branch
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/// `Var(A_centered)` over (B × n_branch × NA) where
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/// `A_centered[i, a, z] = A[i, a, z] − (1/n_d) Σ_a' A[i, a', z]`
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/// and EMA-blends into ISV[A_VAR_EMA_*_INDEX] with Pearl-A
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/// first-observation bootstrap (sentinel
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/// `SENTINEL_A_VAR_EMA=0.0`) + α=`WELFORD_ALPHA_MIN=0.4` per
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/// `pearl_wiener_alpha_floor_for_nonstationary`.
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///
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/// 4 blocks × 256 threads (one block per branch — dir/mag/ord/urg).
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/// Block tree-reduce per `feedback_no_atomicadd`. Returns Ok(()) on
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/// success; HEALTH_DIAG reads the ISV slots via
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/// `read_isv_signal_at(A_VAR_EMA_*_INDEX)` after a stream sync.
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///
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/// Diagnostic only — does NOT modify any consumer path. Per
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/// `feedback_no_htod_htoh_only_mapped_pinned` the ISV bus is already
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/// mapped-pinned; this kernel writes via `dev_ptr +
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/// __threadfence_system()` and the host reads after sync.
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pub fn launch_a_var_ema_update(&self) -> Result<(), MLError> {
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use super::sp14_isv_slots::{
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A_VAR_EMA_DIR_INDEX, A_VAR_EMA_MAG_INDEX,
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A_VAR_EMA_ORD_INDEX, A_VAR_EMA_URG_INDEX,
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SENTINEL_A_VAR_EMA, WELFORD_ALPHA_MIN,
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};
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let b = self.config.batch_size;
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let na = self.config.num_atoms;
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let b0 = self.config.branch_0_size;
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let b1 = self.config.branch_1_size;
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let b2 = self.config.branch_2_size;
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let b3 = self.config.branch_3_size;
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if b == 0 || na == 0 || (b0 + b1 + b2 + b3) == 0 {
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return Ok(());
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}
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let adv_ptr = self.on_b_logits_buf.raw_ptr();
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let isv_ptr = self.isv_signals_dev_ptr;
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let b_i32 = b as i32;
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let na_i32 = na as i32;
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let b0_i32 = b0 as i32;
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let b1_i32 = b1 as i32;
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let b2_i32 = b2 as i32;
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let b3_i32 = b3 as i32;
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let var_idx_dir = A_VAR_EMA_DIR_INDEX as i32;
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let var_idx_mag = A_VAR_EMA_MAG_INDEX as i32;
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let var_idx_ord = A_VAR_EMA_ORD_INDEX as i32;
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let var_idx_urg = A_VAR_EMA_URG_INDEX as i32;
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let alpha: f32 = WELFORD_ALPHA_MIN;
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let sentinel: f32 = SENTINEL_A_VAR_EMA;
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// 4 blocks × 256 threads. Dynamic shmem = (BLOCK_SIZE + NA) × 4
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// bytes for the tree-reduce tile + per-atom mean cache.
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let block_dim: u32 = 256;
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let shmem_bytes: u32 =
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(block_dim + na as u32) * std::mem::size_of::<f32>() as u32;
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unsafe {
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self.stream
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.launch_builder(&self.sp17_a_var_ema_kernel)
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.arg(&adv_ptr)
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.arg(&isv_ptr)
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.arg(&b_i32)
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.arg(&na_i32)
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.arg(&b0_i32)
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.arg(&b1_i32)
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.arg(&b2_i32)
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.arg(&b3_i32)
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.arg(&var_idx_dir)
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.arg(&var_idx_mag)
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.arg(&var_idx_ord)
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.arg(&var_idx_urg)
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.arg(&alpha)
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.arg(&sentinel)
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.launch(LaunchConfig {
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grid_dim: (4, 1, 1),
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block_dim: (block_dim, 1, 1),
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shared_mem_bytes: shmem_bytes,
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})
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.map_err(|e| MLError::ModelError(format!(
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"sp17_a_var_ema_update launch: {e}"
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)))?;
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}
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Ok(())
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}
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/// SP17 Phase 3.1 (2026-05-08) — per-branch A_var EMA readback.
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///
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/// Convenience wrapper: launches the producer, syncs, returns
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/// `[a_var_dir, a_var_mag, a_var_ord, a_var_urg]` from the ISV bus.
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/// Cold-path only (HEALTH_DIAG cadence).
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pub fn read_a_var_ema_per_branch(&self) -> Result<[f32; 4], MLError> {
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use super::sp14_isv_slots::{
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A_VAR_EMA_DIR_INDEX, A_VAR_EMA_MAG_INDEX,
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A_VAR_EMA_ORD_INDEX, A_VAR_EMA_URG_INDEX,
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};
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self.launch_a_var_ema_update()?;
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self.stream
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.synchronize()
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.map_err(|e| MLError::ModelError(format!("sp17_a_var_ema sync: {e}")))?;
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Ok([
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self.read_isv_signal_at(A_VAR_EMA_DIR_INDEX),
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self.read_isv_signal_at(A_VAR_EMA_MAG_INDEX),
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self.read_isv_signal_at(A_VAR_EMA_ORD_INDEX),
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self.read_isv_signal_at(A_VAR_EMA_URG_INDEX),
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])
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}
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/// Update per-branch liquid tau modulation — GPU kernel (RK4/Euler adaptive ODE).
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///
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/// Reads per_branch_q_gaps (pinned device-mapped) and qlstm_context from device.
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@@ -20117,6 +20244,17 @@ impl GpuDqnTrainer {
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}
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.map_err(|e| MLError::ModelError(format!("sp17_v_a_means_diag_buf alloc (5 f32): {e}")))?;
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// SP17 Phase 3.1 (2026-05-08): per-branch A_var EMA producer.
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// Cold-path (epoch boundary) — one launch per HEALTH_DIAG emit.
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// 4 blocks × 256 threads; block tree-reduce per
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// `feedback_no_atomicadd`. Pearl-A bootstrap on slots 474..478.
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let sp17_a_var_ema_module = stream.context()
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.load_cubin(SP17_A_VAR_EMA_CUBIN.to_vec())
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.map_err(|e| MLError::ModelError(format!("sp17 a_var_ema cubin: {e}")))?;
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let sp17_a_var_ema_kernel = sp17_a_var_ema_module
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.load_function("sp17_a_var_ema_update")
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.map_err(|e| MLError::ModelError(format!("sp17_a_var_ema_update: {e}")))?;
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// SP14 Layer C Phase C.1 (2026-05-08): α-machinery cubin loads
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// (alpha_grad_compute, gradient_hack_detect, sp14_scale_wire_col)
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// deleted atomically with the kernel files. Coupling A
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@@ -24355,6 +24493,7 @@ impl GpuDqnTrainer {
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// producer launched at HEALTH_DIAG emit only.
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sp17_v_a_means_diag_kernel,
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sp17_v_a_means_diag_buf,
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sp17_a_var_ema_kernel,
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sp14_dir_concat_qaux_kernel,
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sp14_dir_qaux_concat_scratch,
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// SP14 backward dX scratch — column-SH2 wire is dropped at
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