plan(ml-backtesting): deployability-sweep parallelism implementation plan

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7-task atomic ladder (P1-P7) implementing spec d646c1eb3. Each task
maps to one commit per feedback_no_partial_refactor:

  P1: Per-backtest sim parameter arrays (BatchedSimConfig + kernel ABI)
  P2: seed_inflight_limits_batched kernel (replaces host roundtrip)
  P3: detect_close_transitions_batched kernel (replaces close-detect loop)
  P4: Threshold gate + per-fill cost integration
  P5: CUDA Graph capture of forward_only (1.3× forward target)
  P6: Batched-cell sweep schema + 140-variant runner
  P7: 3-pod scale + final verdict

Measurement gates per §9 of the spec (P2 ≤90s, P5 ≤60s, P6 ≤30min,
P7 ≤60min target / ≤120min firm). Stride=8 fallback activated at P6
if measurement misses by >20%.

Self-review confirms all 13 spec sections covered, no placeholders,
type consistency across tasks.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

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jgrusewski

2026-05-19 16:39:17 +02:00

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