diff --git a/crates/ml/build.rs b/crates/ml/build.rs
index 5e5a521a9..82c777436 100644
--- a/crates/ml/build.rs
+++ b/crates/ml/build.rs
@@ -856,29 +856,16 @@ fn main() {
         // Block-tree-reduce (no atomicAdd) per `feedback_no_atomicadd.md`.
         // Per-epoch boundary launch.
         "dd_saturation_floor_update_kernel.cu",
-        // Class A audit-fix Batch 4-B (2026-05-08, Item 4): adaptive
-        // MIN_HOLD_TEMPERATURE producer. Single-thread cold-path kernel
-        // that reads `ISV[AUX_DIR_ACC_SHORT_EMA_INDEX=373]` (sp13 fast
-        // EMA of binary directional accuracy), maps it to a [5, 50]
-        // temperature via `temp = TEMP_MIN + (TEMP_MAX − TEMP_MIN) ×
-        // skill` where `skill = clamp((short_ema − 0.5)/0.5, 0, 1)`,
-        // and slow-EMA-blends into
-        // `ISV[MIN_HOLD_TEMPERATURE_ADAPTIVE_INDEX=460]`. Pearl-A
-        // first-observation bootstrap (sentinel 50.0 matches the
-        // deleted MIN_HOLD_TEMPERATURE_START=50 anchor for bit-identical
-        // cold-start under both regimes); α=0.05 mid-cadence EMA
-        // thereafter. Replaces the deleted epoch-driven schedule
-        // `T_end + (T_start − T_end) × exp(-epoch / decay)` (formerly
-        // state_layout.cuh::MIN_HOLD_TEMPERATURE_{START, END, DECAY} +
-        // training_loop.rs::min_hold_temperature_for_epoch). Decouples
-        // temperature from epoch number — when WR plateaus, the old
-        // schedule pinned LOW temp (sharp) at end of training (max
-        // punishment when most needed forgiveness); the signal-driven
-        // version reacts to actual realized skill. Per
-        // `feedback_no_legacy_aliases.md` the legacy schedule is deleted
-        // atomically. Bounds [5, 50] are Category-1 dimensional safety
-        // floors per `feedback_isv_for_adaptive_bounds.md`. Per-epoch
-        // boundary launch (same cadence as P0-A REWARD_POS_CAP).
+        // min_hold_temperature_update_kernel.cu — reads
+        // ISV[HOLD_RATE_OBSERVED_EMA_INDEX=382] and
+        // ISV[HOLD_RATE_TARGET_INDEX=381], maps overrun
+        // `clamp(max(0, observed - target) / max(target, 0.01), 0, 1)`
+        // to a [TEMP_MIN=5, TEMP_MAX=50] temperature, blends via
+        // Pearl-A bootstrap + Welford EMA α=0.05, writes to
+        // ISV[MIN_HOLD_TEMPERATURE_ADAPTIVE_INDEX=460]. Per SP16 Phase 1
+        // (revised) — supersedes the prior slot-373 dir-acc-skill mapping;
+        // see docs/dqn-wire-up-audit.md § "SP16 Phase 1 (revised)" for
+        // rationale.
         "min_hold_temperature_update_kernel.cu",
         // SP14 Layer C Phase C.6 (2026-05-08): h_s2_aux RMS EMA producer.
         // Single-block 256-thread kernel computing RMS = sqrt(mean(x²))
diff --git a/crates/ml/tests/sp14_oracle_tests.rs b/crates/ml/tests/sp14_oracle_tests.rs
index 1b567830a..d342ba751 100644
--- a/crates/ml/tests/sp14_oracle_tests.rs
+++ b/crates/ml/tests/sp14_oracle_tests.rs
@@ -1895,12 +1895,6 @@ mod sp16_phase1_min_hold_temperature_gpu {
              expected {}, got {temp}",
             MIN_HOLD_TEMPERATURE_MAX
         );
-        // Belt-and-braces: also verify the slot escaped the sentinel.
-        assert!(
-            (temp - SENTINEL_MIN_HOLD_TEMPERATURE).abs() < 1e-4
-                || temp != SENTINEL_MIN_HOLD_TEMPERATURE,
-            "Producer must have written slot 460 (sentinel-only would imply early-return)"
-        );
     }
 
     /// SP16 Phase 1 (revised) — Test 2: at-target → temp LOW (strict).