From 40871595e8a3f40eade3d1d5ab9af96d2a987010 Mon Sep 17 00:00:00 2001 From: jgrusewski Date: Sun, 3 May 2026 01:39:31 +0200 Subject: [PATCH] =?UTF-8?q?sp7(trainer):=20T5=20polish=20=E2=80=94=20renam?= =?UTF-8?q?e=20cql=5Fdev=20=E2=86=92=20cql=5Fsx=5Fdev=20+=20base=5Fwiener?= =?UTF-8?q?=20annotation?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Two clarity-only edits surfaced by code review: - Rename `cql_dev` → `cql_sx_dev` in `launch_loss_balance_controller`. The launcher uses `grad_decomp_result_dev_ptr + 6 * f32_size` which is the cql_sx (post-budget) slot, not cql (pre-budget at offset 3). The variable name now reflects that. - Add `// 213` inline annotation on `base_wiener_offset` to match the pattern used by all four sibling launchers (lines 11062, 11194, 11303). No semantic impact — pointer arithmetic and parameter order unchanged. Co-Authored-By: Claude Opus 4.7 (1M context) --- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs | 10 +++++----- docs/dqn-wire-up-audit.md | 3 +++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs b/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs index 8254f8feb..16a4d2caa 100644 --- a/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs +++ b/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs @@ -11363,9 +11363,9 @@ impl GpuDqnTrainer { // We use cql_sx (post-budget delta) for ratio parity with what landed // in grad_buf. let f32_size = std::mem::size_of::() as u64; - let iqn_dev = self.grad_decomp_result_dev_ptr + 0 * f32_size; - let cql_dev = self.grad_decomp_result_dev_ptr + 6 * f32_size; - let c51_dev = self.grad_decomp_result_dev_ptr + 9 * f32_size; + let iqn_dev = self.grad_decomp_result_dev_ptr + 0 * f32_size; + let cql_sx_dev = self.grad_decomp_result_dev_ptr + 6 * f32_size; + let c51_dev = self.grad_decomp_result_dev_ptr + 9 * f32_size; // Step 1: producer kernel. let flatness_isv_base_i32 = FLATNESS_BASE as i32; @@ -11386,7 +11386,7 @@ impl GpuDqnTrainer { self.stream .launch_builder(&self.loss_balance_controller_kernel) .arg(&iqn_dev) - .arg(&cql_dev) + .arg(&cql_sx_dev) .arg(&c51_dev) .arg(&isv_dev) .arg(&flatness_isv_base_i32) @@ -11413,7 +11413,7 @@ impl GpuDqnTrainer { // Step 2: apply_pearls_ad_kernel × 24 — one per ISV output slot. // Wiener offset: (SP4_PRODUCER_COUNT + (isv_slot - SP5_SLOT_BASE)) * 3. - let base_wiener_offset = SP4_PRODUCER_COUNT as i32 * 3; + let base_wiener_offset = SP4_PRODUCER_COUNT as i32 * 3; // 213 for (isv_base, scratch_base) in [ (BUDGET_CQL_BASE, SCRATCH_LB_BUDGET_CQL), diff --git a/docs/dqn-wire-up-audit.md b/docs/dqn-wire-up-audit.md index 273d8d326..a669fa78a 100644 --- a/docs/dqn-wire-up-audit.md +++ b/docs/dqn-wire-up-audit.md @@ -3901,6 +3901,9 @@ extended. No producer kernel yet — that arrives in the next commit. constants + `launch_loss_balance_controller(&self)` fn (the producer kernel launch + 24 apply_pearls_ad chain). Producer-only — call site in training_loop.rs lands at T7 (atomic with consumer + stale doc). + T5 polish landed (commit ⟨pending⟩) — `cql_dev` renamed to `cql_sx_dev` + for clarity (the launcher uses the cql_sx post-budget delta) + `// 213` + annotation on `base_wiener_offset` for sibling-launcher consistency. - T6: Pearl 2 contract change (drop CQL/C51/ENS args). - T7: launch site + sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7) + stale doc. - T9–T10: smoke + 50-epoch verification.