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feat(sp20): register 10 ISV slots in StateResetRegistry

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Sentinel = 0.0 per pearl_first_observation_bootstrap. First observation
of each EMA replaces the sentinel directly, no blending.

Slots [510..520):
- loss_cap (510): adaptive loss cap for reward clamp
- alpha_ema (511): Wiener-α EMA for loss_cap producer
- wr_ema (512): win-rate EMA driving loss_cap adaptive ramp
- hold_cost_scale (513): hold penalty cost multiplier
- target_hold_pct (514): hold-engagement target
- hold_pct_ema (515): hold-engagement EMA
- hold_reward_ema (516): hold-action reward EMA
- n_step (517): multi-step TD horizon adapter
- aux_conf_threshold (518): auxiliary task confidence threshold
- aux_gate_temp (519): auxiliary task gating temperature
This commit is contained in:
jgrusewski
2026-05-09 18:17:38 +02:00
parent f5eed1fa79
commit 4249ebc961
2 changed files with 101 additions and 1 deletions
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docs/isv-slots.md
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@@ -497,7 +497,8 @@ work stream and establishes the slot base for upcoming components:
**Files touched (Pre.2 atomic):**
- `crates/ml/src/cuda_pipeline/sp14_isv_slots.rs` — 10 `pub const *_INDEX` constants (at the top level, before the test module) + SP20_SLOT_BASE (510) + SP20_SLOT_END (520) constants + 1 regression test (`sp20_isv_slots_reserved_510_to_520`) verifying all 10 slot indices and ISV_TOTAL_DIM=520
- `crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs` — `ISV_TOTAL_DIM: 510 → 520`, `layout_fingerprint_seed()` extended with all 10 slot `name=index` entries + `ISV_TOTAL_DIM=520` marker (forces fingerprint hash bump → pre-SP20 checkpoints invalidated, greenfield OK)
- `crates/ml/src/trainers/dqn/state_reset_registry.rs` — Task Pre.3 registers all 10 SP20 slots with `FoldReset` category and sentinel=0.0 per `pearl_first_observation_bootstrap`; includes unit test `sp20_isv_slots_registered_with_sentinel_zero`
**Producers/consumers status:** Pre.2 lands the slot reservation only; all 10 slots are zero-initialized until subsequent SP20 phases land producers (per-epoch ISV seeds + GPU kernels) and consumer migration. Mirrors the SP4/SP5/SP11/SP15 pre-allocation pattern.
**Producers/consumers status:** Pre.2 lands the slot reservation only; Pre.3 registers in state reset machinery; all 10 slots are zero-initialized until subsequent SP20 phases land producers (per-epoch ISV seeds + GPU kernels) and consumer migration. Mirrors the SP4/SP5/SP11/SP15 pre-allocation pattern.
**ISV_TOTAL_DIM:** 510 → 520 (Pre.2 adds 10 slots).