feat(sp22): H6 Phase 3 — Phase A foundation (WIP checkpoint, additive)

Phase A of the SP22 H6 Phase 3 implementation runbook
(docs/plans/2026-05-13-sp22-h6-phase3-alpha-beta-runbook.md). Purely
additive: new ISV slots + new kernel files + build.rs registration
+ state_reset_registry entries. Nothing in the running training or
eval pipeline consumes this infrastructure yet — the existing
6-component contract is untouched. Phase A is committable as a clean
WIP foundation; Phases B-F (7-component contract migration, α
plumbing, A2 eval-side wiring, verification, smoke) resume in a
future session.

Files
─────
- crates/ml/src/cuda_pipeline/sp22_isv_slots.rs (NEW)
    REWARD_AUX_ALIGN_EMA_INDEX = 536 — EMA of 7th reward component
    SP22_AUX_ALIGN_SCALE_INDEX  = 537 — SP11-controller scale_β

- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs
    ISV_TOTAL_DIM bumped 536 → 538 (SP22 H6 Phase 3 +2 slots)
    Layout fingerprint extended with SLOT_536 + SLOT_537 entries

- crates/ml/src/cuda_pipeline/mod.rs
    pub mod sp22_isv_slots

- crates/ml/src/trainers/dqn/state_reset_registry.rs
    sp22_reward_aux_align_ema (FoldReset, sentinel 0)
    sp22_aux_align_scale       (FoldReset, sentinel 0)

- crates/ml/src/cuda_pipeline/aux_to_q_dir_bias_kernel.cu (NEW)
    α forward: Q_dir[b, a] += W_aux[a] * state_121[b]
    Reads state_121 from encoder INPUT (batch_states), bypassing
    the cold encoder weight for slot 121. No atomicAdd, no host
    branches, capture-safe.

- crates/ml/src/cuda_pipeline/aux_to_q_dir_bias_backward_kernel.cu (NEW)
    Two kernels in one .cu:
    - aux_to_q_dir_bias_backward_dw: per-action block tree-reduce
      computing dW[a] = Σ_b state_121[b] * dq_dir[b, a]
    - aux_to_q_dir_bias_backward_dstate: per-sample sum
      dstate_121[b] += Σ_a W[a] * dq_dir[b, a] (option-(i) gradient
      routing: both α and encoder paths get signal)

- crates/ml/build.rs
    Both new cubins registered in kernels_with_common (compiled
    successfully by nvcc; cubins exist at OUT_DIR/aux_to_q_dir_bias_*.cubin)

- docs/dqn-wire-up-audit.md
    Phase A entry documenting the checkpoint + remaining-work
    breakdown for next session.

Verification
────────────
- cargo check -p ml --features cuda: 0 errors, 21 pre-existing
  warnings (Phase 2 baseline parity)
- nvcc compiles both new cubins (3.6 KB fwd, 10.6 KB bwd)
- No runtime impact: no consumer wires the new infrastructure yet

Resumes in
──────────
Future session executes Phases B-F per the runbook:
- B: 11 tasks — 7-component contract migration cascade
- C: 1 task — α collector rollout-side wiring
- D: 7 tasks — A2 eval-side aux trunk + α + state-gather
- E: 7 tasks — verification gates
- F: 5 tasks — audit doc append + atomic commit (incl. this Phase A
  + Phase B-F changes) + push + smoke + verdict

Estimated remaining: ~28-43 hr engineering + ~37 min smoke wall-clock.

Phase B partial work (300-line diff for experience_kernels.cu + reward_component_ema_kernel.cu — 7-stride migration + β producer + preamble update) saved at /tmp/sp22-h6-phase3-b-partial.patch (local-only).

Refs
────
- docs/plans/2026-05-12-sp22-h6-phase3-alpha-beta.md (spec)
- docs/plans/2026-05-13-sp22-h6-phase3-alpha-beta-runbook.md (runbook)
- pearl_no_partial_refactor (Phase A is additive; safe to commit alone)
- pearl_no_atomicadd (backward block tree-reduce, no atomics)
- pearl_no_host_branches_in_captured_graph (kernel capture-safety)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

docs/dqn-wire-up-audit.md

@@ -16667,3 +16667,79 @@ combining into one atomic plan.
 If combined α+β fails: amplitude scaling or per-dim adaptive LR are
 fallbacks; the action-distribution bit-identity finding suggests the
 problem is structural, not numerical.
+
+### Phase 3 Phase A foundation (2026-05-13) — WIP checkpoint, additive
+
+Phase A of the H6 Phase 3 implementation runbook
+(`docs/plans/2026-05-13-sp22-h6-phase3-alpha-beta-runbook.md`) lands
+as a purely additive foundation. **No consumer wires the new
+infrastructure yet** — the existing 6-component reward decomposition
+contract is unchanged. Phase A is committable as a clean checkpoint;
+Phases B–F (7-component contract migration, α plumbing, A2 eval-side
+wiring, verification gates, atomic-commit + smoke + verdict) resume
+in a future session.
+
+Phase A files (7):
+
+- `crates/ml/src/cuda_pipeline/sp22_isv_slots.rs` (new) —
+  `REWARD_AUX_ALIGN_EMA_INDEX = 536`, `SP22_AUX_ALIGN_SCALE_INDEX = 537`.
+- `crates/ml/src/cuda_pipeline/mod.rs` — `pub mod sp22_isv_slots`.
+- `crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs` — `ISV_TOTAL_DIM`
+  bumped 536 → 538; layout fingerprint extended with the two new
+  `SLOT_536_REWARD_AUX_ALIGN_EMA` + `SLOT_537_SP22_AUX_ALIGN_SCALE`
+  entries.
+- `crates/ml/src/trainers/dqn/state_reset_registry.rs` — two new
+  `RegistryEntry` rows (FoldReset, sentinel 0).
+- `crates/ml/src/cuda_pipeline/aux_to_q_dir_bias_kernel.cu` (new) —
+  α forward: `Q_dir[b, a] += W_aux[a] * state_121[b]`. Reads
+  `state_121` from the encoder INPUT (`batch_states`), bypassing the
+  cold encoder weight for slot 121.
+- `crates/ml/src/cuda_pipeline/aux_to_q_dir_bias_backward_kernel.cu`
+  (new) — two kernels in one `.cu`: `aux_to_q_dir_bias_backward_dw`
+  (per-action block tree-reduce; no atomicAdd) and
+  `aux_to_q_dir_bias_backward_dstate` (per-sample sum accumulating
+  into encoder-input gradient slot 121, option-(i) gradient routing
+  per spec).
+- `crates/ml/build.rs` — both new cubins registered in
+  `kernels_with_common`.
+
+Verification (Phase A, partial — final gates run at Phase F):
+
+| Gate | Result |
+|---|---|
+| `cargo check -p ml --features cuda` | 0 errors, 21 pre-existing warnings |
+| nvcc cubins | both compile cleanly (3.6 KB fwd, 10.6 KB bwd) |
+| No new consumer wiring | confirmed; running code identical to pre-Phase-A |
+
+Remaining work for Phase 3 verdict (~28–43 hr engineering):
+
+- **Phase B** (11 tasks): 7-component contract migration cascade
+  across `experience_kernels.cu`, `reward_component_ema_kernel.cu`,
+  `reward_decomp_diag_kernel.cu`,
+  `reward_component_mag_ratio_compute_kernel.cu`,
+  `reward_subsystem_controller_kernel.cu`, `health_diag_kernel.cu`,
+  `gpu_experience_collector.rs`, `gpu_dqn_trainer.rs`,
+  `reward_component_monitor.rs`, `training_loop.rs`.
+- **Phase C** (1 task): α collector rollout-side captured-graph
+  wiring.
+- **Phase D** (7 tasks): A2 eval-side — aux trunk weight loading,
+  per-window `prev_aux_dir_prob` buffer, per-step aux trunk forward
+  + softmax-to-per-env launch, α post-Q_dir bias launch, non-NULL
+  `prev_aux_dir_prob.raw_ptr()` to all 3 backtest state-gather
+  launchers, W/aux-trunk ptr sharing trainer ↔ evaluator.
+- **Phase E** (7 tasks): verification gates (cargo check,
+  gpu_backtest_validation, compute-sanitizer, captured-graph
+  integrity, α weight movement, 7-component contract sanity, A2
+  eval activity).
+- **Phase F** (5 tasks): audit doc append (Phase B–F outcomes),
+  single atomic commit covering all Phase B–F changes (per
+  `feedback_no_partial_refactor`), push, smoke dispatch
+  (`./scripts/argo-train.sh dqn --baseline --branch sp20-aux-h-fixed
+  --epochs 3 --gpu-pool ci-training-l40s`), verdict monitoring.
+
+Phase B partial work (file diffs for `experience_kernels.cu` +
+`reward_component_ema_kernel.cu` — 7-component stride migration +
+β producer + EMA kernel preamble update) saved at
+`/tmp/sp22-h6-phase3-b-partial.patch` (300 lines, local-only). Next
+session can apply if useful as a starting point, or discard and
+re-derive directly from the runbook.