feat(sp22): H6 Phase 3 α Phase C1 — collector W ptr setter

Wires the trainer's `w_aux_to_q_dir [4]` device pointer into the
GpuExperienceCollector so rollout-time action selection sees the
active atom-shift for the direction branch.

Changes:
- gpu_experience_collector.rs: new field aux_w_to_q_dir_dev_ptr (u64,
  default 0) + setter set_aux_w_to_q_dir_ptr(). Both rollout launchers
  (compute_expected_q + quantile_q_select) now pass W ptr + exp_states_f32
  + STATE_DIM_PADDED instead of NULL placeholders. NULL-safe via the
  kernels' existing aux_shift_active gating.
- gpu_dqn_trainer.rs: w_aux_to_q_dir field promoted to pub(crate) for
  cross-module access via raw_ptr().
- trainers/dqn/trainer/training_loop.rs: new wire-up block after SP15
  warm-count setter, mirroring the established setter pattern. NULL-safe
  on test scaffolds where fused_ctx or collector is absent.

End-state — rollout activation:
- compute_expected_q + quantile_q_select now return shifted E[Q] /
  quantile-blends per direction action during rollout.
- With trainer's W trained each step (Step 8+11 Adam), the rollout
  policy's direction-action distribution actively reflects the learned
  aux→policy coupling. state_121's per-env value drives a per-(env, action)
  bias of magnitude W[a] (≤0.5 initial prior, learned thereafter).

Verification: cargo check -p ml --lib clean (0 errors, 21 pre-existing
warnings).

Trainer + collector now smoke-ready end-to-end for the trainer/rollout
side. Eval-side activation pending Phase D.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs

@@ -6924,7 +6924,7 @@ pub struct GpuDqnTrainer {
     /// `[Short, Hold, Long, Flat]` — domain belief that aux conviction ×
     /// position-sign biases toward aligned trades. Adam refines from
     /// the prior via projection backward in c51_grad_kernel.
-    w_aux_to_q_dir: cudarc::driver::CudaSlice<f32>,
+    pub(crate) w_aux_to_q_dir: cudarc::driver::CudaSlice<f32>,
     /// SP22 H6 Phase 3 α — Adam first moment (m) for `w_aux_to_q_dir`.
     /// Same shape [b0_size=4] f32; zero-init per Adam convention.
     adam_m_w_aux: cudarc::driver::CudaSlice<f32>,