From 6e479c55c7af3774059bdaacc40c455ec8e91335 Mon Sep 17 00:00:00 2001
From: jgrusewski <jgrusewski@localhost>
Date: Sun, 3 May 2026 09:54:49 +0200
Subject: [PATCH] =?UTF-8?q?sp7(state):=20T2=20bug-fix=20=E2=80=94=20add=20?=
 =?UTF-8?q?4=20missing=20reset=5Fnamed=5Fstate=20dispatch=20arms?=
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T2 (commit aa2854017) registered 4 SP7 ResetEntries:
  sp7_lb_diff_var_cql    → ISV[297..301)
  sp7_lb_sample_var_cql  → ISV[301..305)
  sp7_lb_diff_var_c51    → ISV[305..309)
  sp7_lb_sample_var_c51  → ISV[309..313)

But never added their dispatch arms in `reset_named_state`. At fold
boundary, the dispatcher panics with "unknown name 'sp7_lb_diff_var_cql'"
because every FoldReset entry must have a matching match arm.

Same shape as bug #281 (SP5 Layer A bug-fix). Surfaced by the SP7 T7
local sanity smoke (test_magnitude_distribution).

The 4 new arms mirror the existing `sp5_budget_cql` / `sp5_budget_c51`
template — `for b in 0..4 { write_isv_signal_at(BASE + b, 0.0); }`.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
---
 .../src/trainers/dqn/trainer/training_loop.rs | 36 +++++++++++++++++++
 docs/dqn-wire-up-audit.md                     |  5 +++
 2 files changed, 41 insertions(+)

diff --git a/crates/ml/src/trainers/dqn/trainer/training_loop.rs b/crates/ml/src/trainers/dqn/trainer/training_loop.rs
index 9d635a7c1..484970826 100644
--- a/crates/ml/src/trainers/dqn/trainer/training_loop.rs
+++ b/crates/ml/src/trainers/dqn/trainer/training_loop.rs
@@ -6534,6 +6534,42 @@ impl DQNTrainer {
                     }
                 }
             }
+            // SP7 Task 7 (2026-05-03): loss-balance controller per-branch
+            // Wiener-state EMAs. Sentinel 0 at fold boundary so the
+            // controller's `old_budget < EPS_DIV` cold-start branch fires
+            // and α resets cleanly when budgets re-bootstrap.
+            "sp7_lb_diff_var_cql" => {
+                if let Some(ref fused) = self.fused_ctx {
+                    use crate::cuda_pipeline::sp5_isv_slots::LB_DIFF_VAR_CQL_BASE;
+                    for b in 0..4 {
+                        fused.trainer().write_isv_signal_at(LB_DIFF_VAR_CQL_BASE + b, 0.0);
+                    }
+                }
+            }
+            "sp7_lb_sample_var_cql" => {
+                if let Some(ref fused) = self.fused_ctx {
+                    use crate::cuda_pipeline::sp5_isv_slots::LB_SAMPLE_VAR_CQL_BASE;
+                    for b in 0..4 {
+                        fused.trainer().write_isv_signal_at(LB_SAMPLE_VAR_CQL_BASE + b, 0.0);
+                    }
+                }
+            }
+            "sp7_lb_diff_var_c51" => {
+                if let Some(ref fused) = self.fused_ctx {
+                    use crate::cuda_pipeline::sp5_isv_slots::LB_DIFF_VAR_C51_BASE;
+                    for b in 0..4 {
+                        fused.trainer().write_isv_signal_at(LB_DIFF_VAR_C51_BASE + b, 0.0);
+                    }
+                }
+            }
+            "sp7_lb_sample_var_c51" => {
+                if let Some(ref fused) = self.fused_ctx {
+                    use crate::cuda_pipeline::sp5_isv_slots::LB_SAMPLE_VAR_C51_BASE;
+                    for b in 0..4 {
+                        fused.trainer().write_isv_signal_at(LB_SAMPLE_VAR_C51_BASE + b, 0.0);
+                    }
+                }
+            }
             "sp5_pnl_aggregation" => {
                 // Layer D Task D1: zero ISV[286..290) — total/mean/var/max_dd —
                 // so the new fold's first `launch_sp5_pnl_aggregation` triggers
diff --git a/docs/dqn-wire-up-audit.md b/docs/dqn-wire-up-audit.md
index 9b79e7f65..4ec1407d8 100644
--- a/docs/dqn-wire-up-audit.md
+++ b/docs/dqn-wire-up-audit.md
@@ -3924,4 +3924,9 @@ extended. No producer kernel yet — that arrives in the next commit.
   T7 polish landed (commit ⟨pending⟩) — 2 stale docstrings around
   compute_adaptive_budgets (header floors + last_ens_budget_eff Pearl-2
   attribution) corrected to reflect the SP7 sentinel-aware bootstrap contract.
+  T7 bug-fix landed (commit ⟨pending⟩) — added 4 reset_named_state dispatch
+  arms for sp7_lb_diff_var_cql / _sample_var_cql / _diff_var_c51 /
+  _sample_var_c51 (T2 introduced the registry entries but missed dispatch,
+  causing fold-boundary panic "unknown name 'sp7_lb_diff_var_cql'"; same
+  shape as bug #281). Mirrors existing `sp5_budget_*` arms.
 - T9–T10: smoke + 50-epoch verification.