From 6e7690d82dea46c809ca5bf7e41a5fd3c4c096e1 Mon Sep 17 00:00:00 2001 From: jgrusewski Date: Sun, 3 May 2026 00:58:30 +0200 Subject: [PATCH] =?UTF-8?q?sp7(isv):=20T1=20polish=20=E2=80=94=20alignment?= =?UTF-8?q?=20+=20audit-doc=20stub=20softening?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Minor item 1: Remove extra column-alignment spaces from the 4 SP7 constants (LB_DIFF_VAR_CQL_BASE, LB_SAMPLE_VAR_CQL_BASE, LB_DIFF_VAR_C51_BASE, LB_SAMPLE_VAR_C51_BASE) so they match the no-alignment style of surrounding SP5 constants (BUDGET_C51_BASE etc.). Constant values (297, 301, 305, 309) and inline comments are unchanged. Minor item 2: Soften the Fix 31 T7 stub in dqn-wire-up-audit.md from "sentinel-aware consumer" to "sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7)" so the audit entry does not forward-reference specific constant names before they land. Cargo check: clean (zero warnings, zero errors). Co-Authored-By: Claude Opus 4.7 (1M context) --- crates/ml/src/cuda_pipeline/sp5_isv_slots.rs | 4 ++-- docs/dqn-wire-up-audit.md | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/crates/ml/src/cuda_pipeline/sp5_isv_slots.rs b/crates/ml/src/cuda_pipeline/sp5_isv_slots.rs index e815ac1a2..6e1693723 100644 --- a/crates/ml/src/cuda_pipeline/sp5_isv_slots.rs +++ b/crates/ml/src/cuda_pipeline/sp5_isv_slots.rs @@ -175,9 +175,9 @@ pub const LOW_DD_RATIO_INDEX: usize = 296; // producer scratch buffer; `apply_pearls_ad_kernel` smooths them into // these slots — same Pearl A sentinel-bootstrap + Pearl D Wiener-EMA // as every other SP5 producer. -pub const LB_DIFF_VAR_CQL_BASE: usize = 297; // [4] (candidate_cql − old_cql)² EMA +pub const LB_DIFF_VAR_CQL_BASE: usize = 297; // [4] (candidate_cql − old_cql)² EMA pub const LB_SAMPLE_VAR_CQL_BASE: usize = 301; // [4] (cql_norm)² EMA -pub const LB_DIFF_VAR_C51_BASE: usize = 305; // [4] (candidate_c51 − old_c51)² EMA +pub const LB_DIFF_VAR_C51_BASE: usize = 305; // [4] (candidate_c51 − old_c51)² EMA pub const LB_SAMPLE_VAR_C51_BASE: usize = 309; // [4] (c51_norm)² EMA pub const SP5_SLOT_END: usize = 313; diff --git a/docs/dqn-wire-up-audit.md b/docs/dqn-wire-up-audit.md index d61faf754..e1efd28bb 100644 --- a/docs/dqn-wire-up-audit.md +++ b/docs/dqn-wire-up-audit.md @@ -3886,5 +3886,5 @@ extended. No producer kernel yet — that arrives in the next commit. - T4: build.rs cubin manifest. - T5: trainer struct + launcher fn. - T6: Pearl 2 contract change (drop CQL/C51/ENS args). -- T7: launch site + sentinel-aware consumer + stale doc. +- T7: launch site + sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7) + stale doc. - T9–T10: smoke + 50-epoch verification.