feat(sp21): T2.2 Phase 5+6 combined — E6/E7 signal-driven PER alpha scaling (atomic)

Wires E6 (compute_winner_indices) + E7 (compute_hindsight_labels)
outputs into the PER priority update kernel via signal-driven ISV
slots. Phases 5 and 6 combined into one atomic commit per
feedback_no_deferrals_for_complementary_fixes — both attack the
same consumer kernel (per_update_pa) with non-overlapping refactor
scopes (E6 contributes one ISV-mediated scalar, E7 contributes
another, kernel composes both into alpha_boost).

Plan revision (briefed and accepted 2026-05-11):
- E6's literal Vec<usize> of val bar indices CANNOT directly bump
  training-PER priorities — val and training have separate coord
  systems (no bar-index → buffer-slot mapping).
- E7's true synthetic injection requires val state retention
  infrastructure (n_windows × max_len × state_dim scratch buffer)
  — significant scope expansion deferred to Phase 6.5.
- The MEANINGFUL signal in both phases is scalar aggregations of
  the per-trade tape: E6 winner concentration (top-decile-mean
  P&L / all-mean P&L) and E7 hindsight magnitude (mean
  |counterfactual_pnl|). Both compose multiplicatively into
  per_update_pa's alpha_eff.

ISV slot allocation:
- WINNER_CONCENTRATION_INDEX = 525
- HINDSIGHT_MAGNITUDE_INDEX = 526
- ISV_TOTAL_DIM 525 → 527 (bus extension)
- Layout fingerprint adds 2 SLOT entries
- Compile-time test asserts SP21_SLOT_END (527) ≤ ISV_TOTAL_DIM

Signal semantics:
- winner_concentration: top_decile_mean_pnl / max(all_mean_pnl, EPS).
  > 1.0 = top decile dominates; ≈ 1.0 = uniform; ≤ 0 → 0.0 sentinel
  (losing strategy, signal ill-defined).
- hindsight_magnitude: mean(|counterfactual_pnl|). Higher = larger
  missed opportunities.
- Cold start: both at 0.0 sentinel; kernel short-circuits to
  alpha_eff = alpha (no-op).

ABI surgery (minimal):
- per_update_pa: ONE new arg `const float* __restrict__ isv_signals`
  at end. NULL-tolerant. Reads slots 525/526 device-side, composes
  boost_delta (bounded [0, 0.4]), applies alpha_eff = alpha + delta.
- update_priorities_gpu launcher: passes existing
  self.isv_signals_dev_ptr (already on struct, settable via
  set_isv_signals_ptr — same infra per_insert_pa uses for
  recovery_oversample). Zero new public API.

Producer wireup:
- enrichment.rs: 2 new helpers (compute_winner_concentration,
  compute_hindsight_magnitude); EnrichmentResult gains 2 fields
  (winner_concentration, hindsight_magnitude); run_enrichments
  populates both; log line extended.
- training_loop.rs: post-enrichment block writes both ISV slots
  via fused.trainer().write_isv_signal_at.

Files changed:
- crates/ml/src/cuda_pipeline/sp21_isv_slots.rs: +2 slot consts
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump
  + fingerprint
- crates/ml-dqn/src/per_kernels.cu: per_update_pa ABI + boost logic
- crates/ml-dqn/src/gpu_replay_buffer.rs: launcher passes ISV ptr
- crates/ml/src/trainers/dqn/trainer/enrichment.rs: 2 helpers + 2
  fields + populate
- crates/ml/src/trainers/dqn/trainer/training_loop.rs: write 2 slots
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry

Verification (passing):
- cargo check -p ml --tests --features cuda: 0 errors
- cargo test -p ml --lib sp21_isv_slots: 3/3
- sp20_aggregate_inputs_test: 12/12
- sp20_phase1_4_wireup_test: 2/2
- sp20_emas_compute_test: 4/4
- sp20_controllers_compute_test: 7/7
- sp21_per_trade_predicted_q_test: 3/3
Total: 34 tests, 0 failures. Behavioral gate (alpha_eff lift on
post-warmup val passes) is the upcoming smoke training run.

Deferred follow-up (Phase 6.5): true E7 hindsight synthetic
experience injection via val state retention + per_insert_pa
extension. Significant infrastructure (n_windows × max_len ×
state_dim scratch + insert API extension). Documented in audit.

After this commit (T2.2 Phases 7-8 + 6.5 deferred):
- Phase 7: E8 curriculum weights → segment sampling
- Phase 8: signal-drive remaining controller GAINS
- Phase 6.5: synthetic hindsight injection (deferred — needs val
  state buffer infrastructure)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs

@@ -2622,7 +2622,7 @@ const ISV_NETWORK_DIM: usize = 23;
 /// (and the C-side mirrors in `state_layout.cuh`). Bump this constant in the
 /// SAME commit that adds the new range, and update `layout_fingerprint_seed`
 /// to register the new slot names.
-pub(crate) const ISV_TOTAL_DIM: usize = 525;  // SP21 Phase 4 adds 4 slots [521..525) for BRANCH_LR_SCALE_{DIR,MAG,ORDER,URGENCY}; Phase 3 added 1 slot [520..521) for Q_CORRECTION
+pub(crate) const ISV_TOTAL_DIM: usize = 527;  // SP21 Phase 5+6 adds 2 slots [525..527) for WINNER_CONCENTRATION + HINDSIGHT_MAGNITUDE (PER alpha scaling); Phase 4 added 4 slots [521..525) for BRANCH_LR_SCALE_*; Phase 3 added 1 slot [520..521) for Q_CORRECTION
 /// Legacy alias preserved for call sites that haven't been audited for the
 /// network-vs-total split. New code should pick `ISV_NETWORK_DIM` (for weight
 /// tensor sizing) or `ISV_TOTAL_DIM` (for the broadcast bus buffer).
@@ -3753,7 +3753,9 @@ const fn layout_fingerprint_seed() -> &'static [u8] {
       SLOT_522_BRANCH_LR_SCALE_MAG=522;\
       SLOT_523_BRANCH_LR_SCALE_ORDER=523;\
       SLOT_524_BRANCH_LR_SCALE_URGENCY=524;\
-      ISV_TOTAL_DIM=525;\
+      SLOT_525_WINNER_CONCENTRATION=525;\
+      SLOT_526_HINDSIGHT_MAGNITUDE=526;\
+      ISV_TOTAL_DIM=527;\
       SP19_PRODUCER_HARDCODED_HORIZON_BLEND=sp19_path_b;\
       SP14_C_AUX_TRUNK_CONTROL_PLANE=sp14_c_phase_1;\
       ALPHA_MACHINERY_DELETED=sp14_c_phase_1;\