feat(sp22-vnext): FoldReset registry entries for B5b/C collector buffers

Two collector-side device buffers used by the K=3 trade-outcome head
were missing FoldReset registry coverage:

  - prev_aux_outcome_probs [alloc_episodes × 3]
    TRUE stale-read risk. Producer writes end-of-step; consumer
    (experience_state_gather) reads start-of-next-step into
    state[121..124). Without FoldReset the new fold's step-0 state
    gather would inject the previous fold's last-step softmax probs
    into the first batch's state slots.

  - exp_aux_to_input_buf [alloc_episodes × 262]
    Cleanliness-only. Concat kernel overwrites all 262 columns every
    step before the K=3 forward reads them, so no steady-state stale-
    read risk. Registered for parity with the rest of the K=3
    pipeline + to satisfy feedback_registry_entries_need_dispatch_
    arms (the pin test asserts every registry entry has a matching
    dispatch arm in reset_named_state).

Both fields promoted to pub(crate) on GpuExperienceCollector so
reset_named_state can reach them. Matching dispatch arms added with
the standard memset_zeros pattern (is_win_per_env / hold_baseline_
buffer style).

Tests: All 10 state_reset_registry tests pass, including the critical
every_fold_and_soft_reset_entry_has_dispatch_arm pin test that walks
the dispatch body and validates parity with registry entries. Full
lib suite 1015/1 (the failing test is the pre-existing
test_dqn_checkpoint_round_trip NoisyLinear flake — pred1/pred2 sign
mismatch surfacing ~30-50% of full-suite runs, documented in
project_sp22_h6_vnext_resume memory as unrelated to this work).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

docs/dqn-wire-up-audit.md

@@ -2,6 +2,43 @@
 
 **Status:** Populated during Plan 1 Task 6 (A.5 orphan audit). Updated on every commit per Invariant 7.
 
+## 2026-05-14 — SP22 H6 vNext: FoldReset registry entries for B5b/C collector buffers
+
+**Branch:** `sp20-aux-h-fixed`. **Builds on:** `4b40710b7` (B5b-2 collector
+trade plan launch).
+
+Two collector-side device buffers used by the K=3 trade-outcome head
+were missing FoldReset registry coverage:
+
+- `prev_aux_outcome_probs` `[alloc_episodes × 3]` — **TRUE stale-read
+  risk.** Producer (`aux_outcome_softmax_to_per_env_kernel`) writes
+  end-of-step; consumer (`experience_state_gather`) reads start-of-
+  next-step into `state[121..124)`. Without FoldReset the new fold's
+  step-0 state gather would inject the previous fold's last-step
+  softmax probs into the first batch's state slots.
+- `exp_aux_to_input_buf` `[alloc_episodes × 262]` — cleanliness-only.
+  Producer (`aux_to_input_concat_kernel`) overwrites all 262 columns
+  every step before the K=3 forward reads them, so no stale-read risk
+  in steady state. Registered for parity with the rest of the K=3
+  pipeline + to satisfy `feedback_registry_entries_need_dispatch_arms`.
+
+Both fields promoted to `pub(crate)` on `GpuExperienceCollector` so
+`reset_named_state` (in `training_loop.rs`) can reach them. Matching
+match arms added with the standard `memset_zeros` dispatch pattern
+(`is_win_per_env` / `hold_baseline_buffer` style).
+
+**Tests:** All 10 `state_reset_registry` tests pass, including the
+critical `every_fold_and_soft_reset_entry_has_dispatch_arm` pin test
+that walks the dispatch body and validates parity with registry
+entries. Lib suite 1015/1 (the failing test is the pre-existing
+`test_dqn_checkpoint_round_trip` NoisyLinear flake — surfaces ~30-50%
+of full-suite runs, unrelated to this commit).
+
+**Touched:** `crates/ml/src/cuda_pipeline/gpu_experience_collector.rs`
+(field visibility + doc-comment), `crates/ml/src/trainers/dqn/state_
+reset_registry.rs` (2 new entries), `crates/ml/src/trainers/dqn/
+trainer/training_loop.rs` (2 new dispatch arms).
+
 ## 2026-05-14 — SP22 H6 vNext Phase B5b-2: collector trade plan forward (asymmetry resolved)
 
 **Branch:** `sp20-aux-h-fixed`. **Depends on:** prior commit `fb9b62a1f`