feat(sp15): scaffold sp15_isv_slots.rs with 46 slots [397..443) — ISV_TOTAL_DIM 396→443
Per spec §4.3 allocation map. Pre-allocates disjoint slot ranges to enable Approach B parallel sub-worktrees without index collisions: - Phase 0.B EGF retune: [397..401) - Phase 1.3 drawdown: [401..407) - Phase 1.2 cost: [407..409) - Phase 1.4 baselines: [409..417) - Phase 3.X-3.5.X teachings + recovery: [417..441) - Phase 3.5 deferred anchors: [441..443) Layout fingerprint extended with all 46 slot names. Pre-SP15 checkpoints will be incompatible (greenfield OK per Q1). Two regression tests verify: (1) every slot < ISV_TOTAL_DIM, (2) layout fingerprint locked at named indices. docs/isv-slots.md gets the SP15 section documenting the allocation map + greenfield sub-worktree plan. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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@@ -426,3 +426,37 @@ values are omitted from the emit (recomputing host-side would violate
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- `let warmup_gate: f32 = 1.0;` and `.arg(&warmup_gate)` from B.4 oracle tests
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**Net result:** EGF gate's warmup behavior now lives entirely in the variance-driven k_aux/k_q sigmoid steepness controller. ISV-signal-driven via slots 388 (var_aux) and 389 (var_q). No hardcoded step counter. Honors `feedback_isv_for_adaptive_bounds`.
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## SP15 — Trader Discipline Recovery (Pre-Phase P.2 reservation, 2026-05-06)
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SP15 Pre-Phase Task P.2 extends `ISV_TOTAL_DIM` from 396 → 443 by reserving 46
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contiguous slots at `[397..443)`. The allocation pre-claims disjoint ranges
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across 3 sub-worktrees (Approach B parallel-dispatch) so Phase 0/1/2A can
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land producers and consumers independently without index collisions.
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**Allocation map (per spec §4.3):**
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| Range | Phase | Purpose |
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|-------|-------|---------|
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| `[397..401)` | Phase 0.B | EGF retune anchors (SCHMITT_HI/LO + VAR_AUX/Q_REF) |
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| `[401..407)` | Phase 1.3 | Drawdown reporting (current/max/recovery_bars/persistence/calmar/dd_pct) |
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| `[407..409)` | Phase 1.2 | Cost kernel (OFI_IMPACT_LAMBDA + COST_PER_BAR_AVG) |
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| `[409..417)` | Phase 1.4 | 8 counterfactual baselines (buyhold/hold-only/random-dir-kelly/naive-momentum/aux-only/mag-quarter-fixed/trail-only/naive-reversion sharpe) |
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| `[417..420)` | Phase 3.1 | r_quality + r_discipline split (ALPHA_SPLIT + grad-norm quality/discipline) |
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| `[420..423)` | Phase 3.3 | Quadratic DD penalty (LAMBDA_DD + DD_THRESHOLD + DD_PENALTY_GRAD_NORM) |
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| `[423..426)` | Phase 3.4 | Regret signal (REGRET_EMA + LAMBDA_REGRET + REGRET_GRAD_NORM) |
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| `[426..430)` | Phase 3.5 | Confidence-aware Hold floor (HOLD_FLOOR_ALPHA/K/EPS0 + ENTROPY_DIST_REF) |
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| `[430..433)` | Phase 3.5.2 | DD asymmetric reward (DD_ASYMMETRY_LAMBDA + R_GAIN_DD_BOOST + DD_DIST_VAR) |
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| `[433..436)` | Phase 3.5.3 | Cooldown gate (K_THRESHOLD + M_BARS + BARS_REMAINING) |
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| `[436..439)` | Phase 3.5.4 | Plasticity injection (FIRED_THIS_FOLD + PERSISTENCE_THRESHOLD + WARM_BARS_REMAINING) |
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| `[439..441)` | Phase 3.5.5 | Recovery curriculum in PER (DD_TRAJECTORY_DECREASING + RECOVERY_OVERSAMPLE_WEIGHT) |
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| `[441..443)` | Phase 3.5 deferred | DD_TRAJECTORY_FLOOR + MEDIAN_STREAK_LENGTH ISV anchors |
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**Files touched (P.2 atomic):**
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- `crates/ml/src/cuda_pipeline/sp15_isv_slots.rs` (new) — 46 `pub const *_INDEX` constants + SP15_SLOT_BASE/END/COUNT + 2 regression tests (`all_sp15_slots_fit_within_isv_total_dim`, `sp15_slot_layout_locked`)
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- `crates/ml/src/cuda_pipeline/mod.rs` — `pub mod sp15_isv_slots;` declaration
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- `crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs` — `ISV_TOTAL_DIM: 396 → 443`, `layout_fingerprint_seed()` extended with all 46 slot `name=index` entries before the `ISV_TOTAL_DIM=443` marker (forces fingerprint hash bump → pre-SP15 checkpoints invalidated, greenfield OK per spec Q1)
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**Greenfield sub-worktrees:** `.worktrees/sp15-phase0-egf-retune`, `.worktrees/sp15-phase1-honest-numbers`, `.worktrees/sp15-phase2a-test-scaffold` rebase onto this commit so each phase's producers/consumers see the slot map.
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**Producers/consumers status:** P.2 lands the slot reservation only; all 46 slots are zero-initialized until per-phase tasks land producers (Phase 0/1/3) and atomic consumer migration (Phase 3.X). Mirrors the SP4/SP5/SP11 pre-allocation pattern.
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