From d704ffd1bca4d98e0a592fa6dfba9266ab3fc3b5 Mon Sep 17 00:00:00 2001 From: jgrusewski Date: Sun, 3 May 2026 01:50:58 +0200 Subject: [PATCH] =?UTF-8?q?docs(dqn):=20T6=20polish=20=E2=80=94=20fix=204?= =?UTF-8?q?=20stale=20Pearl=202=20prose=20references=20in=20gpu=5Fdqn=5Ftr?= =?UTF-8?q?ainer.rs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Four comment/docstring sites still described the pre-SP7 Pearl 2 as writing "20 floats / 5 outputs / c51/cql/ens" after the T6 kernel- signature shrink. Updated to reflect the current 6-arg kernel writing 8 floats (IQN + flatness only) into scratch[115..119, 127..131). Co-Authored-By: Claude Sonnet 4.6 --- .../ml/src/cuda_pipeline/gpu_dqn_trainer.rs | 19 +++++++++---------- docs/dqn-wire-up-audit.md | 4 +++- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs b/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs index 011456050..7e4830635 100644 --- a/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs +++ b/crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs @@ -304,17 +304,16 @@ static SP5_PEARL_1_ATOM_CUBIN: &[u8] = static SP5_PEARL_3_SIGMA_CUBIN: &[u8] = include_bytes!(concat!(env!("OUT_DIR"), "/pearl_3_sigma_kernel.cubin")); -/// SP5 Task A3 (2026-05-01): Pearl 2 per-branch loss budget cubin. +/// SP5 Task A3 + SP7 (2026-05-03): Pearl 2 IQN budget + flatness producer cubin. /// Single-block 4-thread kernel. Reads Q_VAR_PER_BRANCH[b] (Pearl 1's /// q_branch_stats output, ISV[222..226)) + NOISY_SIGMA[b] (Pearl 3 output, /// ISV[210..214)). Computes per-branch flatness = clamp(var_q / (σ²+EPS_DIV), -/// 0, 1) and derives (budget_iqn, budget_c51, budget_cql=0, budget_ens, -/// flatness) per branch. Writes 20 floats to -/// producer_step_scratch_buf[111..131). Chained apply_pearls_ad_kernel -/// (20 single-slot launches) smooths via Pearls A+D into ISV[190..210). +/// 0, 1) and derives (budget_iqn, flatness) per branch. Writes 8 floats to +/// producer_step_scratch_buf[115..119, 127..131). Chained apply_pearls_ad_kernel +/// (8 single-slot launches) smooths via Pearls A+D into ISV[194..198, 206..210). +/// SP7: C51/CQL/ENS budget ownership transferred to loss_balance_controller_kernel. /// Must run AFTER launch_sp5_pearl_1_atom (Q_VAR) AND /// launch_sp5_pearl_3_sigma (NOISY_SIGMA). -/// Layer A only — loss-budget consumer migration deferred to Layer B. static SP5_PEARL_2_BUDGET_CUBIN: &[u8] = include_bytes!(concat!(env!("OUT_DIR"), "/pearl_2_budget_kernel.cubin")); @@ -1069,7 +1068,7 @@ pub const SP5_WIENER_TOTAL_FLOATS: usize = /// 4 floats for pearl_3_sigma output (SCRATCH_PEARL_3_SIGMA=103, sigma × 4 branches) /// 4 floats for pearl_3_sf output (SCRATCH_PEARL_3_SF=107, sigma_fraction × 4 branches) /// Task A3 adds: -/// 20 floats for pearl_2_budget output (5 outputs × 4 branches at [111..131)) +/// 8 floats for pearl_2_budget output (2 outputs × 4 branches; SP7 retired C51/CQL/ENS slots) /// [111..115) reserved-for-future (T6 retired SCRATCH_PEARL_2_C51) /// budget_iqn[4] → SCRATCH_PEARL_2_IQN=115 /// [119..127) reserved-for-future (T6 retired SCRATCH_PEARL_2_CQL/_ENS) @@ -14331,9 +14330,9 @@ impl GpuDqnTrainer { .map_err(|e| MLError::ModelError(format!("pearl_3_sigma_update load: {e}")))? }; - // SP5 Task A3 (2026-05-01): load pearl_2_budget loss budget controller kernel. + // SP5 Task A3 + SP7 (2026-05-03): load pearl_2_budget IQN budget + flatness kernel. // Single-block 4-thread kernel; reads Q_VAR_PER_BRANCH (ISV[222..226)) + - // NOISY_SIGMA (ISV[210..214)) from ISV; writes 20 floats to scratch[111..131). + // NOISY_SIGMA (ISV[210..214)) from ISV; writes 8 floats to scratch[115..119, 127..131). // Must be invoked AFTER pearl_1_atom (Q_VAR) AND pearl_3_sigma (NOISY_SIGMA). let pearl_2_budget_kernel = { let module = stream.context().load_cubin(SP5_PEARL_2_BUDGET_CUBIN.to_vec()) @@ -16082,7 +16081,7 @@ impl GpuDqnTrainer { // [87..103) pearl_1_atom_update (Pearl 1 / A1) // [103..107) pearl_3_sigma σ (Pearl 3 / A2) // [107..111) pearl_3_sigma SF (Pearl 3 / A2) - // [111..131) pearl_2_budget (Pearl 2 / A3 — c51/iqn/cql/ens/flatness) + // [111..131) pearl_2_budget (Pearl 2 / A3 — iqn/flatness; SP7 retired c51/cql/ens) // [131..147) pearl_4 cosine + l2 (auxiliary grad_cosine_sim, A4) // [147..171) pearl_4 β1/β2/ε (Pearl 4 / A4) // [171..199) pearl_5 skew/ex_kurt + IQN τ schedule (A5) diff --git a/docs/dqn-wire-up-audit.md b/docs/dqn-wire-up-audit.md index a3ca42e77..300d5dfc5 100644 --- a/docs/dqn-wire-up-audit.md +++ b/docs/dqn-wire-up-audit.md @@ -3910,6 +3910,8 @@ extended. No producer kernel yet — that arrives in the next commit. apply_pearls smoothing loop shrinks from 5 slot-blocks to 2 (IQN + flatness). SCRATCH_PEARL_2_C51/_CQL/_ENS deleted as orphans per feedback_wire_everything_up. CQL/C51/ENS budget ownership now lives - entirely in the SP7 controller. + entirely in the SP7 controller. T6 polish: 4 stale prose references + (cubin static docstring, scratch layout header, constructor load + comment, scratch map) updated to reflect 8-float / 2-output contract. - T7: launch site + sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7) + stale doc. - T9–T10: smoke + 50-epoch verification.