feat(alpha): Phase E.3 follow-up — C51 distributional Q + Thompson + L1-L10 depth + falsifications

C51 distributional Q-network with GPU Thompson selection borrowed
minimally from production (alpha_c51.cu: forward, project, grad,
expected_q, thompson_select kernels; ~260 lines). Uses Huber
negative-tail compression in projection per production
block_bellman_project_f. Action selection 100% GPU via mapped-pinned
i32 output + __threadfence_system + host volatile read (matches
gpu_training_guard MappedBuffer pattern).

Backtest result (2D sweep, 500 episodes per cell, 30 cells):
  cost=0    C51 +10.41 vs linear-Q -15.72  (+26pt, BEATS Phase 1d.4
                                            no-RL baseline +4.4 by 6pt)
  cost=0.125 C51 -13.81 vs -29.17  (+15pt closes half-tick gap)
Win rate at cost=0 best τ: linear-Q 0.008 → C51 0.552.

Calibration hypothesis vindicated; documented in
memory/pearl_c51_thompson_closed_phase_e3_gap.md.

Also in this commit (Phase E.3 follow-up cleanup):
- --pruned-actions falsified (2.4× worse Sharpe). Documented in
  memory/pearl_action_pruning_falsified.md.
- --real-spread falsified for ES futures (76% of bars at 1-tick floor).
- SnapshotRow bid_l/ask_l extended from [f32; 3] to [f32; 10].
  L4-L10 synthesized in this commit; real MBP-10 peek lands in E.4.A T5.
- docs/isv-slots.md updated per kernel-audit-doc hook requirement.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

docs/isv-slots.md

@@ -756,3 +756,23 @@ Both within 1e-5 tolerance. Anchor slot 544 unchanged after both iterations.
 **Cubin:** `target/release/build/ml-*/out/stacker_threshold_controller.cubin`.
 
 **Wiring:** Task 17 — invoke at each rollout-end in `alpha_dqn_h600_smoke.rs`; initialize slot 544 = 0.08 (8% target trade rate) at training start.
+
+## Phase E.3 follow-up — C51 distributional Q (2026-05-15)
+
+`crates/ml/src/cuda_pipeline/alpha_c51.cu` adds five new kernels for
+distributional Q-learning (forward, project, grad, expected_q,
+thompson_select). None of them WRITE to ISV slots — they're pure
+Q-network compute kernels. They depend on the existing
+controller-driven slot 543 (stacker_threshold) for the GPU Thompson
+selector's confidence gate at inference: the threshold is populated
+into a kernel scalar arg from a host-cached `clone_dtoh` of ISV[543]
+at episode boundaries (same pattern as the linear-Q smoke).
+
+ISV-continual-learning (Phase E.4 Pillar B, designed in
+`specs/2026-05-15-phase-e-temporal-encoder-design.md` — not yet
+implemented): the stacker-threshold controller is intended to fire
+at BOTH training and inference. Q-net weights stay frozen at
+inference; effective policy adapts via ISV slot 543 (threshold), 545
+(observed-rate EMA), 546 (Kelly attenuation). No new ISV slots
+allocated for the E.3 follow-up; E.4.B will add MoE-gate-entropy and
+Pearl-1 atom-headroom slots when those land.