spec(sp20): reserve 10 ISV slots [510..520) for WR-first reward optimization

crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs

@@ -2585,7 +2585,7 @@ const ISV_NETWORK_DIM: usize = 23;
 /// (and the C-side mirrors in `state_layout.cuh`). Bump this constant in the
 /// SAME commit that adds the new range, and update `layout_fingerprint_seed`
 /// to register the new slot names.
-pub(crate) const ISV_TOTAL_DIM: usize = 510;
+pub(crate) const ISV_TOTAL_DIM: usize = 520;  // was 510, SP20 added 10 slots [510..520)
 /// Legacy alias preserved for call sites that haven't been audited for the
 /// network-vs-total split. New code should pick `ISV_NETWORK_DIM` (for weight
 /// tensor sizing) or `ISV_TOTAL_DIM` (for the broadcast bus buffer).
@@ -3701,7 +3701,17 @@ const fn layout_fingerprint_seed() -> &'static [u8] {
       SLOT_507_REWARD_HORIZON_WEIGHT_1BAR=507;\
       SLOT_508_REWARD_HORIZON_WEIGHT_5BAR=508;\
       SLOT_509_REWARD_HORIZON_WEIGHT_30BAR=509;\
-      ISV_TOTAL_DIM=510;\
+      SLOT_510_LOSS_CAP=510;\
+      SLOT_511_ALPHA_EMA=511;\
+      SLOT_512_WR_EMA=512;\
+      SLOT_513_HOLD_COST_SCALE=513;\
+      SLOT_514_TARGET_HOLD_PCT=514;\
+      SLOT_515_HOLD_PCT_EMA=515;\
+      SLOT_516_HOLD_REWARD_EMA=516;\
+      SLOT_517_N_STEP=517;\
+      SLOT_518_AUX_CONF_THRESHOLD=518;\
+      SLOT_519_AUX_GATE_TEMP=519;\
+      ISV_TOTAL_DIM=520;\
       SP19_PRODUCER_HARDCODED_HORIZON_BLEND=sp19_path_b;\
       SP14_C_AUX_TRUNK_CONTROL_PLANE=sp14_c_phase_1;\
       ALPHA_MACHINERY_DELETED=sp14_c_phase_1;\