4d4cd996db
Closes the Phase 3.2 forward-reference loop in the SP20 aggregator.
Previously `out_inputs->per_bar_hold_reward = 0.0f` was hardcoded; the
per-bar Hold opportunity-cost producer existed
(experience_kernels.cu:3823 — `per_bar_opp_cost = -aux_conf × cost_scale`)
and wrote to `hold_baseline_buffer` and `r_micro` directly, but never
reached HOLD_REWARD_EMA. Result: HOLD_REWARD_EMA frozen at sentinel 0.0
across all observed epochs; the SP20 reward centering loop
(`r_micro += per_bar_opp_cost - HOLD_REWARD_EMA`) stayed uncentered,
biasing the policy's reward signal away from zero-mean.
T3.3 wireup mirrors the T2.2 alpha refactor: a per-env scratch buffer
that the producer writes at every step (alongside the existing
`hold_baseline_buffer` write), and the aggregator reads at the same
step. Sums opp_cost over Hold-direction envs only; emits the mean as
`per_bar_hold_reward`. The HOLD_REWARD_EMA's gate (`hold_fraction > 0.5f`
from T3.2) preserves the strict-majority semantic from before.
Atomic across producer site, kernel signature, aggregator, launcher,
collector, and tests (per feedback_no_partial_refactor):
- experience_kernels.cu — new `float* per_bar_opp_cost_per_env`
kernel arg, NULL-tolerant write at line ~3823.
- sp20_aggregate_inputs_kernel.cu — new arg, 6th shmem stripe
(`sh_opp_cost_sum`), per-thread Hold-gated accumulation, tree
reduction extended to 6 stripes, output `per_bar_hold_reward =
opp_cost_sum / hold_count` when hold_count > 0 else 0.
- sp20_aggregate_inputs.rs — launcher signature, dynamic_shmem_bytes
5→6 stripes, doc table, internal test.
- gpu_experience_collector.rs — new `per_bar_opp_cost_per_env:
CudaSlice<f32>` field, alloc, struct construction, kernel-arg
pass at both experience_env_step and sp20_aggregate_inputs
launches (raw_ptr).
- sp20_aggregate_inputs_test.rs — helper renamed
`run_kernel_with_is_win_and_opp_cost`, 4 existing sites pass
NULL, 2 NEW oracle tests verifying real producer + NULL fallback.
- sp20_phase1_4_wireup_test.rs — NULL fallback at the wireup site;
HOLD_REWARD_EMA-stays-at-zero assertion remains valid.
Verification:
- cargo check -p ml --tests: passes (warnings only)
- cargo test -p ml --test sp20_aggregate_inputs_test --features cuda
-- --ignored: 12/12 GPU oracle tests pass on RTX 3050 Ti, including
both new T3.3 tests (per_bar_hold_reward_means_over_hold_envs_only,
null_per_bar_opp_cost_emits_zero).
- cargo test -p ml --test sp20_phase1_4_wireup_test --features cuda
-- --ignored: 2/2 pass under the new NULL-tolerant contract.
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
Tier 3 status: T3.1 ✓, T3.2 ✓, T3.3 ✓ (this commit), T3.4 withdrawn,
T3.5 cascade-pending, T3.6 withdrawn.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
379 lines
17 KiB
Rust
379 lines
17 KiB
Rust
//! SP20 Phase 1.4 (2026-05-09, Path C) — fused-producer chain integration test.
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//!
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//! Direct end-to-end exercise of the 4-kernel chain that the
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//! `GpuExperienceCollector` invokes per rollout step:
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//!
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//! Stats (Kernel 3) → Aggregate (Path C) → EMAs (Kernel 1) → Controllers (Kernel 2)
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//!
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//! Constructs synthetic per-env arrays + aux-head outputs in mapped-pinned
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//! buffers, fires the 4 launches in sequence on a single stream, and
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//! asserts that the 10 SP20 ISV slots populate with sensible
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//! formula-derived values.
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//!
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//! Per `pearl_tests_must_prove_not_lock_observations` the assertions are
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//! invariants (slot is non-sentinel, bound-respecting, monotonic in the
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//! expected direction) rather than locked numerical values.
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//!
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//! Run on a GPU host:
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//!
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//! SQLX_OFFLINE=true CUDA_COMPUTE_CAP=86 \
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//! cargo test -p ml --test sp20_phase1_4_wireup_test --features cuda \
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//! -- --ignored --nocapture
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#![allow(clippy::tests_outside_test_module)]
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#[cfg(feature = "cuda")]
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#[allow(unsafe_code)]
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mod gpu {
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use std::sync::Arc;
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use cudarc::driver::{CudaContext, CudaFunction, CudaStream};
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use ml::cuda_pipeline::mapped_pinned::{MappedF32Buffer, MappedI32Buffer};
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use ml::cuda_pipeline::sp14_isv_slots::{
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ALPHA_EMA_INDEX, AUX_CONF_THRESHOLD_INDEX, AUX_GATE_TEMP_INDEX,
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HOLD_COST_SCALE_INDEX, HOLD_PCT_EMA_INDEX, HOLD_REWARD_EMA_INDEX,
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LOSS_CAP_INDEX, N_STEP_INDEX, TARGET_HOLD_PCT_INDEX, WR_EMA_INDEX,
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};
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use ml::cuda_pipeline::sp20_aggregate_inputs::launch_sp20_aggregate_inputs;
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use ml::cuda_pipeline::sp20_controllers_compute::launch_sp20_controllers_compute;
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use ml::cuda_pipeline::sp20_emas_compute::{
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launch_sp20_emas_compute, EMA_INTERNAL_SLOT_COUNT, OBS_COUNT_SLOTS,
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SP20_EMA_INPUTS_F32_LEN,
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};
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use ml::cuda_pipeline::sp20_stats_compute::{
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launch_sp20_stats_compute, AUX_K_CLASSES,
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};
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/// ISV slot count: cover up to slot 519.
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const ISV_LEN: usize = 520;
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/// Production action encoding constants (mirror `state_layout.cuh`).
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const DIR_DIVISOR: i32 = 27; // 3 * 3 * 3 (mag * ord * urg)
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const HOLD_ACTION_ID: i32 = 1;
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fn encode_dir(dir: i32) -> i32 {
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dir * DIR_DIVISOR
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}
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const SP20_STATS_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/sp20_stats_compute_kernel.cubin"
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));
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const SP20_AGGREGATE_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/sp20_aggregate_inputs_kernel.cubin"
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));
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const SP20_EMAS_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/sp20_emas_compute_kernel.cubin"
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));
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const SP20_CONTROLLERS_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/sp20_controllers_compute_kernel.cubin"
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));
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fn make_stream() -> Arc<CudaStream> {
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let ctx = CudaContext::new(0).expect("CUDA context — is a GPU available?");
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ctx.default_stream()
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}
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fn load_kernel(stream: &Arc<CudaStream>, cubin: &[u8], name: &str) -> CudaFunction {
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let m = stream
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.context()
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.load_cubin(cubin.to_vec())
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.unwrap_or_else(|e| panic!("load {name} cubin: {e}"));
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m.load_function(name)
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.unwrap_or_else(|e| panic!("load {name} function: {e}"))
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}
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/// Run the full 4-kernel chain once with the given synthetic inputs.
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/// Returns the final ISV state after the chain settles.
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fn run_chain_once(
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n_envs: usize,
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aux_logits: &[f32],
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trade_close: &[i32],
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step_ret: &[f32],
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hold_at_exit: &[f32],
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actions: &[i32],
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aux_dir_acc: f32,
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) -> Vec<f32> {
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let stream = make_stream();
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let stats_kernel = load_kernel(&stream, SP20_STATS_CUBIN, "sp20_stats_compute_kernel");
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let agg_kernel = load_kernel(&stream, SP20_AGGREGATE_CUBIN, "sp20_aggregate_inputs_kernel");
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let emas_kernel = load_kernel(&stream, SP20_EMAS_CUBIN, "sp20_emas_compute_kernel");
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let ctrl_kernel = load_kernel(&stream, SP20_CONTROLLERS_CUBIN, "sp20_controllers_compute_kernel");
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// ── ISV bus ──
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let isv = unsafe { MappedF32Buffer::new(ISV_LEN) }.expect("alloc isv");
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isv.write_from_slice(&vec![0.0_f32; ISV_LEN]);
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// ── Stats inputs/outputs ──
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assert_eq!(aux_logits.len(), n_envs * AUX_K_CLASSES,
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"aux_logits must be [n_envs * K=2]");
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let aux_logits_buf = unsafe {
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MappedF32Buffer::new(n_envs * AUX_K_CLASSES)
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}.expect("alloc aux_logits");
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aux_logits_buf.write_from_slice(aux_logits);
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let stats_out = unsafe { MappedF32Buffer::new(2) }.expect("alloc stats_out");
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stats_out.write_from_slice(&[0.0_f32, 0.0_f32]);
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// ── Aggregation inputs ──
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let tc_buf = unsafe { MappedI32Buffer::new(n_envs) }.expect("alloc tc");
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tc_buf.write_from_slice(trade_close);
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let sr_buf = unsafe { MappedF32Buffer::new(n_envs) }.expect("alloc sr");
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sr_buf.write_from_slice(step_ret);
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let he_buf = unsafe { MappedF32Buffer::new(n_envs) }.expect("alloc he");
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he_buf.write_from_slice(hold_at_exit);
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let act_buf = unsafe { MappedI32Buffer::new(n_envs) }.expect("alloc act");
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act_buf.write_from_slice(actions);
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let dir_acc_buf = unsafe { MappedF32Buffer::new(1) }.expect("alloc dir_acc");
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dir_acc_buf.write_from_slice(&[aux_dir_acc]);
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// ── Aggregation output / EMA input struct (9 f32 byte-aliased) ──
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let ema_inputs = unsafe { MappedF32Buffer::new(SP20_EMA_INPUTS_F32_LEN) }
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.expect("alloc ema_inputs");
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ema_inputs.write_from_slice(&vec![0.0_f32; SP20_EMA_INPUTS_F32_LEN]);
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// ── EMA scratch ──
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let internal = unsafe { MappedF32Buffer::new(EMA_INTERNAL_SLOT_COUNT) }
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.expect("alloc internal");
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internal.write_from_slice(&vec![0.0_f32; EMA_INTERNAL_SLOT_COUNT]);
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let obs_count = unsafe { MappedI32Buffer::new(OBS_COUNT_SLOTS) }
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.expect("alloc obs_count");
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obs_count.write_from_slice(&vec![0_i32; OBS_COUNT_SLOTS]);
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// ── Launch chain ──
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unsafe {
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launch_sp20_stats_compute(
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&stream, &stats_kernel,
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aux_logits_buf.dev_ptr,
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stats_out.dev_ptr,
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n_envs as i32,
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).expect("launch sp20_stats_compute");
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let stats_p50 = stats_out.dev_ptr;
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let stats_std = stats_out.dev_ptr + std::mem::size_of::<f32>() as u64;
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launch_sp20_aggregate_inputs(
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&stream, &agg_kernel,
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tc_buf.dev_ptr,
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sr_buf.dev_ptr,
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he_buf.dev_ptr,
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act_buf.dev_ptr,
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/* env_stride = */ 1,
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stats_p50,
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stats_std,
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dir_acc_buf.dev_ptr,
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/* alpha_per_env_dev = */ 0, // SP20 Phase 2 Task 2.2 — Phase 1.4
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// wireup test stays NULL; the alpha
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// producer is exercised at the
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// segment_complete site in the full
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// collector path. Tests in this file
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// assert the placeholder contract
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// (alpha_ema stays at sentinel 0.0).
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/* is_win_per_env_dev = */ 0, // SP20 Phase 2 Task 2.2-fix
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// (2026-05-10) — wireup test stays
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// NULL; the kernel falls back to
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// the `sr > 0` legacy predicate so
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// existing wireup-test assertions
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// (e.g. WR_EMA = 1.0 with one
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// winning trade at step_ret > 0)
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// remain valid.
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/* per_bar_opp_cost_per_env_dev = */ 0, // SP21 T3.3 — wireup test stays
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// NULL; consumer falls back to
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// per_bar_hold_reward = 0.0f
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// matching pre-T3.3 contract.
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n_envs as i32,
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DIR_DIVISOR,
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HOLD_ACTION_ID,
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ema_inputs.dev_ptr,
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).expect("launch sp20_aggregate_inputs");
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launch_sp20_emas_compute(
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&stream, &emas_kernel,
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isv.dev_ptr,
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ema_inputs.dev_ptr,
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internal.dev_ptr,
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obs_count.dev_ptr,
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).expect("launch sp20_emas_compute");
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launch_sp20_controllers_compute(
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&stream, &ctrl_kernel,
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isv.dev_ptr,
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internal.dev_ptr,
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).expect("launch sp20_controllers_compute");
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}
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stream.synchronize().expect("sync after sp20 chain");
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isv.read_all()
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}
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/// Smoke: one rollout step with mid-confidence aux + a winning trade
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/// closure at one env should populate every SP20 ISV slot with
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/// non-sentinel, bound-respecting values.
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#[test]
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#[ignore = "requires GPU"]
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fn one_step_chain_populates_all_10_isv_slots() {
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let n_envs = 8;
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// Mid-confidence aux logits: each row [logit_down, logit_up] with
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// a clear winner (e.g. up=1.0, down=0.0 ⇒ softmax up ≈ 0.73).
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// peak_softmax ≈ 0.73 ⇒ aux_conf ≈ 0.73 - 0.5 = 0.23.
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let mut aux_logits = Vec::with_capacity(n_envs * AUX_K_CLASSES);
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for _ in 0..n_envs {
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aux_logits.push(0.0); // logit_down
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aux_logits.push(1.0); // logit_up
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}
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// One env closes a winning trade at duration 5.
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let mut trade_close = vec![0; n_envs];
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let mut step_ret = vec![0.0_f32; n_envs];
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let mut hold_at_exit = vec![0.0_f32; n_envs];
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trade_close[3] = 1;
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step_ret[3] = 0.4;
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hold_at_exit[3] = 5.0;
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// Half the envs picked Hold (4 of 8 = tie ⇒ action_is_hold = 0).
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// Bump to 5 to cross strict-majority threshold and exercise the
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// HOLD_PCT_EMA fire-on-Hold path.
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let mut actions = vec![encode_dir(2); n_envs]; // most envs Long
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for i in 0..5 {
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actions[i] = encode_dir(HOLD_ACTION_ID);
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}
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let isv = run_chain_once(
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n_envs, &aux_logits, &trade_close, &step_ret, &hold_at_exit,
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&actions, /* aux_dir_acc = */ 0.62,
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);
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// ── ISV invariants ──
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// ALPHA_EMA: aggregation kernel sees `alpha_per_env_dev = 0`
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// (NULL in this test scaffold — the full SP20 reward producer
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// is exercised at the `experience_env_step::segment_complete`
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// site, not in this Phase 1.4 wireup test). The kernel falls
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// back to `alpha = 0.0`, first-observation REPLACE on a closed
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// trade ⇒ ALPHA_EMA stays at 0.0. **This validates the SP20
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// Phase 2 Task 2.2 NULL-tolerance contract** — the
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// aggregation kernel still emits 0.0 when the alpha producer
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// is unwired, preserving the Phase 1.4 placeholder behavior
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// for tests that don't exercise the reward producer.
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assert_eq!(isv[ALPHA_EMA_INDEX], 0.0,
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"ALPHA_EMA stays at 0.0 with NULL alpha_per_env producer (Task 2.2 NULL contract)");
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// WR_EMA: 1 win out of 1 close ⇒ win_fraction = 1.0, first-obs
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// replace ⇒ WR_EMA = 1.0. SP21 T3.1: aggregator emits exact
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// fraction (was binary majority).
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assert_eq!(isv[WR_EMA_INDEX], 1.0,
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"WR_EMA = 1.0 after one winning close (1 win / 1 closed = 1.0)");
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// HOLD_PCT_EMA: 5 of 8 envs picked Hold ⇒ hold_fraction = 5/8 =
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// 0.625, first-obs replace ⇒ HOLD_PCT_EMA = 0.625. SP21 T3.2:
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// aggregator emits exact fraction (was binary majority indicator
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// → 1.0). The fractional value lets the downstream HOLD_COST_SCALE
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// controller make graded decisions instead of the cascade-
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// pinning-at-floor that the binary signal produced.
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let hold_pct = isv[HOLD_PCT_EMA_INDEX];
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assert!(
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(hold_pct - 0.625).abs() < 1e-6,
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"HOLD_PCT_EMA = 0.625 (5/8 of envs Hold); got {hold_pct}",
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);
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// HOLD_REWARD_EMA: per_bar_hold_reward = 0.0 (Phase 3.2 fwd
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// ref); fired on Hold ⇒ EMA = 0.0.
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assert_eq!(isv[HOLD_REWARD_EMA_INDEX], 0.0,
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"HOLD_REWARD_EMA stays at 0.0 (Phase 3.2 forward ref)");
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// LOSS_CAP: WR_EMA = 1.0 > 0.55 ⇒ ramp clamped at 1.0 ⇒
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// LOSS_CAP = -1 - 1 = -2.0.
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let lc = isv[LOSS_CAP_INDEX];
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assert!((lc - (-2.0)).abs() < 1e-6,
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"LOSS_CAP = -2.0 with WR_EMA = 1.0; got {lc}");
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// N_STEP: trade_duration_ema = 5 (first-obs replace), then
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// round to 5; clamp [1, 30] ⇒ N_STEP = 5.
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let n = isv[N_STEP_INDEX];
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assert!((n - 5.0).abs() < 1e-6,
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"N_STEP = 5 with trade_duration = 5; got {n}");
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// AUX_CONF_THRESHOLD: aux_dir_acc_ema = 0.62 (first-obs
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// replace) ⇒ raw = 0.62 - 0.50 = 0.12 ⇒ clamp [0.01, 0.20] ⇒
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// 0.12.
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let act = isv[AUX_CONF_THRESHOLD_INDEX];
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assert!((act - 0.12).abs() < 1e-5,
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"AUX_CONF_THRESHOLD = 0.12 with dir_acc = 0.62; got {act}");
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// AUX_GATE_TEMP: aux_std_ema is the std of aux_conf rows; with
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// identical logits per row, aux_conf is identical so std = 0;
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// floor at 0.01.
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let agt = isv[AUX_GATE_TEMP_INDEX];
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assert!((agt - 0.01).abs() < 1e-6,
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"AUX_GATE_TEMP floor = 0.01 with identical aux logits; got {agt}");
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// TARGET_HOLD_PCT: aux_p50_ema is the kernel's median of
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// aux_conf rows (sp4-histogram quantization). With identical
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// logits per row it lands somewhere in [0, 0.5]; the controller
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// formula then maps that to TARGET_HOLD_PCT in [0.1, 0.8].
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// We assert bound-respecting per
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// `pearl_tests_must_prove_not_lock_observations` rather than
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// an observed numerical value (the histogram bin granularity
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// makes the exact value implementation-specific).
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let thp = isv[TARGET_HOLD_PCT_INDEX];
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assert!(thp >= 0.1 - 1e-6 && thp <= 0.8 + 1e-6,
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"TARGET_HOLD_PCT must be in [0.1, 0.8]; got {thp}");
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// HOLD_COST_SCALE: prev = 0 (constructor), hold_pct_ema = 1.0 >
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// tgt + 0.05 ⇒ ramp up: 0 * 1.05 = 0; final clamp [0.01, 0.5]
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// ⇒ 0.01 (floor). Verifies the deadband / final-clamp wiring
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// even at sentinel-zero start.
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let hcs = isv[HOLD_COST_SCALE_INDEX];
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assert!(hcs >= 0.01 - 1e-6 && hcs <= 0.5 + 1e-6,
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"HOLD_COST_SCALE in [0.01, 0.5]; got {hcs}");
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}
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/// SP20 Phase 2 Task 2.2 contract — when the aggregation kernel is
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/// invoked with `alpha_per_env_dev = 0` (NULL, this test scaffold's
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/// configuration) AND the per-bar-hold-reward producer is still in
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/// Phase 3.2 forward-reference, both EMAs stay at sentinel 0.0
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/// regardless of any input combinations. Validates the
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/// NULL-tolerance contract of the aggregation kernel post-Task-2.2:
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/// downstream tests that don't wire the SP20 reward producer (e.g.
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/// this Phase 1.4 wireup smoke) preserve the Phase 1.4 ALPHA_EMA
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/// placeholder behavior.
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///
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/// HOLD_REWARD_EMA stays at 0.0 because Phase 3.2 lands the per-bar
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/// `r_per_bar = -aux_conf * cost_scale` producer; the aggregation
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/// kernel writes 0.0 for `per_bar_hold_reward` until then.
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///
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/// **Pinned forward refs locked here**:
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/// - ALPHA_EMA bound to NULL-alpha-producer scaffold contract.
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/// - HOLD_REWARD_EMA bound to Phase 3.2 placeholder.
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#[test]
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#[ignore = "requires GPU"]
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fn alpha_and_hold_reward_emas_stay_at_zero_with_null_producers() {
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let n_envs = 4;
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// 4 closing wins per call, 4 Hold actions per call
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let trade_close = vec![1; n_envs];
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let step_ret = vec![0.5; n_envs];
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let hold_at_exit = vec![10.0; n_envs];
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let actions = vec![encode_dir(HOLD_ACTION_ID); n_envs];
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let aux_logits = vec![0.5_f32; n_envs * AUX_K_CLASSES];
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|
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// Single chain run is enough — `run_chain_once` passes
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// alpha_per_env_dev=0 (NULL), so the aggregation kernel falls
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// back to `alpha = 0.0`; first-obs REPLACE on 0.0 lands the
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// EMA at 0.0.
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let isv = run_chain_once(
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n_envs, &aux_logits, &trade_close, &step_ret, &hold_at_exit,
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&actions, 0.99,
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|
);
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|
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assert_eq!(isv[ALPHA_EMA_INDEX], 0.0,
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|
"ALPHA_EMA stays at 0.0 with NULL alpha_per_env producer \
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|
(Task 2.2 NULL-tolerance contract). The full SP20 reward \
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|
producer at experience_env_step::segment_complete is NOT \
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|
exercised in this Phase 1.4 wireup test.");
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assert_eq!(isv[HOLD_REWARD_EMA_INDEX], 0.0,
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|
"HOLD_REWARD_EMA must be 0.0 — Phase 3.2 forward ref \
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|
placeholder. Aggregation kernel writes 0.0 until \
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|
Component 2 lands the per-bar producer.");
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|
}
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|
}
|