Completes the ISV-unified Q-support range spec
(docs/superpowers/specs/2026-04-23-isv-v-range-unification.md) by
migrating the per_sample_support buffer from per-sample [B, 3] to
per-sample-per-branch [B, 4, 3] stride-12. Without this phase the
atom_positions grid already spanned per-branch adaptive ranges (landed
in 9deda5f65 via ISV slots 23..30) while the loss-projection
Bellman step still read a single V(s)-centred range — atoms and
projection disagreed, which is the exact pathology the spec fixes.
Producers:
* iql_value_kernel.cu::iql_compute_per_sample_support — new kernel
signature adds isv_signals pointer; writes 4 branch triples per
sample where centre = isv_signals[23 + 2*d] and half-width = V(s)-
derived Q spread. Bootstrap identity: ISV centres=0 + readiness=0
falls back to [-1, 1] across all 4 branches, byte-identical to the
pre-Phase-2d single-range default at epoch 1.
* iql_value_kernel.cu::iql_support_floor — Frugal-1U p5 estimator now
aggregates half-widths across all (sample, branch) pairs and applies
the floor per (sample, branch) independently.
* gpu_iql_trainer.rs — per_sample_support_buf sized b*4*3, seed writes
12 floats per sample, compute_per_sample_support takes isv_dev_ptr
and forwards it to the kernel; launch-site arg order aligned.
* fused_training.rs — passes trainer.isv_signals_dev_ptr() into the
IQL call.
Consumers (all migrated to stride-12 indexing `b*12 + d*3 + {0,1,2}`):
* c51_loss_kernel.cu::c51_loss_batched — per-branch (v_min, v_max,
delta_z) read INSIDE the d-loop; degenerate-support skip is now
per-branch (continue instead of whole-sample early exit).
* c51_grad_kernel.cu::c51_grad_kernel — per-branch z_norm and
delta_z for the q-gap floor gradient path.
* experience_kernels.cu::compute_expected_q — per-branch (v_min, dz)
inside the d-loop that iterates all 4 branches.
* experience_kernels.cu::mag_concat_qdir — reads direction branch
(d=0) slots from the stride-12 tile.
* experience_kernels.cu::quantile_q_select — per-branch (v_min, dz)
inside the d-loop.
Experience-collector parity:
* gpu_experience_collector.rs — its OWN per_sample_support_buf grows
to alloc_episodes*4*3; update_per_sample_support tiles the same
(v_min, v_max, delta_z) triple to all 4 branches so the layout
matches the IQL buffer and the consumer kernels read uniformly.
Safety:
* Bootstrap byte-identical at epoch 1 preserved (ISV centres default 0,
readiness ramps from 0 → 1).
* No stub values, no TODO/FIXME/XXX markers introduced.
* Kernel scalar arg (gamma) is already f32 in GpuIqlConfig — no f64→f32
cast needed at the call site (feedback_cudarc_f64_f32_abi compliance
via type, not cast).
* c51_loss branch-degenerate `continue` is uniform across the block
(all threads read the same support_base) so __syncthreads inside
the loop body remains collective.
Compile verified: cargo check -p ml + --workspace pass (SQLX_OFFLINE,
CARGO_INCREMENTAL=0, sccache) and cargo build -p ml compiles all
CUDA kernels via nvcc. cargo test -p ml --lib --no-run succeeds.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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