DSR + normalized PnL + drawdown penalty + idle penalty + regime-adaptive
scaling + asymmetric loss + position-time decay + transaction costs.
All computed per-step in the CUDA kernel. Zero CPU involvement.
12 floats per-episode state, ~25 FLOPs per step, zero extra kernel
launches. 7 new hyperopt dimensions (Phase Fast fixed, Phase Full
searchable). Regime scaling from existing ADX/CUSUM features.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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