Wires the 3 Layer D producer kernels into the production hot path AND
removes the host-side EMA arithmetic for sharpe/max_dd/low_dd_ratio in
the same commit per feedback_no_partial_refactor + feedback_no_cpu_compute_strict.
Sites migrated (host → GPU kernel + ISV slot):
training_sharpe_ema → launch_training_metrics_ema → ISV[294]
max_dd_ema → launch_training_metrics_ema → ISV[295]
low_dd_ratio → launch_training_metrics_ema → ISV[296]
LearningHealth.compose → launch_health_composition → ISV[290..294)
trade-PnL aggregation → launch_sp5_pnl_aggregation → ISV[286..290)
Behavior preserved within float precision: every EMA β decay constant,
warmup/clamp wrapper, and downstream consumer formula migrates verbatim.
The kernels reproduce the host computations bit-for-bit (verified by the
GPU-gated unit tests landed in D1/D2/D3 at f42b5fff8 and the D1-rewrite
re-verification at 66f7e64d1; smoke-test-7pv9v PASSED with the additive
kernels loaded but unwired). The additional Pearl A+D smoothing layer
(ALPHA_META=1e-3) is the SP5 architectural change the entire Layer D
programme commits to (cf. pearl_first_observation_bootstrap +
pearl_wiener_optimal_adaptive_alpha).
Removed: host-side EMA arithmetic at training_loop.rs:5043-5099 (~57
lines covering max_dd α=0.1 + low_dd_ratio α=0.15 + training_sharpe
adaptive-α + sentinel branches). Struct fields self.training_sharpe_ema,
::_initialized, self.max_dd_ema, self.low_dd_ratio are KEPT because
external consumers exist (HEALTH_DIAG emit at training_loop.rs:3899,
adaptive-DSR aux-weight controller at 3772, smoke tests at
td_propagation.rs:126/135/155 + generalization.rs:102/103, registry log
emit at 6646); they now hold ISV-Pearl-smoothed values populated by
read_isv_signal_at(294/295/296) after the kernel chain completes.
Also added: GpuDqnTrainer::synchronize_isv_stream() — public cold-path
stream-sync helper at gpu_dqn_trainer.rs:~18475. Single cuStreamSynchronize
of the training stream, mirroring the existing per_branch_q_gap_ema()
embedded sync. Used once per epoch by D4's read-back path.
Out of scope (deferred to D5):
- HealthEmaTrackers::update host-side α=0.1 EMA (metrics.rs:23-25):
produces D2's inputs; D2's launcher takes already-EMA'd scalars.
Eliminating this needs a 4th kernel; out of D4 scope.
- LearningHealth::update warmup wrapper + [0.2, 0.95] clamp
(learning_health.rs:114-124): may have non-DQN consumers (PPO, eval);
deferred to a separate refactor.
- compute_epoch_financials per-bar equity walk: stays as host-side
input source for D1; D1 reproduces it on GPU as a PARALLEL producer
publishing to ISV.
Verification:
- cargo check + build clean
- sp5_isv_slots + state_reset_registry unit tests 8/8 pass
- cargo test -p ml --lib: 933 pass / 14 fail (identical to pre-D4
baseline; failing tests are pre-existing GPU-context-required tests,
not regressions)
- `git grep "= EMA_BETA *|= (1.0 - EMA_BETA)"` returns 0 (was already
0 — gate is a no-op for SP5 because production uses literal
coefficients, not a named EMA_BETA constant). Meaningful gate
`git grep "0.9 \* self.max_dd_ema|0.85 \* self.low_dd_ratio"` also
returns 0 — confirms host EMA arithmetic deletion.
- Order-of-ops: launches chained on training stream before consumer
reads; stream-event sync only (synchronize_isv_stream once per epoch
for cold-path host scalar refresh; producer→consumer paths on the
same stream observe FIFO order without explicit fence).
Mapped-pinned discipline (per feedback_no_htod_htoh_only_mapped_pinned):
D1's step_returns + done_flags consumed via fresh MappedF32Buffer
allocations populated by host_slice_mut — no HtoD copy. Once-per-epoch
cold-path; matches existing pattern at training_loop.rs:1318.
L40S smoke validation deferred to next dispatch — D4 is structurally
risky enough (HEALTH_DIAG visibility behaviour change + ISV-Pearl-
smoothing on host-scalar reads + first-epoch cold-start interaction
with Pearl A) to validate separately. Closes feedback_no_cpu_compute_strict
sweep for SP5 scope (modulo D5 follow-up).
Refs: SP5 plan §D Task D4. Builds on D1-rewrite (66f7e64d1), D2
(e49756ac9), D3 (f42b5fff8). First D4 attempt was blocked by D1
per-trade vs per-bar mismatch; resolved by D1-rewrite.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2e9e276a0c