jgrusewski 45a2041db4 feat(rl): SP20 P6 position heat cap — force-flat on over-leverage ...

Last-defense guard: if |position_lots| exceeds the ISV-driven
RL_HEAT_CAP_MAX_LOTS (slot 504, default 8 = MAX_UNITS × max_order_size),
the kernel overrides actions[b] to FlatFromLong (a3) or FlatFromShort
(a4) — full flatten, no partial. Catches runaway pyramid accumulation
before it reaches actions_to_market_targets.

Override stack ordering (step_with_lobsim):
  1. rl_trail_mutate (a7/a8)
  2. rl_trail_stop_check → may override to FlatFromLong/Short
  3. rl_position_heat_check (THIS) → may override to FlatFromLong/Short
  4. actions_to_market_targets → reads final actions[b]

Kernel `cuda/rl_position_heat_check.cu`:
  * 1 block, b_size threads (grid-stride for b_size > 256)
  * Reads position_lots from pos_state at offset 0 (PosFlat layout)
  * Cap read from ISV[504]; if cap ≤ 0 → no-op (guard disabled)
  * Per feedback_no_atomicadd: fired-count diagnostic uses shared-mem
    flag array + thread-0 serial count (b_size ≤ 256 in practice)
  * Writes fired-count to ISV[505] for diag

ISV slots:
  * 504: RL_HEAT_CAP_MAX_LOTS_INDEX (seed 8.0)
  * 505: RL_HEAT_CAP_FIRED_COUNT_INDEX (diagnostic, written per step)
  * RL_SLOTS_END bumped 505 → 506

Diag (alpha_rl_train):
  * "heat_cap": { "fired_count": N, "max_lots": 8 }

GPU oracle test (trade_management_kernels.rs):
  * position_heat_cap_overrides_on_breach — long 5 > cap 4 → a3;
    short -5 < -cap -4 → a4; long 3 ≤ cap 4 → untouched (Hold)

Verification (RTX 3050 Ti):
  * cargo check -p ml-alpha --examples → clean
  * integrated_trainer_smoke 1/1 → ok
  * trade_management_kernels 6/6 (was 5/5, +1 heat cap) → ok
  * audit-rust-consts → 0 flags

2026-05-24 20:36:05 +02:00

..

fixtures

fix(ml-core): deterministic GPU weight init via scoped_init_seed

2026-05-19 01:19:13 +02:00

adamw_invariants.rs

feat(ml-alpha): BCE multi-horizon + AdamW kernels

2026-05-16 21:57:26 +02:00

aux_heads.rs

feat(aux-heads): rewrite for A+B paired (BCE + conditional-Huber) (CB3+CB4)

2026-05-22 11:16:29 +02:00

aux_trunk.rs

feat(aux-trunk): smaller single-bucket CfC for aux supervision (Layer B3)

2026-05-22 09:03:00 +02:00

backward_finite_diff.rs

feat(ml-alpha): cfc_step_backward emits grad_x for upstream chain

2026-05-16 22:59:36 +02:00

bce_grad_finite_diff.rs

refactor(ml-alpha): consolidate BCE — Kendall σ is THE BCE, wire MHA into trainer

2026-05-18 14:59:12 +02:00

bucket_routing.rs

feat(per-horizon-cfc): add bucket_routing.rs (Controller A + transition dispatch)

2026-05-21 16:18:04 +02:00

bucket_transition_kernels.rs

Revert "fix(per-horizon-cfc): extend block-diagonal mask to heads_w1 (Smoke 2 fix)"

2026-05-21 23:48:15 +02:00

cfc_step_bit_equiv.rs

feat(ml-alpha): cfc_step kernel + invariant-based GPU validation

2026-05-16 21:50:20 +02:00

cfc_step_per_branch.rs

fix(per-horizon-cfc): ALPHA — skip reorder, channels_in_bucket lookup, Adam moment masking

2026-05-21 20:43:51 +02:00

dqn_toy.rs

feat(rl): R6 — replace LobEnv with kernel-driven GPU-pure env step

2026-05-23 10:39:25 +02:00

encoder_gradient.rs

feat(rl): expose forward_encoder() for RL head consumption (Phase B)

2026-05-22 22:28:19 +02:00

forward_graph_capture.rs

feat(ml-alpha): CUDA Graph capture of forward_only (P5)

2026-05-19 17:32:28 +02:00

forward_step_golden.rs

feat(per-horizon-cfc): forward_step_into uses Phase 2 fused dispatch

2026-05-21 19:10:22 +02:00

frd_head.rs

feat(rl): FRD layer-1 backward (dW1, db1, dh_t with ReLU mask) — F.3c

2026-05-24 18:40:30 +02:00

gpu_log_ring_invariants.rs

refactor(per-horizon): N_HORIZONS 5→3 — remaining ml-alpha tests

2026-05-22 01:45:45 +02:00

heads_bit_equiv.rs

feat(ml-alpha): multi_horizon_heads kernel (128->5 sigmoid)

2026-05-16 21:51:48 +02:00

heads_block_diagonal.rs

feat(per-horizon-cfc): add heads_block_diagonal_fwd.cu (compact ragged w_skip)

2026-05-21 16:04:29 +02:00

integrated_trainer_smoke.rs

fix(rl): R9 local-smoke prep — two test-fixture bugs

2026-05-23 13:36:03 +02:00

isv_bootstrap.rs

audit: ISV-ify 10 more design constants — Schulman + bootstraps + streaming α

2026-05-24 01:47:18 +02:00

isv_bus.rs

feat(ml-alpha): IsvBus — 32-slot device-resident f32 bus

2026-05-16 21:38:54 +02:00

multi_horizon_loader.rs

refactor(rl): FRD horizons + range_σ are ISV-driven, not literals

2026-05-24 19:23:39 +02:00

multi_resolution_pipeline.rs

test(ml-alpha): synthetic multi-resolution pipeline test

2026-05-22 20:46:55 +02:00

output_smoothness_grad_finite_diff.rs

refactor(per-horizon): N_HORIZONS 5→3 — remaining ml-alpha tests

2026-05-22 01:45:45 +02:00

perception_forward_golden.rs

fix(ml-core): deterministic GPU weight init via scoped_init_seed

2026-05-19 01:19:13 +02:00

perception_overfit.rs

feat(aux-supervision): wire BCE + conditional-Huber actual calls (CB5)

2026-05-22 11:32:19 +02:00

pinned_slots.rs

feat(ml-alpha): mapped-pinned ingress slots for snapshot + fill

2026-05-16 21:42:28 +02:00

ppo_toy.rs

feat(rl): R6 — replace LobEnv with kernel-driven GPU-pure env step

2026-05-23 10:39:25 +02:00

projection_bit_equiv.rs

feat(ml-alpha): projection kernel (128->8 + layer-norm)

2026-05-16 21:52:57 +02:00

r3_ema_advantage.rs

fix(rl): apply derive-from-input bootstrap to γ + coef controllers

2026-05-23 13:56:40 +02:00

r4_action_kernels.rs

feat(rl): R7d — PER wired + off-policy DQN with stop-grad on encoder

2026-05-23 12:59:42 +02:00

r5_controllers_and_soft_update.rs

audit: ISV-ify 10 more design constants — Schulman + bootstraps + streaming α

2026-05-24 01:47:18 +02:00

r7d_per_wiring.rs

feat(rl): R7d — PER wired + off-policy DQN with stop-grad on encoder

2026-05-23 12:59:42 +02:00

smoothness_lambda_controller_invariants.rs

refactor(per-horizon): rewrite smoothness controller test for N_HORIZONS=3

2026-05-22 01:07:33 +02:00

snap_feature_bit_equiv.rs

Revert "arch(ml-alpha): restore count-delta redundancy at feature slot [26]"

2026-05-18 23:16:38 +02:00

trade_management_kernels.rs

feat(rl): SP20 P6 position heat cap — force-flat on over-leverage

2026-05-24 20:36:05 +02:00