Layer C close-out C2 — the host-side EMA arithmetic block in
GpuDqnTrainer::update_iqn_readiness violated feedback_no_cpu_compute_strict
(any compute — EMA, reduction, mean — belongs on GPU regardless of frequency).
The cold-start sentinel + adaptive-α EMA + improvement-gauge formula now run
GPU-side via update_iqn_readiness_kernel (single-thread, single-block, mirrors
update_grad_norm_emas_kernel shape). The kernel takes the host-passed iqn_loss
scalar (from gpu_iqn.read_total_loss() mapped-pinned readback) and updates
three coupled mapped-pinned scalars (iqn_loss_initial_pinned, iqn_loss_ema_pinned,
iqn_readiness_pinned) in-place. __threadfence_system() guarantees PCIe-visibility
to mapped-pinned host_ptr accessors and to other-stream kernel reads via dev_ptrs.
Storage: iqn_loss_initial and iqn_loss_ema migrated from host-resident f32
fields to mapped-pinned device-mapped scalars (matches grad_norm_fast/slow_ema
pattern from C1 redesigned). New accessors iqn_loss_ema_value() and
iqn_loss_initial_value() read through the host_ptrs. iqn_readiness pinned slot
remains the same — c51_loss_kernel CVaR α consumer dev_ptr unchanged.
Cold-start sentinel (prev_initial < 1e-12 ⇒ assign loss directly + readiness=0)
preserves the deleted host-side bootstrap branch exactly. Same adaptive-α formula
clamp(|err|/(|err|+0.01), 0.01, 0.30) and improvement gauge clamped to [0,1].
state_reset_registry entries updated to reflect the new mapped-pinned storage
and producer relocation; reset_iqn_readiness_state writes 0.0 through the
pinned slots so the next kernel launch re-enters the bootstrap branch.
Verification: SP4 lib tests + 16 SP4 GPU producer unit tests pass on RTX 3050 Ti.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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