1dac3c3fc2
Holds perception outputs (slots 0..13) on-device; slow-path write/snapshot go through MappedF32Buffer DtoD per the htod/htoh discipline. Slot semantics documented in design spec Section 7. Also deletes examples/alpha_mamba_baseline.rs which Task 1 left orphaned (used the deleted eval + training modules). Task 17 will rebuild the Mamba2 baseline trainer path inside gate/cfc_vs_mamba2.rs against the new Phase A loader. Tests pass on local sm_86 (3/3): round-trip one slot, 32-slot capacity, multi-slot independent writes. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
48 lines
1.4 KiB
Rust
48 lines
1.4 KiB
Rust
//! ISV bus round-trip tests. Requires a CUDA device on this host.
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use ml_alpha::isv::{IsvBus, SLOTS};
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use ml_core::device::MlDevice;
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fn test_device() -> MlDevice {
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MlDevice::cuda(0).expect("CUDA 0 required for ml-alpha tests")
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}
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#[test]
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fn isv_bus_round_trip_one_slot() {
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let dev = test_device();
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let mut bus = IsvBus::new(&dev).expect("alloc");
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bus.write_slot(7, 3.14).expect("write");
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let snap = bus.snapshot().expect("read");
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approx::assert_relative_eq!(snap[7], 3.14_f32, epsilon = 1e-6);
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for (i, v) in snap.iter().enumerate() {
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if i == 7 {
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continue;
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}
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assert_eq!(*v, 0.0_f32, "slot {i} should be zero on init");
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}
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}
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#[test]
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fn isv_bus_has_32_slots() {
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let dev = test_device();
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let bus = IsvBus::new(&dev).expect("alloc");
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assert_eq!(bus.len(), SLOTS);
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assert_eq!(SLOTS, 32);
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}
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#[test]
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fn isv_bus_multi_slot_writes_independent() {
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let dev = test_device();
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let mut bus = IsvBus::new(&dev).expect("alloc");
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bus.write_slot(0, 1.0).unwrap();
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bus.write_slot(15, 2.0).unwrap();
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bus.write_slot(31, 3.0).unwrap();
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let snap = bus.snapshot().unwrap();
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approx::assert_relative_eq!(snap[0], 1.0);
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approx::assert_relative_eq!(snap[15], 2.0);
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approx::assert_relative_eq!(snap[31], 3.0);
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for i in [1, 7, 14, 16, 30] {
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assert_eq!(snap[i], 0.0, "slot {i} unexpectedly nonzero");
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}
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}
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