The TMA inline PTX had three invalid instructions causing
CUDA_ERROR_INVALID_PTX at driver JIT time on sm_90 (H100):
1. cp.async.bulk missing required 4th mbarrier operand
2. cp.async.bulk.commit_group — does not exist in any PTX ISA
3. cp.async.bulk.wait_group — does not exist in any PTX ISA
These confused two different CUDA instruction families:
- cp.async (Ampere, uses commit_group/wait_group, 16B per op)
- cp.async.bulk (Hopper TMA, uses mbarrier, up to 256KB per op)
Fix: rewrite cooperative_load_tile_tma() with correct Hopper protocol:
mbarrier.init → mbarrier.arrive.expect_tx → cp.async.bulk [mbar] →
mbarrier.try_wait.parity
Also adds 16-byte alignment guard (cp.async.bulk requires size % 16 == 0)
with float4 fallback for unaligned bias tiles (e.g. NUM_ACTIONS=5 → 20B).
Retains DISABLE_TMA retry in gpu_experience_collector as safety net.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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