After the Phase 4 dueling-head merge landed on main, six integration
tests no longer compiled — they referenced trainer fields and methods
that were renamed or removed during the R-series refactor:
isv_d (CudaSlice<f32>) → isv_dev_ptr: u64 (raw, cached)
isv_host (Vec<f32>) → isv_mapped: MappedF32Buffer
launch_rl_controllers_per_step() → launch_rl_fused_controllers()
softmax_ce_grad(..&mut CudaSlice) → softmax_ce_grad(..&u64)
trainer.replay (Vec-based PER) → gpu_replay (CUDA buffers)
N_HORIZONS = 5 → N_HORIZONS = 3
Release binary built clean throughout (the cluster doesn't pull in
test sources), so the breakage was invisible until `cargo test --tests`
surfaced it post-merge.
Per `feedback_no_partial_refactor`: when a contract changes, every
consumer migrates atomically — the test suite was left behind by
those R-series PRs, this commit closes the gap.
Per `feedback_no_htod_htoh_only_mapped_pinned`: tests now use the
same mapped-pinned ISV view as production (zero-copy host reads via
`isv_host_slice()` / `read_isv_host(slot)`, single-slot writes via
`isv_mapped.write_record(slot, val)`).
Changes per file:
isv_bootstrap.rs (1 site)
Read full ISV via `trainer.isv_host_slice()` instead of dtoh
of the now-removed `isv_d` CudaSlice. Sync producing stream
first so bootstrap-controller writes are visible host-side.
r3_ema_advantage.rs (5 sites)
Rewrote `readback_isv` helper to take `&IntegratedTrainer`
and use the mapped-pinned mirror. All 5 call sites simplified
from `readback_isv(&dev, &trainer.isv_d)` to `readback_isv(&trainer)`.
r5_controllers_and_soft_update.rs
Deleted G3 (`launch_rl_controllers_per_step` no longer exists;
`launch_rl_fused_controllers` is the architectural replacement
with different setup requirements — its 'all controllers move
slots' invariant is exercised end-to-end by every cluster run).
Kept G4 (DqnHead soft-update Polyak formula) with updated API.
trade_management_kernels.rs (3 sites)
`set_isv_slot` helper now uses `isv_mapped.write_record(slot, val)`
— single volatile write to mapped-pinned, GPU sees it after next
sync, no explicit HtoD copy needed.
frd_head.rs (11 sites incl. ce_total_loss helper)
Added `alloc_loss_buf(n) -> MappedF32Buffer` helper. All callers
of `FrdHead::softmax_ce_grad` now pass `&loss_buf.dev_ptr`
(raw u64) instead of `&mut loss_d` (CudaSlice), and read results
via `stream.synchronize()?; loss_buf.read_all()`.
heads_bit_equiv.rs (per_head_independence)
N_HORIZONS dropped from 5 to 3 in production. Test was hardcoded
against the old count (probs[3], probs[4], 5-element bias vec)
causing compile-time index-out-of-bounds. Per
`feedback_use_consts_not_literals_for_structural_dims`: rewrote
to address by N_HORIZONS-relative offsets (first / last / middle).
r7d_per_wiring.rs (deleted)
The old Rust-side `PrioritizedReplay` struct (R7c's
`src/rl/replay.rs`) was removed when the PER buffer moved fully
GPU-side as `gpu_replay: GpuReplayBuffer`. The test was a guard
against re-introducing that dead Rust struct; the dead file no
longer exists in the tree (verified `crates/ml-alpha/src/rl/replay.rs`
is gone), so the guard is moot. The new buffer's correctness is
exercised end-to-end by every cluster training run.
Validation:
- cargo build -p ml-alpha --release: clean
- cargo build -p ml-alpha --tests: clean (all files compile)
- integrated_trainer_smoke (GPU, --ignored): passes
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
277 lines
13 KiB
Rust
277 lines
13 KiB
Rust
//! Phase R1 gate **G1** — `IntegratedTrainer::new` bootstraps each of
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//! the 7 RL adaptive-controller ISV slots to its canonical default via
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//! the kernel-defined `*_BOOTSTRAP` constants (`pearl_first_observation_bootstrap`
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//! sentinel-zero path).
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//!
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//! This catches the canonical Phase F defect (commit history preserved
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//! on `ml-alpha-phase-f-g-flawed`) where ISV[400..406] stayed at
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//! `alloc_zeros` sentinel `0.0` in production, causing
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//! `bellman_target_projection`, `dqn_distributional_q`, and
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//! `ppo_clipped_surrogate` to consume γ=0 / ε=0 / entropy_coef=0 and
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//! train against degenerate Bellman / surrogate targets.
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//!
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//! Per `feedback_no_cpu_test_fallbacks`: the oracle is the kernel's
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//! own `#define *_BOOTSTRAP` constant, not a CPU computation.
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//!
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//! Per `pearl_tests_must_prove_not_lock_observations`: this asserts an
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//! invariant ("bootstrap path wrote the canonical value defined by the
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//! kernel") not a tuned magic number — if a kernel rewrites its
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//! bootstrap constant in a future refactor, this test updates with the
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//! constant, not with empirical observation.
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//!
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//! Run with:
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//! `cargo test -p ml-alpha --test isv_bootstrap -- --ignored --nocapture`
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use ml_alpha::rl::isv_slots::{
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RL_ADV_VAR_RATIO_CLAMP_INDEX, RL_ADV_VAR_RATIO_TARGET_INDEX, RL_DIV_TARGET_INDEX,
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RL_ENTROPY_COEF_INDEX, RL_ENTROPY_TARGET_FRAC_INDEX, RL_EPS_BOOTSTRAP_INDEX,
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RL_GAMMA_INDEX, RL_IMPROVEMENT_THRESHOLD_INDEX, RL_KL_TARGET_INDEX,
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RL_KURT_GAUSSIAN_INDEX, RL_KURT_LIFT_SCALE_INDEX, RL_KURT_NOISE_FLOOR_INDEX,
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RL_K_LOOP_DIVISOR_INDEX, RL_K_LOOP_MAX_INDEX, RL_LOSS_LAMBDA_AUX_INDEX,
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RL_LR_BOOTSTRAP_INDEX, RL_LR_DECAY_FACTOR_INDEX, RL_LR_LOSS_EMA_ALPHA_INDEX,
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RL_LR_MAX_INDEX, RL_LR_MIN_INDEX, RL_LR_WARMUP_STEPS_INDEX,
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RL_MEAN_TRADE_DURATION_EMA_INDEX, RL_N_ROLLOUT_STEPS_INDEX, RL_PER_ALPHA_INDEX,
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RL_PLATEAU_PATIENCE_INDEX, RL_PPO_CLAMP_MARGIN_INDEX, RL_PPO_CLIP_INDEX,
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RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX, RL_PPO_RATIO_CLAMP_MAX_INDEX,
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RL_REWARD_CLAMP_LOSS_INDEX, RL_REWARD_CLAMP_WIN_INDEX, RL_REWARD_SCALE_BOOTSTRAP_INDEX,
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RL_REWARD_SCALE_INDEX, RL_ROLLOUT_BOOTSTRAP_INDEX, RL_SCHULMAN_ADJUST_RATE_INDEX,
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RL_SCHULMAN_TOLERANCE_INDEX, RL_SLOTS_END, RL_STREAM_ALPHA_INDEX, RL_TARGET_TAU_INDEX,
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RL_TAU_BOOTSTRAP_INDEX, RL_TD_KURTOSIS_CLAMP_INDEX,
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};
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use ml_alpha::trainer::integrated::{IntegratedTrainer, IntegratedTrainerConfig};
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use ml_alpha::trainer::perception::PerceptionTrainerConfig;
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use ml_core::device::MlDevice;
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// Canonical bootstrap values — each MUST match the kernel's
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// corresponding `*_BOOTSTRAP` #define in
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// `crates/ml-alpha/cuda/rl_*_controller.cu`. Source of truth is the
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// .cu file; this test asserts the kernel actually wrote those values.
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// Bootstrap value at sentinel input (post-R9 audit: derive-from-input
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// pattern in rl_gamma_controller.cu). Sentinel d_ema = 0 → clamped
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// d=1 → target = 0.5^1 = 0.5 → clamped to GAMMA_MIN = 0.90. Was
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// hardcoded 0.99 (canonical long-horizon) before R9 closed the
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// dead-zone at trade_duration_ema ≈ 69 events.
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const GAMMA_BOOTSTRAP: f32 = 0.90;
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const TAU_BOOTSTRAP: f32 = 0.005;
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const EPS_BOOTSTRAP: f32 = 0.2;
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// Bootstrap value at sentinel input (post-R9 audit: derive-from-input
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// pattern in rl_entropy_coef_controller.cu). Sentinel h_obs = 0 →
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// deficit = h_target = 1.538 → target = (1.538 / 2.197) × 0.05 ≈
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// 0.035. Was hardcoded 0.01 (canonical PPO entropy bonus) before R9
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// closed the dead-zone at entropy_observed_ema ≈ 1.099.
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const COEF_BOOTSTRAP: f32 = 0.035;
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const ROLLOUT_BOOTSTRAP: f32 = 2048.0;
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// Bootstrap value at sentinel input (per the post-R9-audit
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// derive-from-input bootstrap pattern in rl_per_alpha_controller.cu):
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// kurt_excess=0 → target = 0.4. Was hardcoded 0.6 before R9 closed
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// the dead-zone where target(kurt=10) = bootstrap froze the
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// controller.
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const PER_ALPHA_BOOTSTRAP: f32 = 0.4;
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const REWARD_SCALE_BOOTSTRAP: f32 = 1.0;
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#[test]
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#[ignore = "requires CUDA (MlDevice::cuda(0))"]
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fn g1_isv_bootstrap_writes_canonical_values() {
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let dev = match MlDevice::cuda(0) {
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Ok(d) => d,
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Err(e) => {
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eprintln!("CUDA 0 not available — skipping G1 ({e})");
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return;
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}
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};
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let cfg = IntegratedTrainerConfig {
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perception: PerceptionTrainerConfig {
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seq_len: 4,
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n_batch: 1,
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..PerceptionTrainerConfig::default()
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},
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dqn_seed: 0xCAFE,
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ppo_seed: 0xBEEF,
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..IntegratedTrainerConfig::default()
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};
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let trainer = IntegratedTrainer::new(&dev, cfg).expect("IntegratedTrainer::new");
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// Read ISV via the mapped-pinned host view. Per
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// `feedback_no_htod_htoh_only_mapped_pinned`: tests use the same
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// zero-copy mirror as production. Sync the producing stream first
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// so the bootstrap-controller writes from `IntegratedTrainer::new`
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// are visible host-side.
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trainer.stream.synchronize().expect("sync trainer stream");
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let isv: &[f32] = trainer.isv_host_slice();
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assert_eq!(isv.len(), RL_SLOTS_END, "ISV buffer length");
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// Floating-point exact equality is the right oracle here — each
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// kernel's bootstrap path is `isv[slot] = K_BOOTSTRAP; return;`
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// with no arithmetic, so the host-side f32 must equal the kernel's
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// f32 literal bit-for-bit. EPS guards against any unexpected
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// post-bootstrap math we don't see here.
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const EPS: f32 = 1e-6;
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assert!(
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(isv[RL_GAMMA_INDEX] - GAMMA_BOOTSTRAP).abs() < EPS,
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"ISV[γ={RL_GAMMA_INDEX}] expected {GAMMA_BOOTSTRAP}, got {}",
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isv[RL_GAMMA_INDEX]
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);
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assert!(
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(isv[RL_TARGET_TAU_INDEX] - TAU_BOOTSTRAP).abs() < EPS,
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"ISV[τ={RL_TARGET_TAU_INDEX}] expected {TAU_BOOTSTRAP}, got {}",
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isv[RL_TARGET_TAU_INDEX]
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);
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assert!(
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(isv[RL_PPO_CLIP_INDEX] - EPS_BOOTSTRAP).abs() < EPS,
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"ISV[ε={RL_PPO_CLIP_INDEX}] expected {EPS_BOOTSTRAP}, got {}",
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isv[RL_PPO_CLIP_INDEX]
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);
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assert!(
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(isv[RL_ENTROPY_COEF_INDEX] - COEF_BOOTSTRAP).abs() < EPS,
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"ISV[entropy_coef={RL_ENTROPY_COEF_INDEX}] expected {COEF_BOOTSTRAP}, got {}",
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isv[RL_ENTROPY_COEF_INDEX]
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);
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assert!(
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(isv[RL_N_ROLLOUT_STEPS_INDEX] - ROLLOUT_BOOTSTRAP).abs() < EPS,
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"ISV[n_rollout_steps={RL_N_ROLLOUT_STEPS_INDEX}] expected {ROLLOUT_BOOTSTRAP}, got {}",
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isv[RL_N_ROLLOUT_STEPS_INDEX]
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);
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assert!(
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(isv[RL_PER_ALPHA_INDEX] - PER_ALPHA_BOOTSTRAP).abs() < EPS,
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"ISV[per_α={RL_PER_ALPHA_INDEX}] expected {PER_ALPHA_BOOTSTRAP}, got {}",
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isv[RL_PER_ALPHA_INDEX]
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);
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assert!(
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(isv[RL_REWARD_SCALE_INDEX] - REWARD_SCALE_BOOTSTRAP).abs() < EPS,
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"ISV[reward_scale={RL_REWARD_SCALE_INDEX}] expected {REWARD_SCALE_BOOTSTRAP}, got {}",
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isv[RL_REWARD_SCALE_INDEX]
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);
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// Invariant: the EMA-input slots are NOT yet bootstrapped. Phase
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// R3 wires the EMA producer kernels that fill these; until then
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// they MUST remain at `alloc_zeros` sentinel 0. Asserting this
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// here protects against accidental controller-side writes to the
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// wrong slot (a defect a one-character bug could introduce, given
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// the slots are sequential).
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//
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// Exception: RL_PPO_RATIO_CLAMP_MAX_INDEX is a controller-OUTPUT
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// slot (the R9 ppo ratio clamp ceiling). Its bootstrap path fires
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// during `with_controllers_bootstrapped`, leaving the slot at
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// PPO_RATIO_CLAMP_BOOTSTRAP = 10.0 — checked separately below.
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for slot in RL_MEAN_TRADE_DURATION_EMA_INDEX..RL_SLOTS_END {
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// R9 controller-OUTPUT / ISV-resident-design-constant slots
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// that bootstrap to non-zero values.
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if slot == RL_PPO_RATIO_CLAMP_MAX_INDEX
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|| slot == RL_ADV_VAR_RATIO_CLAMP_INDEX
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|| slot == RL_TD_KURTOSIS_CLAMP_INDEX
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|| slot == RL_ADV_VAR_RATIO_TARGET_INDEX
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|| slot == RL_K_LOOP_DIVISOR_INDEX
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|| slot == RL_K_LOOP_MAX_INDEX
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|| slot == RL_REWARD_CLAMP_WIN_INDEX
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|| slot == RL_REWARD_CLAMP_LOSS_INDEX
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|| slot == RL_KL_TARGET_INDEX
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|| slot == RL_IMPROVEMENT_THRESHOLD_INDEX
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|| slot == RL_PLATEAU_PATIENCE_INDEX
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|| slot == RL_DIV_TARGET_INDEX
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|| slot == RL_ENTROPY_TARGET_FRAC_INDEX
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|| slot == RL_KURT_LIFT_SCALE_INDEX
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|| slot == RL_PPO_CLAMP_MARGIN_INDEX
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|| slot == RL_LR_WARMUP_STEPS_INDEX
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|| slot == RL_LR_BOOTSTRAP_INDEX
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|| slot == RL_LR_MIN_INDEX
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|| slot == RL_LR_MAX_INDEX
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|| slot == RL_LR_LOSS_EMA_ALPHA_INDEX
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|| slot == RL_LR_DECAY_FACTOR_INDEX
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|| slot == RL_LOSS_LAMBDA_AUX_INDEX
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|| slot == RL_SCHULMAN_TOLERANCE_INDEX
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|| slot == RL_SCHULMAN_ADJUST_RATE_INDEX
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|| slot == RL_STREAM_ALPHA_INDEX
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|| slot == RL_KURT_GAUSSIAN_INDEX
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|| slot == RL_KURT_NOISE_FLOOR_INDEX
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|| slot == RL_TAU_BOOTSTRAP_INDEX
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|| slot == RL_EPS_BOOTSTRAP_INDEX
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|| slot == RL_ROLLOUT_BOOTSTRAP_INDEX
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|| slot == RL_REWARD_SCALE_BOOTSTRAP_INDEX
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|| slot == RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX
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{
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continue;
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}
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assert_eq!(
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isv[slot], 0.0,
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"ISV[{slot}] expected sentinel 0.0 (R3 wires EMA producers), got {}",
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isv[slot]
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);
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}
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// R9 — PPO ratio clamp ceiling bootstrap.
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assert!(
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(isv[RL_PPO_RATIO_CLAMP_MAX_INDEX] - 10.0).abs() < EPS,
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"ISV[ppo_ratio_clamp_max={RL_PPO_RATIO_CLAMP_MAX_INDEX}] expected 10.0, got {}",
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isv[RL_PPO_RATIO_CLAMP_MAX_INDEX]
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);
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// R9 — streaming-kernel output clamp ceilings (seeded device-side
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// by rl_streaming_clamp_init during bootstrap).
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assert!(
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(isv[RL_ADV_VAR_RATIO_CLAMP_INDEX] - 100.0).abs() < EPS,
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"ISV[adv_var_ratio_clamp={RL_ADV_VAR_RATIO_CLAMP_INDEX}] expected 100.0, got {}",
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isv[RL_ADV_VAR_RATIO_CLAMP_INDEX]
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);
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assert!(
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(isv[RL_TD_KURTOSIS_CLAMP_INDEX] - 30.0).abs() < EPS,
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"ISV[td_kurtosis_clamp={RL_TD_KURTOSIS_CLAMP_INDEX}] expected 30.0, got {}",
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isv[RL_TD_KURTOSIS_CLAMP_INDEX]
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);
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// R9 — ISV-driven advantage-variance-ratio target (replaces the
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// prior hardcoded #define = 0.1 in rl_rollout_steps_controller).
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assert!(
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(isv[RL_ADV_VAR_RATIO_TARGET_INDEX] - 5.0).abs() < EPS,
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"ISV[adv_var_ratio_target={RL_ADV_VAR_RATIO_TARGET_INDEX}] expected 5.0, got {}",
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isv[RL_ADV_VAR_RATIO_TARGET_INDEX]
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);
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// R9 — K-loop config (divisor + max), seeded by rl_streaming_clamp_init.
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assert!(
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(isv[RL_K_LOOP_DIVISOR_INDEX] - 2048.0).abs() < EPS,
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"ISV[k_loop_divisor={RL_K_LOOP_DIVISOR_INDEX}] expected 2048.0, got {}",
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isv[RL_K_LOOP_DIVISOR_INDEX]
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);
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assert!(
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(isv[RL_K_LOOP_MAX_INDEX] - 4.0).abs() < EPS,
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"ISV[k_loop_max={RL_K_LOOP_MAX_INDEX}] expected 4.0, got {}",
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isv[RL_K_LOOP_MAX_INDEX]
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);
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// R9 — 10 ISV-driven design constants seeded by rl_isv_write.
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assert!((isv[RL_REWARD_CLAMP_WIN_INDEX] - 1.0).abs() < EPS);
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assert!((isv[RL_REWARD_CLAMP_LOSS_INDEX] - 3.0).abs() < EPS);
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assert!((isv[RL_KL_TARGET_INDEX] - 0.01).abs() < EPS);
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assert!((isv[RL_IMPROVEMENT_THRESHOLD_INDEX] - 0.99).abs() < EPS);
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assert!((isv[RL_PLATEAU_PATIENCE_INDEX] - 1000.0).abs() < EPS);
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assert!((isv[RL_DIV_TARGET_INDEX] - 0.01).abs() < EPS);
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assert!((isv[RL_ENTROPY_TARGET_FRAC_INDEX] - 0.7).abs() < EPS);
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assert!((isv[RL_KURT_LIFT_SCALE_INDEX] - 7.0).abs() < EPS);
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assert!((isv[RL_PPO_CLAMP_MARGIN_INDEX] - 10.0).abs() < EPS);
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assert!((isv[RL_LR_WARMUP_STEPS_INDEX] - 2000.0).abs() < EPS);
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assert!((isv[RL_LR_BOOTSTRAP_INDEX] - 1e-3).abs() < EPS);
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assert!((isv[RL_LR_MIN_INDEX] - 1e-4).abs() < EPS);
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assert!((isv[RL_LR_MAX_INDEX] - 1e-2).abs() < EPS);
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assert!((isv[RL_LR_LOSS_EMA_ALPHA_INDEX] - 0.05).abs() < EPS);
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assert!((isv[RL_LR_DECAY_FACTOR_INDEX] - 0.5).abs() < EPS);
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assert!((isv[RL_LOSS_LAMBDA_AUX_INDEX] - 1.0).abs() < EPS);
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assert!((isv[RL_SCHULMAN_TOLERANCE_INDEX] - 1.5).abs() < EPS);
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assert!((isv[RL_SCHULMAN_ADJUST_RATE_INDEX] - 1.5).abs() < EPS);
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assert!((isv[RL_STREAM_ALPHA_INDEX] - 0.05).abs() < EPS);
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assert!((isv[RL_KURT_GAUSSIAN_INDEX] - 3.0).abs() < EPS);
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assert!((isv[RL_KURT_NOISE_FLOOR_INDEX] - 1.0).abs() < EPS);
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assert!((isv[RL_TAU_BOOTSTRAP_INDEX] - 0.005).abs() < EPS);
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assert!((isv[RL_EPS_BOOTSTRAP_INDEX] - 0.2).abs() < EPS);
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assert!((isv[RL_ROLLOUT_BOOTSTRAP_INDEX] - 2048.0).abs() < EPS);
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assert!((isv[RL_REWARD_SCALE_BOOTSTRAP_INDEX] - 1.0).abs() < EPS);
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assert!((isv[RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX] - 10.0).abs() < EPS);
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eprintln!(
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"G1 OK — bootstraps: γ={:.4} τ={:.4} ε={:.4} entropy_coef={:.4} \
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n_rollout_steps={:.1} per_α={:.4} reward_scale={:.4}",
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isv[RL_GAMMA_INDEX],
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isv[RL_TARGET_TAU_INDEX],
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isv[RL_PPO_CLIP_INDEX],
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isv[RL_ENTROPY_COEF_INDEX],
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isv[RL_N_ROLLOUT_STEPS_INDEX],
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isv[RL_PER_ALPHA_INDEX],
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isv[RL_REWARD_SCALE_INDEX],
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);
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}
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