nsys profiling identified two hot-path bottlenecks:
1. sync_training_event() — cuEventSynchronize blocked host 5-11ms
EVERY step (87.9% of CUDA API wall time). Removed: LR controller
uses EMA smoothing, 2-step deferred mapped-pinned reads are fine.
2. 24 raw_memset_d8_zero calls per K-loop iteration — zeroed scratch
buffers that backward kernels overwrite completely. At K_max=4:
72 memsets/step, 26% of CUDA API time. Disabled via if-false gate.
Expected combined impact: ~2s saved per 200 steps → measurable sps
improvement at b=1024.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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