After the Phase 4 dueling-head merge landed on main, six integration
tests no longer compiled — they referenced trainer fields and methods
that were renamed or removed during the R-series refactor:
isv_d (CudaSlice<f32>) → isv_dev_ptr: u64 (raw, cached)
isv_host (Vec<f32>) → isv_mapped: MappedF32Buffer
launch_rl_controllers_per_step() → launch_rl_fused_controllers()
softmax_ce_grad(..&mut CudaSlice) → softmax_ce_grad(..&u64)
trainer.replay (Vec-based PER) → gpu_replay (CUDA buffers)
N_HORIZONS = 5 → N_HORIZONS = 3
Release binary built clean throughout (the cluster doesn't pull in
test sources), so the breakage was invisible until `cargo test --tests`
surfaced it post-merge.
Per `feedback_no_partial_refactor`: when a contract changes, every
consumer migrates atomically — the test suite was left behind by
those R-series PRs, this commit closes the gap.
Per `feedback_no_htod_htoh_only_mapped_pinned`: tests now use the
same mapped-pinned ISV view as production (zero-copy host reads via
`isv_host_slice()` / `read_isv_host(slot)`, single-slot writes via
`isv_mapped.write_record(slot, val)`).
Changes per file:
isv_bootstrap.rs (1 site)
Read full ISV via `trainer.isv_host_slice()` instead of dtoh
of the now-removed `isv_d` CudaSlice. Sync producing stream
first so bootstrap-controller writes are visible host-side.
r3_ema_advantage.rs (5 sites)
Rewrote `readback_isv` helper to take `&IntegratedTrainer`
and use the mapped-pinned mirror. All 5 call sites simplified
from `readback_isv(&dev, &trainer.isv_d)` to `readback_isv(&trainer)`.
r5_controllers_and_soft_update.rs
Deleted G3 (`launch_rl_controllers_per_step` no longer exists;
`launch_rl_fused_controllers` is the architectural replacement
with different setup requirements — its 'all controllers move
slots' invariant is exercised end-to-end by every cluster run).
Kept G4 (DqnHead soft-update Polyak formula) with updated API.
trade_management_kernels.rs (3 sites)
`set_isv_slot` helper now uses `isv_mapped.write_record(slot, val)`
— single volatile write to mapped-pinned, GPU sees it after next
sync, no explicit HtoD copy needed.
frd_head.rs (11 sites incl. ce_total_loss helper)
Added `alloc_loss_buf(n) -> MappedF32Buffer` helper. All callers
of `FrdHead::softmax_ce_grad` now pass `&loss_buf.dev_ptr`
(raw u64) instead of `&mut loss_d` (CudaSlice), and read results
via `stream.synchronize()?; loss_buf.read_all()`.
heads_bit_equiv.rs (per_head_independence)
N_HORIZONS dropped from 5 to 3 in production. Test was hardcoded
against the old count (probs[3], probs[4], 5-element bias vec)
causing compile-time index-out-of-bounds. Per
`feedback_use_consts_not_literals_for_structural_dims`: rewrote
to address by N_HORIZONS-relative offsets (first / last / middle).
r7d_per_wiring.rs (deleted)
The old Rust-side `PrioritizedReplay` struct (R7c's
`src/rl/replay.rs`) was removed when the PER buffer moved fully
GPU-side as `gpu_replay: GpuReplayBuffer`. The test was a guard
against re-introducing that dead Rust struct; the dead file no
longer exists in the tree (verified `crates/ml-alpha/src/rl/replay.rs`
is gone), so the guard is moot. The new buffer's correctness is
exercised end-to-end by every cluster training run.
Validation:
- cargo build -p ml-alpha --release: clean
- cargo build -p ml-alpha --tests: clean (all files compile)
- integrated_trainer_smoke (GPU, --ignored): passes
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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