Root cause: IEEE-754 rule 0 * NaN = NaN defeats W=0 safety. Two smokes
proved the bug propagates regardless of W magnitude — pattern identical
at W=[-0.5,0,+0.5,0] (train-th8pj) and W=[0,0,0,0] (train-gs4gx).
The state_121 = batch_states[i * state_dim + 121] read in 4 atom-shift
kernels can contain NaN (upstream source: aux head softmax producing
NaN at some rollout step, stored in replay buffer, sampled into
trainer's batch). 0 * NaN = NaN propagates through all atom-shift
arithmetic.
Defensive fix: guard each state_121 read with isfinite check, fallback
to 0 if NaN/inf. Applies to:
- compute_expected_q (experience_kernels.cu)
- mag_concat_qdir (experience_kernels.cu)
- quantile_q_select (experience_kernels.cu)
- c51_loss_batched (c51_loss_kernel.cu) — state_121 AND next_state_121
- c51_aux_dw_kernel (s121 AND ns121)
This unblocks Phase 3 mechanism validation. The actual state_121 NaN
source (aux head or state assembly) is to be investigated separately.
Cargo check clean.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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