Phase 3b builds on Phase 3a (2e4c7ebf6). Adds the α infrastructure
to the trainer: 2 new CUBIN statics + 7 new struct fields (W weight
+ Adam moments + grad accumulator + 3 kernel handles), and the
new() constructor's alloc + kernel-load block.
α kernels are loaded but NEVER launched yet. Phase 3b is functionally
equivalent to Phase 3a at runtime — the loaded kernels are dead code
until the captured-graph integration (Phase 3c) lands.
Architectural finding deferred to Phase 3c
──────────────────────────────────────────
The trainer's dueling head doesn't have a separate Q_dir buffer.
The `mag_concat_qdir` kernel (gpu_dqn_trainer.rs:9884) computes
Q_dir INTERNALLY from on_v_logits_buf + on_b_logits_buf (V + A
dueling combine: Q[a] = V + (A[a] - mean(A)) per atom), then
immediately concatenates the result with h_s2 in one fused pass.
There's no intermediate buffer between "Q_dir computed" and
"Q_dir consumed" where α could inject as a parallel skip
connection.
Two options for α integration (Phase 3c will pick):
1. Modify mag_concat_qdir to take W_aux + state_121 args and
apply the α bias to its internal Q_dir computation before
concat. Invasive — changes a load-bearing kernel.
2. Add a NEW α-precompute kernel: write Q_dir into a dedicated
buffer (V + A combine), then mag_concat_qdir reads from that
buffer instead of doing the combine inline. Refactors the
dueling head's forward — cleaner separation, bigger change.
Phase 3b commits the α infrastructure so Phase 3c can focus solely
on the captured-graph integration design choice without also
needing to allocate buffers + load kernels.
Files
─────
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs:
+ pub(crate) static SP22_AUX_TO_Q_DIR_BIAS_CUBIN
+ pub(crate) static SP22_AUX_TO_Q_DIR_BIAS_BWD_CUBIN
+ 7 struct fields: w_aux_to_q_dir, adam_m_w_aux, adam_v_w_aux,
dw_aux_buf, aux_to_q_dir_bias_kernel,
aux_to_q_dir_bias_backward_dw_kernel,
aux_to_q_dir_bias_backward_dstate_kernel
+ new() block: alloc 4 zero-init f32 buffers (b0_size=4) for
W + Adam moments + grad accumulator; load 2 cubins, 3
function handles.
+ Struct construction list extended with 7 new fields.
- docs/dqn-wire-up-audit.md:
Phase 3b entry documenting the architectural finding +
Phase 3c scope.
Verification
────────────
- cargo check -p ml --features cuda: 0 errors, 21 pre-existing
warnings (Phase 2/3a baseline parity).
- nvcc cubins unchanged (kernels built in Phase A).
- Runtime equivalent to Phase 3a: α kernels never launched.
Phase 3c scope (remaining for full α activation)
────────────────────────────────────────────────
- Pick option 1 or 2 for mag_concat_qdir integration.
- Wire α forward in training captured forward graph (Step 7).
- Wire α backward kernels in captured backward graph (Step 8).
- Wire α Adam-step update (Step 9).
- C1: α forward in collector's rollout-time captured graph.
- D1-D7: A2 eval-side aux trunk + α + state-gather wiring.
- B6: SP11 controller extension for non-zero scale_β.
- B7/B10/B11: HEALTH_DIAG telemetry extensions.
- E + F: verification gates + atomic Phase F commit + smoke + verdict.
Estimated remaining: ~20-30 hr engineering + ~37 min smoke wall-clock.
Refs
────
- docs/plans/2026-05-12-sp22-h6-phase3-alpha-beta.md (spec)
- docs/plans/2026-05-13-sp22-h6-phase3-alpha-beta-runbook.md (runbook)
- 464bc5f7a (Phase A foundation)
- 2e4c7ebf6 (Phase 3a — 7-component contract + β producer)
- pearl_no_partial_refactor (Phase 3b is additive struct fields)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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