spec(dqn): SP2 + SP3 combined — F0 regression fix + Q-learning structural stability
Designs the fixes for the two SP1 leftover issues identified at SP1 closure
(commit 047f175fb):
1. SP2 — F0 regression fix (instrumentation overhead optimization):
Consolidate the 11 per-step check_nan_f32 launches in
run_nan_checks_post_backward into a single fused-reduce kernel
(dqn_nan_check_fused_f32_kernel). 1 launch instead of 11; expected
F0 return to ~55 baseline (was regressing to ~35 across 3 SP1 smokes).
2. SP3 — Q-learning structural stability (5 mechanisms):
- M1: Target-Q clipping at single-point source, ISV-driven
(10 × isv[Q_ABS_REF].max(1.0))
- M2: C51 atom-position growth bounds, same ISV bound
- M3: Hard target sync at fold boundary (DQN + IQN + ensemble target nets)
- M4: Adam EMA reset at fold transitions (comprehensive — all Adams)
- M5: Embedded Adam-centric diagnostic instrumentation (slots 36-47):
Adam m/v max-abs (slots 36-43), weight max-abs (44-45),
target_q post-clip (46), atom span (47). Sticky-bit threshold
checks; SP2's fused kernel is extended (NOT replaced) to handle
all 24 slots in 24 blocks.
Architecture: SP2 lands first; Gate 1 must pass (F0 ≥ 53.08 + slot
24-35 firing topology unchanged) before SP3 starts. SP3's 5 mechanisms
ship in ONE commit per feedback_no_partial_refactor (related fixes
for the same root pathology — Q-target inflation drives Adam EMA
saturation drives weight drift drives cuBLAS overflow). Gate 2
evaluates the full SP1 7-criterion bar.
Operating principles (mandatory):
- ISV-driven design for every dynamic bound (no hardcoded clip values)
- ε floor on ISV multiplier per SP1 pearl (`isv.max(1.0)`)
- Combined RELATED commits per feedback_no_partial_refactor
- Permanent diagnostic infrastructure (always-on, no debug flags)
- No deferrals — anomalies during impl get fixed within scope
Validation cost: SP2 ~1-2 days + 1 smoke; SP3 ~3-5 days + 1-2 smokes.
Combined ~1000 LOC across 2 commits.
Spec covers: architecture, components (SP2 fused kernel + SP3 5
mechanisms), data flow, ISV slot bindings, validation gates, error
handling failure modes, operating principles, anti-patterns,
sequencing constraints, effort estimate, handoff conditions.
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