jgrusewski
edd7ceb0f2
perf(cuda): H100 optimization Wave 0+1 — NVTX profiling, L2 cache pinning, dynamic shmem, async double buffer
Wave 0 (NVTX Instrumentation):
- Add ml-core::nvtx module with NvtxRange RAII guard (runtime dlopen, zero overhead when absent)
- Instrument 10 CUDA pipeline hot paths: experience collector, backtest evaluator,
PPO collector, statistics, training guard, monitoring, replay buffer
Wave 1 (Low-Effort H100 Optimizations):
- L2 cache persistence: pin DQN weights (~23MB BF16) in H100's 50MB L2 via
cudaCtxSetLimit(CU_LIMIT_PERSISTING_L2_CACHE_SIZE) — 3.5x effective bandwidth
- Dynamic shared memory: GPU-aware tile sizing (228KB H100, 164KB A100, 100KB RTX)
via CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES opt-in
- Async double buffer: sync_staging() with CUDA stream synchronization before swap
Validation: 0 clippy errors, 1629 tests passed (308+410+911), 0 gpu-hotpath violations
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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