feat(cuda): pipeline improvements — double buffer, weights, collectors
- common_device_functions.cuh: extended shared header for fused ops - double_buffer.rs: async double-buffered GPU memory transfers - gpu_weights.rs: unified weight management for fused training - gpu_experience_collector.rs: streamlined GPU experience collection - gpu_ppo_collector.rs: PPO collector GPU path improvements - gpu_curiosity_trainer.rs + kernel: curiosity training on GPU - dqn_experience_kernel.cu: experience kernel updates Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
jgrusewski
@@ -5,6 +5,25 @@
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* Both kernels prepend this file's contents before their own source.
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*/
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/* ------------------------------------------------------------------ */
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/* BF16 Mixed Precision Support (H100 Tensor Core Path) */
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/* ------------------------------------------------------------------ */
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/* H100 SM90: 989 TFLOPS BF16 tensor cores vs 67 TFLOPS F32 scalar.
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* Strategy: BF16 storage + BF16 matmul inputs + F32 accumulation.
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* This matches NVIDIA's native tensor core accumulate mode. */
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#include <cuda_bf16.h>
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/** BF16 leaky ReLU — operates on raw bf16, returns bf16. */
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__device__ __forceinline__ __nv_bfloat16 leaky_relu_bf16(__nv_bfloat16 x) {
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float xf = __bfloat162float(x);
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return __float2bfloat16((xf >= 0.0f) ? xf : 0.01f * xf);
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}
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/** Convert F32 to BF16 (truncation, matching PyTorch default). */
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__device__ __forceinline__ __nv_bfloat16 f32_to_bf16(float x) {
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return __float2bfloat16(x);
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}
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/* ------------------------------------------------------------------ */
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/* Constants */
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/* ------------------------------------------------------------------ */
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@@ -195,6 +214,12 @@ __device__ void noisy_matvec_leaky_relu(
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#ifndef SHMEM_TILE_ROWS
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#define SHMEM_TILE_ROWS 64
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#endif
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/* BF16 weight tiles are half the byte-width of F32, so the same shared memory
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* region fits 2× the rows. Forward kernels using BF16 weights tile with this
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* doubled row count, halving tiling iterations for the largest matmuls. */
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#ifndef SHMEM_TILE_ROWS_BF16
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#define SHMEM_TILE_ROWS_BF16 (2 * SHMEM_TILE_ROWS)
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#endif
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#ifndef SHMEM_MAX_IN_DIM
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#define SHMEM_MAX_IN_DIM 256 /* max(STATE_DIM, SHARED_H1, SHARED_H2) */
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#endif
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@@ -294,10 +319,10 @@ __device__ __forceinline__ void cooperative_load_tile_tma(
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: : "r"(mbar_addr), "r"((unsigned int)byte_count) : "memory"
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);
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/* Issue bulk copies in 16KB chunks.
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/* Issue bulk copies in 64KB chunks (H100 TMA optimal).
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* cp.async.bulk.shared::cta.global [dst], [src], size, [mbar];
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* Each copy auto-increments the mbarrier TX counter on completion. */
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const int CHUNK_FLOATS = 4096; /* 16 KB per chunk */
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const int CHUNK_FLOATS = 16384; /* 64 KB per chunk */
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int remaining = count;
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int offset = 0;
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while (remaining > 0) {
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@@ -317,13 +342,15 @@ __device__ __forceinline__ void cooperative_load_tile_tma(
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}
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}
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/* Ensure all lanes see the mbarrier init before waiting.
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/* Ensure all threads see the mbarrier init before waiting.
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* Critical on Hopper with independent thread scheduling — without
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* this fence, lanes 1-31 could reach try_wait before thread 0 writes
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* the mbarrier init. */
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__syncwarp(0xFFFFFFFF);
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* this fence, other threads could reach try_wait before thread 0
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* writes the mbarrier init.
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* Uses __syncthreads() to support multi-warp blocks (EPISODES_PER_BLOCK > 1)
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* where multiple warps share the same shmem tile. Safe for single-warp too. */
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__syncthreads();
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/* ALL lanes wait for the bulk copies to complete.
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/* ALL threads wait for the bulk copies to complete.
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* mbarrier completes when: arrivals == init_count (1)
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* AND tx_bytes_delivered == expected_tx (byte_count).
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* Phase parity 0 matches the freshly-initialized mbarrier.
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@@ -345,9 +372,9 @@ __device__ __forceinline__ void cooperative_load_tile_tma(
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}
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}
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/* Ensure all lanes completed the wait before caller can reinitialize
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/* Ensure all threads completed the wait before caller can reinitialize
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* the mbarrier for the next tile in the same forward pass. */
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__syncwarp(0xFFFFFFFF);
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__syncthreads();
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}
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#endif /* __CUDA_ARCH__ >= 900 */
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@@ -370,6 +397,191 @@ __device__ __forceinline__ void cooperative_load_tile(
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#endif
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}
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/* ------------------------------------------------------------------ */
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/* BF16 Shared Memory Weight Caching */
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/* ------------------------------------------------------------------ */
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/**
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* Cooperatively load a BF16 weight tile from global to shared memory.
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* Global source is BF16 (__nv_bfloat16*), shared dest is also BF16.
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* Halves bandwidth vs F32 load. Must call __syncwarp() after.
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*
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* Uses short2 vectorized loads (4 bytes = 2 BF16 elements per load)
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* for coalesced access on H100.
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*/
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__device__ __forceinline__ void cooperative_load_tile_bf16(
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__nv_bfloat16* __restrict__ shmem_dst,
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const __nv_bfloat16* __restrict__ global_src,
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int count /* total bf16 elements to load */
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) {
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/* Vectorize as short2 (2 BF16 = 4 bytes per load) */
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int vec2_count = count / 2;
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int remainder = count & 1;
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short2* dst2 = (short2*)shmem_dst;
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const short2* src2 = (const short2*)global_src;
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for (int i = threadIdx.x; i < vec2_count; i += blockDim.x)
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dst2[i] = src2[i];
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if (remainder && threadIdx.x == 0) {
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int base = vec2_count * 2;
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shmem_dst[base] = global_src[base];
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}
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}
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/**
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* Cooperatively load a BF16 bias tile from global to F32 shared memory.
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* Biases are small and added in F32, so expand on load.
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*/
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__device__ __forceinline__ void cooperative_load_bias_bf16_to_f32(
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float* __restrict__ shmem_dst,
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const __nv_bfloat16* __restrict__ global_src,
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int count
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) {
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for (int i = threadIdx.x; i < count; i += blockDim.x)
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shmem_dst[i] = __bfloat162float(global_src[i]);
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}
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/**
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* Warp-cooperative matrix-vector multiply with BF16 weights, F32 accumulation.
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*
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* Weights in shared memory are BF16 (__nv_bfloat16), input is F32 distributed,
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* dot product accumulates in F32. Bias is F32 (pre-expanded on load).
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* This matches the H100 tensor core accumulate mode: BF16 × BF16 → F32.
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*
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* @param shmem_W_bf16 BF16 weight tile [tile_rows × in_dim] in shared memory
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* @param shmem_b_f32 F32 bias tile [tile_rows] in shared memory
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* @param input_dist F32 distributed input [DIST_SIZE(in_dim)] per lane
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* @param output_dist F32 distributed output [DIST_SIZE(out_dim)] per lane
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*/
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__device__ void warp_matvec_bf16_shmem(
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const __nv_bfloat16* __restrict__ shmem_W_bf16,
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const float* __restrict__ shmem_b_f32,
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const float* input_dist,
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float* output_dist,
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int in_dim,
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int out_dim,
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int tile_offset,
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int tile_rows,
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int activate,
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int lane_id
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) {
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(void)out_dim;
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for (int j = 0; j < tile_rows; j++) {
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const __nv_bfloat16* row = shmem_W_bf16 + j * in_dim;
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/* F32 accumulation of BF16 dot product */
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float partial = 0.0f;
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for (int i = lane_id; i < in_dim; i += 32) {
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float w_f32 = __bfloat162float(row[i]);
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partial += w_f32 * input_dist[i / 32];
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}
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/* Add F32 bias (only lane 0) */
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if (lane_id == 0)
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partial += shmem_b_f32[j];
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float sum = warp_reduce_sum_all(partial);
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if (activate) sum = leaky_relu(sum);
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int gj = tile_offset + j;
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if (lane_id == (gj & 31))
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output_dist[gj >> 5] = sum;
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}
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}
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/**
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* Warp-cooperative BF16 matvec with broadcast output (non-distributed).
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* Same as warp_matvec_bf16_shmem but ALL lanes store every output element.
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* Used for small output layers (C51 atom logits) where all lanes need results.
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*/
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__device__ void warp_matvec_bf16_broadcast_shmem(
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const __nv_bfloat16* __restrict__ shmem_W_bf16,
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const float* __restrict__ shmem_b_f32,
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const float* input_dist,
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float* output, /* NOT distributed — all lanes get full copy */
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int in_dim,
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int out_dim,
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int tile_offset,
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int tile_rows,
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int activate,
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int lane_id
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) {
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(void)out_dim;
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for (int j = 0; j < tile_rows; j++) {
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const __nv_bfloat16* row = shmem_W_bf16 + j * in_dim;
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float partial = 0.0f;
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for (int i = lane_id; i < in_dim; i += 32) {
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float w_f32 = __bfloat162float(row[i]);
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partial += w_f32 * input_dist[i / 32];
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}
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if (lane_id == 0)
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partial += shmem_b_f32[j];
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float sum = warp_reduce_sum_all(partial);
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if (activate) sum = leaky_relu(sum);
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output[tile_offset + j] = sum;
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}
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}
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/* ------------------------------------------------------------------ */
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/* BF16 Tiled Layer Macro */
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/* ------------------------------------------------------------------ */
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/* BF16 version of TILE_LAYER_WARP_CLEAN: loads BF16 weights from global,
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* expands bias to F32, computes matvec with F32 accumulation.
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* Shared memory layout: shmem_w holds BF16 weights (half the size),
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* shmem_b holds F32 bias (expanded on load).
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*
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* NOTE: shmem_w is cast to __nv_bfloat16* — the caller's shared memory
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* buffer must be large enough for tile_rows × in_dim × sizeof(bf16) elements.
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* Since sizeof(bf16) = sizeof(float)/2, the existing F32 buffer is always
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* large enough. */
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#ifndef TILE_LAYER_WARP_BF16
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#define TILE_LAYER_WARP_BF16(W_bf16, b_bf16, input_dist, output_dist, in_d, out_d, act, shmem_w, shmem_b, lane) \
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do { \
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__nv_bfloat16* _shmem_w_bf16 = (__nv_bfloat16*)(shmem_w); \
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for (int _tile = 0; _tile < ((out_d) + SHMEM_TILE_ROWS_BF16 - 1) / SHMEM_TILE_ROWS_BF16; _tile++) { \
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int _ts = _tile * SHMEM_TILE_ROWS_BF16; \
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int _tr = SHMEM_MIN(SHMEM_TILE_ROWS_BF16, (out_d) - _ts); \
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cooperative_load_tile_bf16(_shmem_w_bf16, (const __nv_bfloat16*)(W_bf16) + _ts * (in_d), _tr * (in_d)); \
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cooperative_load_bias_bf16_to_f32(shmem_b, (const __nv_bfloat16*)(b_bf16) + _ts, _tr); \
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__syncwarp(0xFFFFFFFF); \
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warp_matvec_bf16_shmem(_shmem_w_bf16, shmem_b, input_dist, output_dist, \
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in_d, out_d, _ts, _tr, act, lane); \
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__syncwarp(0xFFFFFFFF); \
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} \
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} while (0)
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#endif
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/* ------------------------------------------------------------------ */
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/* F32→BF16 Weight Conversion Kernel */
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/* ------------------------------------------------------------------ */
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/**
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* Convert F32 weights to BF16 in-place on GPU.
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* Called once per weight sync (not per training step).
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* Grid: ceil(n/256), Block: 256.
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*/
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extern "C" __global__ void f32_to_bf16_kernel(
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const float* __restrict__ src,
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__nv_bfloat16* __restrict__ dst,
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int n
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) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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if (idx < n)
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dst[idx] = __float2bfloat16(src[idx]);
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}
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/**
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* Convert BF16 weights back to F32 on GPU.
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* Used for reverse sync (GPU weights → VarMap for checkpointing).
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*/
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extern "C" __global__ void bf16_to_f32_kernel(
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const __nv_bfloat16* __restrict__ src,
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float* __restrict__ dst,
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int n
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) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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if (idx < n)
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dst[idx] = __bfloat162float(src[idx]);
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}
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/* ------------------------------------------------------------------ */
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/**
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* Matrix-vector multiply from shared memory: output = shmem_W * input + shmem_b.
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*
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@@ -50,10 +50,18 @@ extern "C" __global__ void curiosity_zero_grads(float* grads, int n) {
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/* Kernel 3: Forward + backward pass, accumulate gradients */
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/* ------------------------------------------------------------------ */
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/* Warp-level sum reduction via butterfly shuffle (all lanes get result) */
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__device__ __forceinline__ float warp_sum_cur(float val) {
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_xor_sync(0xFFFFFFFF, val, offset);
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return val;
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}
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/**
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* One thread per sample. Computes forward pass, MSE loss, and backpropagates
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* gradients via atomicAdd. For ~12K params this is fine on H100 (native
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* FP32 atomics) and adequate on Ampere.
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* gradients via atomicAdd with warp-level pre-reduction (32x fewer atomics).
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* Threads within a warp process different samples but accumulate gradients
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* to the same weight indices, so warp reduction before atomicAdd is valid.
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*/
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extern "C" __global__ void curiosity_forward_backward(
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const float* __restrict__ states, /* [N, state_dim] */
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@@ -123,14 +131,20 @@ extern "C" __global__ void curiosity_forward_backward(
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d_pred[o] = (pred[o] - next_state[o]) * inv_out;
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}
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/* ---- Backward: Layer 2 ---- */
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/* ---- Backward: Layer 2 (warp-reduced atomics) ---- */
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float d_hidden[CUR_HIDDEN];
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for (int h = 0; h < CUR_HIDDEN; h++) d_hidden[h] = 0.0f;
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for (int o = 0; o < CUR_OUTPUT; o++) {
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atomicAdd(&grad_b2[o], d_pred[o]);
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{
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float val = warp_sum_cur(d_pred[o]);
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if ((threadIdx.x & 31) == 0) atomicAdd(&grad_b2[o], val);
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}
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for (int h = 0; h < CUR_HIDDEN; h++) {
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atomicAdd(&grad_w2[o * CUR_HIDDEN + h], d_pred[o] * hidden[h]);
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{
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float val = warp_sum_cur(d_pred[o] * hidden[h]);
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if ((threadIdx.x & 31) == 0) atomicAdd(&grad_w2[o * CUR_HIDDEN + h], val);
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}
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d_hidden[h] += w2[o * CUR_HIDDEN + h] * d_pred[o];
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}
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}
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@@ -140,11 +154,17 @@ extern "C" __global__ void curiosity_forward_backward(
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if (pre_act[h] <= 0.0f) d_hidden[h] *= 0.01f;
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}
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/* ---- Backward: Layer 1 ---- */
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/* ---- Backward: Layer 1 (warp-reduced atomics) ---- */
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for (int h = 0; h < CUR_HIDDEN; h++) {
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atomicAdd(&grad_b1[h], d_hidden[h]);
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{
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float val = warp_sum_cur(d_hidden[h]);
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if ((threadIdx.x & 31) == 0) atomicAdd(&grad_b1[h], val);
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}
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for (int i = 0; i < CUR_INPUT; i++) {
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atomicAdd(&grad_w1[h * CUR_INPUT + i], d_hidden[h] * input[i]);
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{
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float val = warp_sum_cur(d_hidden[h] * input[i]);
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if ((threadIdx.x & 31) == 0) atomicAdd(&grad_w1[h * CUR_INPUT + i], val);
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}
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}
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}
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}
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@@ -222,3 +242,234 @@ extern "C" __global__ void curiosity_adam_step_fused(
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float v_hat = vv[local_i] / (1.0f - powf(beta2, (float)step));
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p[local_i] -= lr * m_hat / (sqrtf(v_hat) + eps);
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}
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/* ------------------------------------------------------------------ */
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/* Kernel 5: Fully fused zero + forward/backward + Adam */
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/* ------------------------------------------------------------------ */
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/**
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* Fuses gradient zeroing, forward+backward pass, and Adam optimizer
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* update into a single kernel launch. Uses an atomic block-arrival
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* counter for grid-wide synchronization between the fwd/bwd phase
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* (sample-parallel) and the Adam phase (parameter-parallel).
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*
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* Phase 1 (all threads): Zero gradient buffers via grid-stride loop,
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* then __syncthreads() within each block.
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* Phase 2 (all threads): Forward + backward pass (one sample per thread),
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* accumulate gradients via warp-reduced atomicAdd.
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* Phase 3 (last-arriving block only): After all blocks complete phase 2,
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* the last block to arrive (detected via atomic counter) applies
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* Adam update across all parameters in a grid-stride loop.
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*
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* Saves 4 memset dispatches + 1 kernel launch = 5 fewer GPU dispatches
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* per training step (~30-50 µs on H100 at high training frequency).
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||||
*/
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extern "C" __global__ void curiosity_fused_zero_fwd_bwd_adam(
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const float* __restrict__ states, /* [N, state_dim] */
|
||||
const int* __restrict__ actions, /* [N] */
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const float* __restrict__ next_states, /* [N, state_dim] */
|
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/* Weights (updated in-place by Adam in phase 3) */
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||||
float* __restrict__ w1, /* [CUR_HIDDEN, CUR_INPUT] */
|
||||
float* __restrict__ b1, /* [CUR_HIDDEN] */
|
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float* __restrict__ w2, /* [CUR_OUTPUT, CUR_HIDDEN] */
|
||||
float* __restrict__ b2, /* [CUR_OUTPUT] */
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||||
/* Gradient accumulators (zeroed in phase 1, accumulated in phase 2) */
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||||
float* __restrict__ grad_w1, /* [CUR_HIDDEN, CUR_INPUT] */
|
||||
float* __restrict__ grad_b1, /* [CUR_HIDDEN] */
|
||||
float* __restrict__ grad_w2, /* [CUR_OUTPUT, CUR_HIDDEN] */
|
||||
float* __restrict__ grad_b2, /* [CUR_OUTPUT] */
|
||||
/* Adam first moment */
|
||||
float* __restrict__ adam_m_w1, /* [CUR_HIDDEN * CUR_INPUT] */
|
||||
float* __restrict__ adam_m_b1, /* [CUR_HIDDEN] */
|
||||
float* __restrict__ adam_m_w2, /* [CUR_OUTPUT * CUR_HIDDEN] */
|
||||
float* __restrict__ adam_m_b2, /* [CUR_OUTPUT] */
|
||||
/* Adam second moment */
|
||||
float* __restrict__ adam_v_w1, /* [CUR_HIDDEN * CUR_INPUT] */
|
||||
float* __restrict__ adam_v_b1, /* [CUR_HIDDEN] */
|
||||
float* __restrict__ adam_v_w2, /* [CUR_OUTPUT * CUR_HIDDEN] */
|
||||
float* __restrict__ adam_v_b2, /* [CUR_OUTPUT] */
|
||||
/* Atomic block-arrival counter (must be zeroed before launch) */
|
||||
int* __restrict__ block_counter,
|
||||
/* Scalar parameters */
|
||||
int N, /* number of training samples */
|
||||
int state_dim,
|
||||
int batch_size, /* == N, for gradient averaging */
|
||||
float lr, float beta1, float beta2, float eps,
|
||||
int adam_step /* 1-based step counter */
|
||||
) {
|
||||
int tid = blockIdx.x * blockDim.x + threadIdx.x;
|
||||
int grid_size = gridDim.x * blockDim.x;
|
||||
|
||||
/* ================================================================ */
|
||||
/* PHASE 1: Zero gradient buffers (grid-stride loop) */
|
||||
/* ================================================================ */
|
||||
int total_grad_elems = CUR_TOTAL_PARAMS;
|
||||
/* Pack all 4 grad arrays into a single linear index space:
|
||||
* [0, w1_len) -> grad_w1
|
||||
* [w1_len, w1_len+b1_len) -> grad_b1
|
||||
* [w1_len+b1_len, w1_len+b1_len+w2_len) -> grad_w2
|
||||
* [w1_len+b1_len+w2_len, total) -> grad_b2 */
|
||||
int w1_len = CUR_HIDDEN * CUR_INPUT;
|
||||
int b1_len = CUR_HIDDEN;
|
||||
int w2_len = CUR_OUTPUT * CUR_HIDDEN;
|
||||
/* b2_len = CUR_OUTPUT (implicit) */
|
||||
|
||||
for (int i = tid; i < total_grad_elems; i += grid_size) {
|
||||
if (i < w1_len) {
|
||||
grad_w1[i] = 0.0f;
|
||||
} else if (i < w1_len + b1_len) {
|
||||
grad_b1[i - w1_len] = 0.0f;
|
||||
} else if (i < w1_len + b1_len + w2_len) {
|
||||
grad_w2[i - w1_len - b1_len] = 0.0f;
|
||||
} else {
|
||||
grad_b2[i - w1_len - b1_len - w2_len] = 0.0f;
|
||||
}
|
||||
}
|
||||
|
||||
/* Ensure all gradient buffers are zeroed before any thread starts
|
||||
* the forward/backward pass. __syncthreads() synchronizes within
|
||||
* the block; __threadfence() ensures global memory visibility. */
|
||||
__threadfence();
|
||||
__syncthreads();
|
||||
|
||||
/* ================================================================ */
|
||||
/* PHASE 2: Forward + backward pass (one sample per thread) */
|
||||
/* ================================================================ */
|
||||
if (tid < N) {
|
||||
const float* state = states + tid * state_dim;
|
||||
int action_idx = actions[tid];
|
||||
const float* next_state = next_states + tid * state_dim;
|
||||
|
||||
/* ---- Forward pass ---- */
|
||||
|
||||
/* Build input: first MARKET_DIM state features + 3-class action one-hot */
|
||||
float input[CUR_INPUT];
|
||||
for (int i = 0; i < MARKET_DIM; i++) input[i] = state[i];
|
||||
input[MARKET_DIM + 0] = 0.0f;
|
||||
input[MARKET_DIM + 1] = 0.0f;
|
||||
input[MARKET_DIM + 2] = 0.0f;
|
||||
|
||||
/* Action to category one-hot */
|
||||
int category;
|
||||
if (action_idx <= 1) category = 0; /* Short100/Short50 */
|
||||
else if (action_idx == 2) category = 1; /* Flat */
|
||||
else category = 2; /* Long50/Long100 */
|
||||
input[MARKET_DIM + category] = 1.0f;
|
||||
|
||||
/* Layer 1: pre_act = w1 * input + b1, hidden = LeakyReLU(pre_act, 0.01) */
|
||||
float pre_act[CUR_HIDDEN];
|
||||
float hidden[CUR_HIDDEN];
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) {
|
||||
float sum = b1[h];
|
||||
for (int i = 0; i < CUR_INPUT; i++) {
|
||||
sum += w1[h * CUR_INPUT + i] * input[i];
|
||||
}
|
||||
pre_act[h] = sum;
|
||||
hidden[h] = (sum > 0.0f) ? sum : 0.01f * sum;
|
||||
}
|
||||
|
||||
/* Layer 2: pred = w2 * hidden + b2 (no activation) */
|
||||
float pred[CUR_OUTPUT];
|
||||
for (int o = 0; o < CUR_OUTPUT; o++) {
|
||||
float sum = b2[o];
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) {
|
||||
sum += w2[o * CUR_HIDDEN + h] * hidden[h];
|
||||
}
|
||||
pred[o] = sum;
|
||||
}
|
||||
|
||||
/* ---- Loss: MSE(pred, next_state[:MARKET_DIM]) ---- */
|
||||
float d_pred[CUR_OUTPUT];
|
||||
float inv_out = 2.0f / (float)CUR_OUTPUT;
|
||||
for (int o = 0; o < CUR_OUTPUT; o++) {
|
||||
d_pred[o] = (pred[o] - next_state[o]) * inv_out;
|
||||
}
|
||||
|
||||
/* ---- Backward: Layer 2 (warp-reduced atomics) ---- */
|
||||
float d_hidden[CUR_HIDDEN];
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) d_hidden[h] = 0.0f;
|
||||
|
||||
for (int o = 0; o < CUR_OUTPUT; o++) {
|
||||
{
|
||||
float val = warp_sum_cur(d_pred[o]);
|
||||
if ((threadIdx.x & 31) == 0) atomicAdd(&grad_b2[o], val);
|
||||
}
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) {
|
||||
{
|
||||
float val = warp_sum_cur(d_pred[o] * hidden[h]);
|
||||
if ((threadIdx.x & 31) == 0) atomicAdd(&grad_w2[o * CUR_HIDDEN + h], val);
|
||||
}
|
||||
d_hidden[h] += w2[o * CUR_HIDDEN + h] * d_pred[o];
|
||||
}
|
||||
}
|
||||
|
||||
/* ---- Backward: LeakyReLU ---- */
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) {
|
||||
if (pre_act[h] <= 0.0f) d_hidden[h] *= 0.01f;
|
||||
}
|
||||
|
||||
/* ---- Backward: Layer 1 (warp-reduced atomics) ---- */
|
||||
for (int h = 0; h < CUR_HIDDEN; h++) {
|
||||
{
|
||||
float val = warp_sum_cur(d_hidden[h]);
|
||||
if ((threadIdx.x & 31) == 0) atomicAdd(&grad_b1[h], val);
|
||||
}
|
||||
for (int i = 0; i < CUR_INPUT; i++) {
|
||||
{
|
||||
float val = warp_sum_cur(d_hidden[h] * input[i]);
|
||||
if ((threadIdx.x & 31) == 0) atomicAdd(&grad_w1[h * CUR_INPUT + i], val);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ================================================================ */
|
||||
/* Grid-wide barrier via atomic block-arrival counter */
|
||||
/* ================================================================ */
|
||||
/* Ensure all global memory writes (gradient atomicAdds) from this
|
||||
* block are visible to all other blocks before signalling arrival. */
|
||||
__threadfence();
|
||||
__syncthreads();
|
||||
|
||||
/* Thread 0 of each block increments the arrival counter.
|
||||
* The last block to arrive (counter == gridDim.x - 1) proceeds
|
||||
* to phase 3. All other blocks exit. */
|
||||
__shared__ int is_last_block;
|
||||
if (threadIdx.x == 0) {
|
||||
int arrived = atomicAdd(block_counter, 1);
|
||||
is_last_block = (arrived == (int)gridDim.x - 1) ? 1 : 0;
|
||||
}
|
||||
__syncthreads();
|
||||
if (!is_last_block) return;
|
||||
|
||||
/* ================================================================ */
|
||||
/* PHASE 3: Adam optimizer update (last block, grid-stride loop) */
|
||||
/* ================================================================ */
|
||||
/* The last-arriving block processes all CUR_TOTAL_PARAMS parameters
|
||||
* using blockDim.x threads in a stride loop. This avoids a second
|
||||
* kernel launch entirely. */
|
||||
int block_tid = threadIdx.x;
|
||||
int block_size = blockDim.x;
|
||||
|
||||
for (int i = block_tid; i < total_grad_elems; i += block_size) {
|
||||
/* Determine which param group and local offset */
|
||||
float* p; float* g; float* mm; float* vv;
|
||||
int local_i;
|
||||
if (i < w1_len) {
|
||||
p = w1; g = grad_w1; mm = adam_m_w1; vv = adam_v_w1; local_i = i;
|
||||
} else if (i < w1_len + b1_len) {
|
||||
p = b1; g = grad_b1; mm = adam_m_b1; vv = adam_v_b1; local_i = i - w1_len;
|
||||
} else if (i < w1_len + b1_len + w2_len) {
|
||||
p = w2; g = grad_w2; mm = adam_m_w2; vv = adam_v_w2; local_i = i - w1_len - b1_len;
|
||||
} else {
|
||||
p = b2; g = grad_b2; mm = adam_m_b2; vv = adam_v_b2; local_i = i - w1_len - b1_len - w2_len;
|
||||
}
|
||||
|
||||
float grad = g[local_i] / (float)batch_size;
|
||||
mm[local_i] = beta1 * mm[local_i] + (1.0f - beta1) * grad;
|
||||
vv[local_i] = beta2 * vv[local_i] + (1.0f - beta2) * grad * grad;
|
||||
float m_hat = mm[local_i] / (1.0f - powf(beta1, (float)adam_step));
|
||||
float v_hat = vv[local_i] / (1.0f - powf(beta2, (float)adam_step));
|
||||
p[local_i] -= lr * m_hat / (sqrtf(v_hat) + eps);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4,15 +4,16 @@
|
||||
//! can be uploaded to GPU while the current fold is still training.
|
||||
//! Call `upload_to_staging()` then `swap()` to seamlessly transition.
|
||||
//!
|
||||
//! ## CUDA stream synchronization
|
||||
//! ## CUDA event-based async synchronization
|
||||
//!
|
||||
//! On CUDA devices, `upload_to_staging()` issues PCIe transfers on the default
|
||||
//! stream. Before `swap()` promotes staging to active, it calls
|
||||
//! `sync_staging()` to synchronize the device — guaranteeing all in-flight
|
||||
//! transfers are complete. On CPU this is a no-op.
|
||||
//! stream, then records a lightweight `CudaEvent` marking the upload's
|
||||
//! completion point. `sync_staging()` polls the event via `is_complete()`
|
||||
//! (non-blocking) and only falls back to `event.synchronize()` if the upload
|
||||
//! has not yet landed. This eliminates the 2-4 ms host stall that a full
|
||||
//! `stream.synchronize()` caused at every fold boundary.
|
||||
//!
|
||||
//! When candle gains stream-aware tensor creation, the upload can be issued on
|
||||
//! a dedicated secondary stream for true overlap with training kernels.
|
||||
//! On CPU / Metal, synchronization is a no-op (tensors are immediately ready).
|
||||
|
||||
use candle_core::Device;
|
||||
use tracing::info;
|
||||
@@ -20,15 +21,22 @@ use tracing::info;
|
||||
use super::DqnGpuData;
|
||||
use crate::MLError;
|
||||
|
||||
#[cfg(feature = "cuda")]
|
||||
use candle_core::cuda_backend::cudarc::driver::CudaEvent;
|
||||
|
||||
/// Double-buffered GPU data loader.
|
||||
///
|
||||
/// While the trainer reads from `active()`, the next fold's data can be
|
||||
/// uploaded into `staging` via `upload_to_staging()`. Once the current
|
||||
/// fold finishes, `swap()` promotes staging → active in O(1).
|
||||
/// fold finishes, `swap()` promotes staging -> active in O(1).
|
||||
///
|
||||
/// `swap()` internally calls [`sync_staging()`](Self::sync_staging) to
|
||||
/// ensure all GPU transfers are complete before the trainer reads the new data.
|
||||
#[derive(Debug)]
|
||||
///
|
||||
/// On CUDA, synchronization uses a lightweight `CudaEvent` recorded after
|
||||
/// the upload rather than a full `stream.synchronize()`. The event is
|
||||
/// polled non-blockingly first; only if the upload is still in flight does
|
||||
/// the host block on `event.synchronize()`.
|
||||
pub struct DoubleBufferedLoader {
|
||||
active: Option<DqnGpuData>,
|
||||
staging: Option<DqnGpuData>,
|
||||
@@ -36,6 +44,26 @@ pub struct DoubleBufferedLoader {
|
||||
/// Whether the staging upload has been synchronized (GPU transfers complete).
|
||||
/// Set to `false` by `upload_to_staging()`, set to `true` by `sync_staging()`.
|
||||
staging_synced: bool,
|
||||
/// CUDA event recorded on the default stream immediately after the staging
|
||||
/// upload. `sync_staging()` waits on this event instead of synchronizing
|
||||
/// the entire stream. `None` until the first CUDA staging upload.
|
||||
#[cfg(feature = "cuda")]
|
||||
staging_event: Option<CudaEvent>,
|
||||
}
|
||||
|
||||
impl std::fmt::Debug for DoubleBufferedLoader {
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
|
||||
let mut s = f.debug_struct("DoubleBufferedLoader");
|
||||
s.field("active", &self.active)
|
||||
.field("staging", &self.staging)
|
||||
.field("device", &self.device)
|
||||
.field("staging_synced", &self.staging_synced);
|
||||
#[cfg(feature = "cuda")]
|
||||
{
|
||||
s.field("staging_event", &self.staging_event.as_ref().map(|_| "CudaEvent(...)"));
|
||||
}
|
||||
s.finish()
|
||||
}
|
||||
}
|
||||
|
||||
impl DoubleBufferedLoader {
|
||||
@@ -45,7 +73,9 @@ impl DoubleBufferedLoader {
|
||||
active: None,
|
||||
staging: None,
|
||||
device,
|
||||
staging_synced: true, // no pending upload → trivially synced
|
||||
staging_synced: true, // no pending upload -> trivially synced
|
||||
#[cfg(feature = "cuda")]
|
||||
staging_event: None,
|
||||
}
|
||||
}
|
||||
|
||||
@@ -56,7 +86,7 @@ impl DoubleBufferedLoader {
|
||||
) -> Result<(), MLError> {
|
||||
let gpu_data = DqnGpuData::upload(data, &self.device)?;
|
||||
info!(
|
||||
"DoubleBuffer: initial upload — {} bars, {:.1} MB VRAM",
|
||||
"DoubleBuffer: initial upload -- {} bars, {:.1} MB VRAM",
|
||||
gpu_data.num_bars,
|
||||
gpu_data.vram_bytes() as f64 / 1_048_576.0,
|
||||
);
|
||||
@@ -66,7 +96,8 @@ impl DoubleBufferedLoader {
|
||||
|
||||
/// Upload next fold's data into the staging slot (can overlap with training).
|
||||
///
|
||||
/// On CUDA the PCIe transfer is issued on the default stream. The data is
|
||||
/// On CUDA the PCIe transfer is issued on the default stream and a
|
||||
/// lightweight `CudaEvent` is recorded immediately after. The data is
|
||||
/// *not* guaranteed to be resident until [`sync_staging()`](Self::sync_staging)
|
||||
/// (or [`swap()`](Self::swap), which calls it internally) completes.
|
||||
pub fn upload_to_staging(
|
||||
@@ -75,24 +106,42 @@ impl DoubleBufferedLoader {
|
||||
) -> Result<(), MLError> {
|
||||
let gpu_data = DqnGpuData::upload(data, &self.device)?;
|
||||
info!(
|
||||
"DoubleBuffer: staging upload — {} bars, {:.1} MB VRAM",
|
||||
"DoubleBuffer: staging upload -- {} bars, {:.1} MB VRAM",
|
||||
gpu_data.num_bars,
|
||||
gpu_data.vram_bytes() as f64 / 1_048_576.0,
|
||||
);
|
||||
self.staging = Some(gpu_data);
|
||||
self.staging_synced = false; // upload in-flight until sync
|
||||
|
||||
// Record a CudaEvent on the default stream so sync_staging() can wait
|
||||
// on just this upload rather than synchronizing the entire stream.
|
||||
#[cfg(feature = "cuda")]
|
||||
{
|
||||
if let Device::Cuda(ref cuda_dev) = self.device {
|
||||
let stream = cuda_dev.cuda_stream();
|
||||
let event = stream.record_event(None).map_err(|e| {
|
||||
MLError::DeviceError(format!(
|
||||
"DoubleBuffer: staging event record failed: {e}"
|
||||
))
|
||||
})?;
|
||||
self.staging_event = Some(event);
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Synchronize the CUDA device to ensure all staging upload transfers are
|
||||
/// complete.
|
||||
/// Ensure the staging upload has landed on the device.
|
||||
///
|
||||
/// On CPU / Metal this is a no-op. On CUDA it synchronizes the default
|
||||
/// stream, guaranteeing that the PCIe transfer issued by
|
||||
/// [`upload_to_staging()`](Self::upload_to_staging) has landed in device
|
||||
/// memory.
|
||||
/// On CPU / Metal this is a no-op. On CUDA it first polls the staging
|
||||
/// event with `is_complete()` (non-blocking). If the upload has already
|
||||
/// finished (the common case -- training takes far longer than upload),
|
||||
/// this returns immediately without any host stall. Otherwise it falls
|
||||
/// back to `event.synchronize()`, which is still cheaper than a full
|
||||
/// `stream.synchronize()` because it only waits for work up to the
|
||||
/// recorded event, not all subsequent stream activity.
|
||||
///
|
||||
/// It is safe (but wasteful) to call this multiple times — subsequent
|
||||
/// It is safe (but wasteful) to call this multiple times -- subsequent
|
||||
/// calls after the first are no-ops.
|
||||
///
|
||||
/// [`swap()`](Self::swap) calls this internally, so callers only need to
|
||||
@@ -104,23 +153,28 @@ impl DoubleBufferedLoader {
|
||||
|
||||
#[cfg(feature = "cuda")]
|
||||
{
|
||||
if let Device::Cuda(ref cuda_dev) = self.device {
|
||||
cuda_dev
|
||||
.cuda_stream()
|
||||
.synchronize()
|
||||
.map_err(|e| {
|
||||
if let Some(ref event) = self.staging_event {
|
||||
// Fast path: non-blocking poll. If the upload finished while
|
||||
// training was running (the typical case), we avoid any host
|
||||
// block at all.
|
||||
if !event.is_complete() {
|
||||
// Slow path: upload still in flight -- block until just
|
||||
// this event (not the whole stream) completes.
|
||||
event.synchronize().map_err(|e| {
|
||||
MLError::DeviceError(format!(
|
||||
"DoubleBuffer: CUDA stream sync failed: {e}"
|
||||
"DoubleBuffer: staging event sync failed: {e}"
|
||||
))
|
||||
})?;
|
||||
}
|
||||
}
|
||||
// If no event was recorded (non-CUDA device path), nothing to wait on.
|
||||
}
|
||||
|
||||
self.staging_synced = true;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Swap staging → active. Old active data is dropped (GPU memory freed).
|
||||
/// Swap staging -> active. Old active data is dropped (GPU memory freed).
|
||||
///
|
||||
/// Calls [`sync_staging()`](Self::sync_staging) first to ensure the upload
|
||||
/// is fully resident on the device before the trainer reads from it.
|
||||
@@ -135,9 +189,9 @@ impl DoubleBufferedLoader {
|
||||
})?;
|
||||
let old_bars = self.active.as_ref().map_or(0, |d| d.num_bars);
|
||||
self.active = Some(staging);
|
||||
self.staging_synced = true; // staging is gone → trivially synced
|
||||
self.staging_synced = true; // staging is gone -> trivially synced
|
||||
info!(
|
||||
"DoubleBuffer: swapped (old {} bars → new {} bars)",
|
||||
"DoubleBuffer: swapped (old {} bars -> new {} bars)",
|
||||
old_bars,
|
||||
self.active.as_ref().map_or(0, |d| d.num_bars),
|
||||
);
|
||||
@@ -245,7 +299,7 @@ mod tests {
|
||||
// After upload, staging is not yet synced
|
||||
assert!(!loader.is_staging_synced());
|
||||
|
||||
// sync_staging on CPU is a no-op but marks synced
|
||||
// sync_staging on CUDA uses event-based sync
|
||||
loader.sync_staging().unwrap();
|
||||
assert!(loader.is_staging_synced());
|
||||
}
|
||||
@@ -287,7 +341,7 @@ mod tests {
|
||||
#[test]
|
||||
fn test_double_buffer_synced_after_new() {
|
||||
let loader = DoubleBufferedLoader::new(cuda_device());
|
||||
// Fresh loader has no pending uploads → trivially synced
|
||||
// Fresh loader has no pending uploads -> trivially synced
|
||||
assert!(loader.is_staging_synced());
|
||||
}
|
||||
|
||||
|
||||
@@ -2,9 +2,14 @@
|
||||
* Zero-Roundtrip DQN Experience Collection Kernel
|
||||
*
|
||||
* Requires common_device_functions.cuh prepended via NVRTC source concatenation.
|
||||
* Launch config: grid=(ceil(N/32),1,1), block=(32,1,1).
|
||||
* Each thread processes one independent episode of L timesteps.
|
||||
* 128 episodes x 500 timesteps = 64,000 experiences per launch.
|
||||
*
|
||||
* Standard kernel: grid=(ceil(N/block),1,1), block=(256,1,1).
|
||||
* Each thread processes one independent episode of L timesteps.
|
||||
*
|
||||
* Warp kernel (sm_90+): grid=(ceil(N/EPB),1,1), block=(32*EPB,1,1).
|
||||
* EPB = EPISODES_PER_BLOCK warps per block, each warp handles one episode.
|
||||
* Multiple warps share cooperative weight tile loads via __syncthreads().
|
||||
* Occupancy: EPB=4 at N=128 → 128 warps = 4,096 threads vs 1,024 at EPB=1.
|
||||
*/
|
||||
|
||||
/* DQN-specific layer sizes — overridable via NVRTC #define injection */
|
||||
@@ -288,6 +293,10 @@ __device__ __forceinline__ float max_arr(const float* vals, int len) {
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
/* All TILE_LAYER_WARP macros use __syncthreads() for cooperative weight loading.
|
||||
* With EPISODES_PER_BLOCK > 1, multiple warps share the same shmem tile;
|
||||
* __syncthreads() ensures all warps complete their load portion before
|
||||
* any warp reads from the tile. Safe for single-warp blocks too. */
|
||||
#define TILE_LAYER_WARP_NOISY(W_global, b_global, input_dist, output_dist, in_d, out_d, act, shmem_w, shmem_b, sigma, rng_ptr, lane) \
|
||||
do { \
|
||||
for (int _tile = 0; _tile < ((out_d) + SHMEM_TILE_ROWS - 1) / SHMEM_TILE_ROWS; _tile++) { \
|
||||
@@ -295,10 +304,10 @@ __device__ __forceinline__ float max_arr(const float* vals, int len) {
|
||||
int _tr = SHMEM_MIN(SHMEM_TILE_ROWS, (out_d) - _ts); \
|
||||
cooperative_load_tile(shmem_w, (W_global) + _ts * (in_d), _tr * (in_d)); \
|
||||
cooperative_load_tile(shmem_b, (b_global) + _ts, _tr); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
warp_noisy_matvec_leaky_relu_shmem(shmem_w, shmem_b, input_dist, output_dist, \
|
||||
in_d, out_d, _ts, _tr, act, sigma, rng_ptr, lane); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
@@ -311,10 +320,10 @@ __device__ __forceinline__ float max_arr(const float* vals, int len) {
|
||||
int _tr = SHMEM_MIN(SHMEM_TILE_ROWS, (out_d) - _ts); \
|
||||
cooperative_load_tile(shmem_w, (W_global) + _ts * (in_d), _tr * (in_d)); \
|
||||
cooperative_load_tile(shmem_b, (b_global) + _ts, _tr); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
warp_matvec_broadcast_shmem(shmem_w, shmem_b, input_dist, output, \
|
||||
in_d, out_d, _ts, _tr, act, lane); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
@@ -325,10 +334,10 @@ __device__ __forceinline__ float max_arr(const float* vals, int len) {
|
||||
int _tr = SHMEM_MIN(SHMEM_TILE_ROWS, (out_d) - _ts); \
|
||||
cooperative_load_tile(shmem_w, (W_global) + _ts * (in_d), _tr * (in_d)); \
|
||||
cooperative_load_tile(shmem_b, (b_global) + _ts, _tr); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
warp_noisy_matvec_broadcast_shmem(shmem_w, shmem_b, input_dist, output, \
|
||||
in_d, out_d, _ts, _tr, act, sigma, rng_ptr, lane); \
|
||||
__syncwarp(0xFFFFFFFF); \
|
||||
__syncthreads(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
@@ -2251,9 +2260,10 @@ extern "C" __global__ void dqn_full_experience_kernel(
|
||||
* lane 0 extras: cur_scratch[64] + state_full[48] + next_state_full[48]
|
||||
* = 640 bytes (only lane 0)
|
||||
*
|
||||
* Launch config: grid=(N, 1, 1), block=(32, 1, 1).
|
||||
* One block per episode. All 32 lanes must participate in __syncthreads()
|
||||
* and cooperative_load_tile together.
|
||||
* Launch config: grid=(ceil(N/EPB), 1, 1), block=(32*EPB, 1, 1).
|
||||
* EPB = EPISODES_PER_BLOCK warps per block (injected via NVRTC).
|
||||
* All warps cooperatively load weight tiles; each warp handles one episode.
|
||||
* All threads must participate in __syncthreads() and cooperative_load_tile.
|
||||
*
|
||||
* C51 distributional mode is supported via q_forward_distributional_warp_shmem
|
||||
* which uses broadcast output for the small atom layers (v2, a2).
|
||||
@@ -2386,9 +2396,13 @@ extern "C" __global__ void dqn_full_experience_kernel_warp(
|
||||
float epoch_dsr_var = epoch_state[6];
|
||||
float epoch_step_count = epoch_state[7];
|
||||
|
||||
/* ---- Thread / warp identity ---- */
|
||||
int episode_id = blockIdx.x; /* one block per episode */
|
||||
int lane_id = threadIdx.x; /* 0..31 within the warp */
|
||||
/* ---- Thread / warp identity ----
|
||||
* With EPISODES_PER_BLOCK > 1, each block contains multiple warps.
|
||||
* Each warp handles one independent episode; all warps in a block
|
||||
* share cooperative weight tile loads through __syncthreads(). */
|
||||
int warp_id = threadIdx.x / 32; /* 0..EPISODES_PER_BLOCK-1 */
|
||||
int lane_id = threadIdx.x % 32; /* 0..31 within the warp */
|
||||
int episode_id = blockIdx.x * EPISODES_PER_BLOCK + warp_id;
|
||||
int tid_valid = (episode_id < N) ? 1 : 0;
|
||||
|
||||
/* ---- Load per-episode state (lane 0 owns simulation state) ---- */
|
||||
@@ -3234,14 +3248,16 @@ extern "C" __global__ void dqn_full_experience_kernel_warp(
|
||||
rng_states[episode_id] = rng;
|
||||
}
|
||||
|
||||
/* ---- Epoch state writeback: last block, lane 0 ---- */
|
||||
/* ---- Epoch state writeback: last valid episode, lane 0 ---- */
|
||||
// Only vol_ema, dsr_mean, dsr_var, step_count are updated per-kernel.
|
||||
// Portfolio state is per-episode (in portfolio_states), not per-epoch.
|
||||
// NOTE: Picks the episode processed by last block's thread 0 as the
|
||||
// representative seed for the next epoch. Not a cross-episode reduction.
|
||||
// This is acceptable: all episodes see the same market data in temporal
|
||||
// order, so accumulators converge to similar values across episodes.
|
||||
if (threadIdx.x == 0 && blockIdx.x == gridDim.x - 1) {
|
||||
// NOTE: Picks the last valid episode as the representative seed for the
|
||||
// next epoch. Not a cross-episode reduction. This is acceptable: all
|
||||
// episodes see the same market data in temporal order, so accumulators
|
||||
// converge to similar values across episodes.
|
||||
// With EPISODES_PER_BLOCK > 1, episode N-1 may not be warp 0 of the
|
||||
// last block. Use episode_id == N-1 as the writeback condition.
|
||||
if (lane_id == 0 && episode_id == N - 1) {
|
||||
epoch_state[0] = local_vol_ema;
|
||||
epoch_state[1] = local_median_vol;
|
||||
if (use_dsr) {
|
||||
|
||||
@@ -9,10 +9,13 @@
|
||||
//!
|
||||
//! Architecture: `[MARKET_DIM+3] -> [128] LeakyReLU -> [MARKET_DIM]` (MARKET_DIM=42: 11_954 params)
|
||||
//!
|
||||
//! Kernels:
|
||||
//! Kernels (fused path -- 2 launches per step):
|
||||
//! - `curiosity_shift_states`: builds shifted next_states from states buffer
|
||||
//! - `curiosity_forward_backward`: forward + backward pass, atomicAdd gradients
|
||||
//! - `curiosity_adam_step`: Adam optimizer step with bias correction
|
||||
//! - `curiosity_fused_zero_fwd_bwd_adam`: zeros grads + forward/backward + Adam in one launch
|
||||
//!
|
||||
//! Legacy kernels (kept for fallback, not used in hot path):
|
||||
//! - `curiosity_forward_backward`: standalone forward + backward pass
|
||||
//! - `curiosity_adam_step` / `curiosity_adam_step_fused`: standalone Adam optimizers
|
||||
|
||||
use std::sync::{Arc, OnceLock};
|
||||
|
||||
@@ -79,6 +82,8 @@ pub struct GpuCuriosityTrainer {
|
||||
fwd_bwd_func: CudaFunction,
|
||||
adam_func: CudaFunction,
|
||||
adam_fused_func: CudaFunction,
|
||||
/// Fully fused kernel: zero grads + fwd/bwd + Adam in one launch.
|
||||
fused_zero_fwd_bwd_adam_func: CudaFunction,
|
||||
|
||||
// Gradient buffers
|
||||
grad_w1: CudaSlice<f32>, // [CUR_W1_LEN]
|
||||
@@ -101,6 +106,9 @@ pub struct GpuCuriosityTrainer {
|
||||
// Shifted next_states buffer
|
||||
next_states_buf: CudaSlice<f32>,
|
||||
|
||||
/// Atomic block-arrival counter for fused kernel grid-wide sync (single i32 on GPU).
|
||||
block_counter: CudaSlice<i32>,
|
||||
|
||||
// Adam step counter (1-based)
|
||||
step: i32,
|
||||
|
||||
@@ -111,10 +119,11 @@ pub struct GpuCuriosityTrainer {
|
||||
buf_capacity: usize,
|
||||
}
|
||||
|
||||
/// Launch Adam optimizer step for one parameter group.
|
||||
/// Launch Adam optimizer step for one parameter group (legacy, kept for fallback).
|
||||
///
|
||||
/// Free function to avoid borrow conflicts when calling from
|
||||
/// `train_on_collector_buffers` (which mutably borrows multiple fields).
|
||||
#[allow(dead_code)]
|
||||
fn launch_adam_step(
|
||||
stream: &CudaStream,
|
||||
adam_func: &CudaFunction,
|
||||
@@ -193,6 +202,11 @@ impl GpuCuriosityTrainer {
|
||||
let adam_fused_func = module.load_function("curiosity_adam_step_fused").map_err(|e| {
|
||||
MLError::ModelError(format!("curiosity_adam_step_fused load: {e}"))
|
||||
})?;
|
||||
let fused_zero_fwd_bwd_adam_func = module
|
||||
.load_function("curiosity_fused_zero_fwd_bwd_adam")
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("curiosity_fused_zero_fwd_bwd_adam load: {e}"))
|
||||
})?;
|
||||
|
||||
// ---- Allocate gradient buffers ----
|
||||
let grad_w1 = stream.alloc_zeros::<f32>(CUR_W1_LEN).map_err(|e| {
|
||||
@@ -243,6 +257,11 @@ impl GpuCuriosityTrainer {
|
||||
MLError::ModelError(format!("alloc next_states_buf: {e}"))
|
||||
})?;
|
||||
|
||||
// ---- Allocate atomic block-arrival counter for fused kernel ----
|
||||
let block_counter = stream.alloc_zeros::<i32>(1).map_err(|e| {
|
||||
MLError::ModelError(format!("alloc block_counter: {e}"))
|
||||
})?;
|
||||
|
||||
debug!(
|
||||
state_dim,
|
||||
max_samples,
|
||||
@@ -256,6 +275,7 @@ impl GpuCuriosityTrainer {
|
||||
fwd_bwd_func,
|
||||
adam_func,
|
||||
adam_fused_func,
|
||||
fused_zero_fwd_bwd_adam_func,
|
||||
grad_w1,
|
||||
grad_b1,
|
||||
grad_w2,
|
||||
@@ -269,6 +289,7 @@ impl GpuCuriosityTrainer {
|
||||
adam_v_w2,
|
||||
adam_v_b2,
|
||||
next_states_buf,
|
||||
block_counter,
|
||||
step: 0,
|
||||
state_dim,
|
||||
buf_capacity: max_samples,
|
||||
@@ -317,8 +338,9 @@ impl GpuCuriosityTrainer {
|
||||
let sd_i32 = sd as i32;
|
||||
let n_i32 = n_train as i32;
|
||||
|
||||
// ---- Step 1: Build shifted next_states buffer ----
|
||||
// ---- Launch 1/2: Build shifted next_states buffer ----
|
||||
// next_states[i] = states[i + state_dim] (shift by one timestep)
|
||||
// Separate launch because grid dimensions differ from the fwd/bwd grid.
|
||||
let shift_total = n_train * sd;
|
||||
let shift_cfg = LaunchConfig {
|
||||
grid_dim: (((shift_total as u32) + 255) / 256, 1, 1),
|
||||
@@ -338,80 +360,73 @@ impl GpuCuriosityTrainer {
|
||||
})?;
|
||||
}
|
||||
|
||||
// ---- Step 2: Zero gradient buffers via memset (faster than kernel) ----
|
||||
self.stream.memset_zeros(&mut self.grad_w1).map_err(|e| {
|
||||
MLError::ModelError(format!("memset grad_w1: {e}"))
|
||||
})?;
|
||||
self.stream.memset_zeros(&mut self.grad_b1).map_err(|e| {
|
||||
MLError::ModelError(format!("memset grad_b1: {e}"))
|
||||
})?;
|
||||
self.stream.memset_zeros(&mut self.grad_w2).map_err(|e| {
|
||||
MLError::ModelError(format!("memset grad_w2: {e}"))
|
||||
})?;
|
||||
self.stream.memset_zeros(&mut self.grad_b2).map_err(|e| {
|
||||
MLError::ModelError(format!("memset grad_b2: {e}"))
|
||||
})?;
|
||||
// ---- Launch 2/2: Fused zero + forward/backward + Adam ----
|
||||
// Single kernel launch replaces 4 memset + fwd_bwd + adam_fused = 6 dispatches.
|
||||
self.step += 1;
|
||||
let step = self.step;
|
||||
let bs_i32 = n_train as i32;
|
||||
|
||||
// ---- Step 3: Forward + backward pass ----
|
||||
let fwd_cfg = LaunchConfig {
|
||||
// Zero the block-arrival counter before launch.
|
||||
self.stream
|
||||
.memset_zeros(&mut self.block_counter)
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("memset block_counter: {e}"))
|
||||
})?;
|
||||
|
||||
// Grid covers N training samples (one thread per sample for fwd/bwd).
|
||||
// The last block to finish also handles Adam update for all params.
|
||||
let fused_cfg = LaunchConfig {
|
||||
grid_dim: (((n_train as u32) + 255) / 256, 1, 1),
|
||||
block_dim: (256, 1, 1),
|
||||
shared_mem_bytes: 0,
|
||||
};
|
||||
unsafe {
|
||||
self.stream
|
||||
.launch_builder(&self.fwd_bwd_func)
|
||||
.launch_builder(&self.fused_zero_fwd_bwd_adam_func)
|
||||
// Experience data
|
||||
.arg(states)
|
||||
.arg(actions)
|
||||
.arg(&self.next_states_buf)
|
||||
.arg(&weights.w1)
|
||||
.arg(&weights.b1)
|
||||
.arg(&weights.w2)
|
||||
.arg(&weights.b2)
|
||||
// Weights (updated in-place by Adam)
|
||||
.arg(&mut weights.w1)
|
||||
.arg(&mut weights.b1)
|
||||
.arg(&mut weights.w2)
|
||||
.arg(&mut weights.b2)
|
||||
// Gradient accumulators
|
||||
.arg(&mut self.grad_w1)
|
||||
.arg(&mut self.grad_b1)
|
||||
.arg(&mut self.grad_w2)
|
||||
.arg(&mut self.grad_b2)
|
||||
// Adam first moment
|
||||
.arg(&mut self.adam_m_w1)
|
||||
.arg(&mut self.adam_m_b1)
|
||||
.arg(&mut self.adam_m_w2)
|
||||
.arg(&mut self.adam_m_b2)
|
||||
// Adam second moment
|
||||
.arg(&mut self.adam_v_w1)
|
||||
.arg(&mut self.adam_v_b1)
|
||||
.arg(&mut self.adam_v_w2)
|
||||
.arg(&mut self.adam_v_b2)
|
||||
// Block-arrival counter
|
||||
.arg(&mut self.block_counter)
|
||||
// Scalar parameters
|
||||
.arg(&n_i32)
|
||||
.arg(&sd_i32)
|
||||
.launch(fwd_cfg)
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("curiosity_forward_backward launch: {e}"))
|
||||
})?;
|
||||
}
|
||||
|
||||
// ---- Step 4: Increment step counter ----
|
||||
self.step += 1;
|
||||
let step = self.step;
|
||||
|
||||
// ---- Step 5: Fused Adam optimizer step (single launch for all 4 param groups) ----
|
||||
let total_params = CUR_W1_LEN + CUR_B1_LEN + CUR_W2_LEN + CUR_B2_LEN;
|
||||
let fused_cfg = LaunchConfig {
|
||||
grid_dim: (((total_params as u32) + 255) / 256, 1, 1),
|
||||
block_dim: (256, 1, 1),
|
||||
shared_mem_bytes: 0,
|
||||
};
|
||||
let n0 = CUR_W1_LEN as i32;
|
||||
let n1 = CUR_B1_LEN as i32;
|
||||
let n2 = CUR_W2_LEN as i32;
|
||||
let n3 = CUR_B2_LEN as i32;
|
||||
let bs_i32 = n_train as i32;
|
||||
unsafe {
|
||||
self.stream
|
||||
.launch_builder(&self.adam_fused_func)
|
||||
.arg(&mut weights.w1).arg(&self.grad_w1).arg(&mut self.adam_m_w1).arg(&mut self.adam_v_w1).arg(&n0)
|
||||
.arg(&mut weights.b1).arg(&self.grad_b1).arg(&mut self.adam_m_b1).arg(&mut self.adam_v_b1).arg(&n1)
|
||||
.arg(&mut weights.w2).arg(&self.grad_w2).arg(&mut self.adam_m_w2).arg(&mut self.adam_v_w2).arg(&n2)
|
||||
.arg(&mut weights.b2).arg(&self.grad_b2).arg(&mut self.adam_m_b2).arg(&mut self.adam_v_b2).arg(&n3)
|
||||
.arg(&bs_i32)
|
||||
.arg(&ADAM_LR).arg(&ADAM_BETA1).arg(&ADAM_BETA2).arg(&ADAM_EPS).arg(&step)
|
||||
.arg(&ADAM_LR)
|
||||
.arg(&ADAM_BETA1)
|
||||
.arg(&ADAM_BETA2)
|
||||
.arg(&ADAM_EPS)
|
||||
.arg(&step)
|
||||
.launch(fused_cfg)
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("curiosity_adam_step_fused launch: {e}"))
|
||||
MLError::ModelError(format!(
|
||||
"curiosity_fused_zero_fwd_bwd_adam launch: {e}"
|
||||
))
|
||||
})?;
|
||||
}
|
||||
|
||||
debug!(step, n_train, "curiosity GPU training step complete");
|
||||
debug!(step, n_train, "curiosity GPU training step complete (fused)");
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
@@ -268,6 +268,9 @@ pub struct GpuExperienceCollector {
|
||||
warp_kernel_func: Option<CudaFunction>,
|
||||
/// Whether to use warp-cooperative kernel (sm_70+ detected).
|
||||
use_warp_kernel: bool,
|
||||
/// Warp kernel: episodes packed per thread block (1/4/8).
|
||||
/// Multiple warps per block share cooperative weight tile loads for higher SM occupancy.
|
||||
episodes_per_block: usize,
|
||||
/// Number of episodes buffers were allocated for (from config, not MAX constant).
|
||||
alloc_episodes: usize,
|
||||
/// Number of timesteps buffers were allocated for (from config, not MAX constant).
|
||||
@@ -399,6 +402,47 @@ impl GpuExperienceCollector {
|
||||
// PLUS advantage head output (ADV_H elements at offset DIST_SIZE(VALUE_H))
|
||||
// So scratch1 must hold max(SHARED_H1, VALUE_H + ADV_H) in distributed form.
|
||||
let scratch1_dim = shared_h1.max(value_h + adv_h);
|
||||
|
||||
// ---- Warp kernel SM occupancy: episodes per block ----
|
||||
// H100 has 456 SMs (132 in H100 SXM, 456 is theoretical max for GH200).
|
||||
// At n_episodes=32 with 1 episode/block, only 32 blocks × 32 threads = 1024
|
||||
// threads = 1.76% occupancy. Packing multiple warps per block increases
|
||||
// occupancy by amortizing cooperative weight tile loads across warps.
|
||||
//
|
||||
// Adaptive scaling:
|
||||
// n_episodes >= 1024: 8 episodes/block (256 threads/block)
|
||||
// n_episodes >= 256: 4 episodes/block (128 threads/block)
|
||||
// otherwise: 1 episode/block (32 threads/block, legacy)
|
||||
let episodes_per_block: usize = if alloc_episodes >= 1024 {
|
||||
8
|
||||
} else if alloc_episodes >= 256 {
|
||||
4
|
||||
} else {
|
||||
1
|
||||
};
|
||||
|
||||
// TILE_LAYER_WARP_CLEAN override: when multiple warps share a block,
|
||||
// cooperative_load_tile distributes across blockDim.x threads (not just 32).
|
||||
// __syncthreads() ensures all warps complete loading before any warp reads.
|
||||
// This is also correct for EPISODES_PER_BLOCK=1 (equivalent to __syncwarp).
|
||||
//
|
||||
// Defined BEFORE common_device_functions.cuh so the #ifndef guard in .cuh
|
||||
// picks up our version instead of the default __syncwarp version.
|
||||
let tile_layer_warp_clean_override = "\
|
||||
#define TILE_LAYER_WARP_CLEAN(W_global, b_global, input_dist, output_dist, in_d, out_d, act, shmem_w, shmem_b, lane) \\\n\
|
||||
do { \\\n\
|
||||
for (int _tile = 0; _tile < ((out_d) + SHMEM_TILE_ROWS - 1) / SHMEM_TILE_ROWS; _tile++) { \\\n\
|
||||
int _ts = _tile * SHMEM_TILE_ROWS; \\\n\
|
||||
int _tr = SHMEM_MIN(SHMEM_TILE_ROWS, (out_d) - _ts); \\\n\
|
||||
cooperative_load_tile(shmem_w, (W_global) + _ts * (in_d), _tr * (in_d)); \\\n\
|
||||
cooperative_load_tile(shmem_b, (b_global) + _ts, _tr); \\\n\
|
||||
__syncthreads(); \\\n\
|
||||
warp_matvec_leaky_relu_shmem(shmem_w, shmem_b, input_dist, output_dist, \\\n\
|
||||
in_d, out_d, _ts, _tr, act, lane); \\\n\
|
||||
__syncthreads(); \\\n\
|
||||
} \\\n\
|
||||
} while (0)\n";
|
||||
|
||||
let dim_overrides = format!(
|
||||
"#define NOISY_MAX_DIM {noisy_max_dim}\n\
|
||||
#define STATE_DIM {state_dim}\n\
|
||||
@@ -412,7 +456,12 @@ impl GpuExperienceCollector {
|
||||
#define SCRATCH1_DIM {scratch1_dim}\n\
|
||||
#define NUM_ATOMS_MAX {num_atoms_max}\n\
|
||||
#define SHMEM_MAX_IN_DIM {shmem_max_in_dim}\n\
|
||||
#define SHMEM_TILE_ROWS {shmem_tile_rows}\n"
|
||||
#define SHMEM_TILE_ROWS {shmem_tile_rows}\n\
|
||||
#define EPISODES_PER_BLOCK {episodes_per_block}\n\
|
||||
#ifndef SHMEM_MIN\n\
|
||||
#define SHMEM_MIN(a, b) (((a) < (b)) ? (a) : (b))\n\
|
||||
#endif\n\
|
||||
{tile_layer_warp_clean_override}\n"
|
||||
);
|
||||
// dim_overrides BEFORE common_src so #ifndef guards in .cuh/.cu
|
||||
// skip their defaults — no macro redefinition warnings from NVRTC.
|
||||
@@ -420,7 +469,8 @@ impl GpuExperienceCollector {
|
||||
info!(
|
||||
"GPU experience collector: compiling kernel with dims state={state_dim} market={market_dim} \
|
||||
shared=[{shared_h1},{shared_h2}] value={value_h} adv={adv_h} atoms_max={num_atoms_max} \
|
||||
shmem_max_in={shmem_max_in_dim} shmem_tile_rows={shmem_tile_rows}"
|
||||
shmem_max_in={shmem_max_in_dim} shmem_tile_rows={shmem_tile_rows} \
|
||||
episodes_per_block={episodes_per_block}"
|
||||
);
|
||||
let context = stream.context();
|
||||
|
||||
@@ -843,6 +893,7 @@ impl GpuExperienceCollector {
|
||||
shmem_tile_rows,
|
||||
warp_kernel_func,
|
||||
use_warp_kernel,
|
||||
episodes_per_block,
|
||||
alloc_episodes,
|
||||
alloc_timesteps,
|
||||
online_weights,
|
||||
@@ -1137,9 +1188,16 @@ impl GpuExperienceCollector {
|
||||
|
||||
let (launch_config, active_kernel) =
|
||||
if let (true, Some(warp_fn)) = (use_warp, &self.warp_kernel_func) {
|
||||
// Multi-warp packing: EPISODES_PER_BLOCK warps per block.
|
||||
// Each warp (32 threads) handles one episode; all warps in a
|
||||
// block share cooperative weight tile loads via __syncthreads().
|
||||
// At EPB=4, n=128 → grid=(32,1,1), block=(128,1,1) = 4096 threads.
|
||||
let epb = self.episodes_per_block as u32;
|
||||
let block_x = 32 * epb;
|
||||
let grid_x = (n + epb - 1) / epb;
|
||||
let cfg = LaunchConfig {
|
||||
grid_dim: (n, 1, 1),
|
||||
block_dim: (32, 1, 1),
|
||||
grid_dim: (grid_x, 1, 1),
|
||||
block_dim: (block_x, 1, 1),
|
||||
shared_mem_bytes: shmem_bytes,
|
||||
};
|
||||
(cfg, warp_fn)
|
||||
@@ -1160,6 +1218,7 @@ impl GpuExperienceCollector {
|
||||
grid_x = launch_config.grid_dim.0,
|
||||
block_x = launch_config.block_dim.0,
|
||||
shared_mem_kb = shmem_bytes / 1024,
|
||||
episodes_per_block = self.episodes_per_block,
|
||||
epsilon = config.epsilon,
|
||||
gamma = config.gamma,
|
||||
warp_kernel = use_warp,
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
use std::sync::Arc;
|
||||
|
||||
use candle_core::cuda_backend::cudarc;
|
||||
use cudarc::driver::{CudaFunction, CudaSlice, CudaStream, LaunchConfig, PushKernelArg};
|
||||
use cudarc::driver::{CudaFunction, CudaSlice, CudaStream, DevicePtr, LaunchConfig, PushKernelArg};
|
||||
use cudarc::nvrtc::Ptx;
|
||||
use candle_nn::VarMap;
|
||||
use tracing::{debug, info};
|
||||
@@ -167,6 +167,12 @@ pub struct GpuPpoExperienceCollector {
|
||||
advantages_out: CudaSlice<f32>, // [MAX_EPISODES * MAX_TIMESTEPS]
|
||||
returns_out: CudaSlice<f32>, // [MAX_EPISODES * MAX_TIMESTEPS]
|
||||
dones_out: CudaSlice<i32>, // [MAX_EPISODES * MAX_TIMESTEPS]
|
||||
|
||||
// Consolidated readback staging: D2D gather then single DtoH per dtype
|
||||
readback_f32_staging: CudaSlice<f32>,
|
||||
readback_f32_host: Vec<f32>,
|
||||
readback_i32_staging: CudaSlice<i32>,
|
||||
readback_i32_host: Vec<i32>,
|
||||
}
|
||||
|
||||
impl GpuPpoExperienceCollector {
|
||||
@@ -327,6 +333,25 @@ impl GpuPpoExperienceCollector {
|
||||
MLError::ModelError(format!("Failed to alloc dones_out: {e}"))
|
||||
})?;
|
||||
|
||||
// ---- Step 6b: Allocate consolidated readback staging buffers ----
|
||||
// f32 staging: states (N*L*STATE_DIM) + log_probs (N*L) + advantages (N*L) + returns (N*L)
|
||||
let f32_staging_len = total_output * STATE_DIM + 3 * total_output;
|
||||
let readback_f32_staging = stream
|
||||
.alloc_zeros::<f32>(f32_staging_len)
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("Failed to alloc readback_f32_staging: {e}"))
|
||||
})?;
|
||||
let readback_f32_host = vec![0.0_f32; f32_staging_len];
|
||||
|
||||
// i32 staging: actions (N*L) + done_flags (N*L)
|
||||
let i32_staging_len = 2 * total_output;
|
||||
let readback_i32_staging = stream
|
||||
.alloc_zeros::<i32>(i32_staging_len)
|
||||
.map_err(|e| {
|
||||
MLError::ModelError(format!("Failed to alloc readback_i32_staging: {e}"))
|
||||
})?;
|
||||
let readback_i32_host = vec![0_i32; i32_staging_len];
|
||||
|
||||
// ---- Step 7: Log buffer sizes ----
|
||||
let per_episode_bytes = (PORTFOLIO_STATE_SIZE + BARRIER_STATE_SIZE) * 4
|
||||
+ DIVERSITY_WINDOW * 4
|
||||
@@ -360,6 +385,10 @@ impl GpuPpoExperienceCollector {
|
||||
advantages_out,
|
||||
returns_out,
|
||||
dones_out,
|
||||
readback_f32_staging,
|
||||
readback_f32_host,
|
||||
readback_i32_staging,
|
||||
readback_i32_host,
|
||||
})
|
||||
}
|
||||
|
||||
@@ -521,47 +550,86 @@ impl GpuPpoExperienceCollector {
|
||||
})?;
|
||||
}
|
||||
|
||||
// ---- Step 6: Download output buffers (only N*L elements) ----
|
||||
// ---- Step 6: Consolidated readback (D2D gather + 2 DtoH) ----
|
||||
// 4 f32 buffers (states + log_probs + advantages + returns) → 1 DtoH
|
||||
// 2 i32 buffers (actions + done_flags) → 1 DtoH
|
||||
let total = n_episodes * timesteps;
|
||||
let states_count = total * STATE_DIM;
|
||||
let total_f32 = states_count + 3 * total;
|
||||
let total_i32 = 2 * total;
|
||||
|
||||
let states_view = self.states_out.slice(..total * STATE_DIM);
|
||||
let actions_view = self.actions_out.slice(..total);
|
||||
let log_probs_view = self.log_probs_out.slice(..total);
|
||||
let advantages_view = self.advantages_out.slice(..total);
|
||||
let returns_view = self.returns_out.slice(..total);
|
||||
let dones_view = self.dones_out.slice(..total);
|
||||
// D2D gather f32 buffers into readback_f32_staging
|
||||
{
|
||||
let (dst_base, _dst_sync) = self.readback_f32_staging.device_ptr(&self.stream);
|
||||
let mut byte_offset: usize = 0;
|
||||
let f32_size = std::mem::size_of::<f32>();
|
||||
|
||||
let mut states = vec![0.0_f32; total * STATE_DIM];
|
||||
let mut actions = vec![0_i32; total];
|
||||
let mut log_probs = vec![0.0_f32; total];
|
||||
let mut advantages = vec![0.0_f32; total];
|
||||
let mut returns = vec![0.0_f32; total];
|
||||
let mut done_flags = vec![0_i32; total];
|
||||
for (src_slice, count) in [
|
||||
(self.states_out.slice(..states_count), states_count),
|
||||
(self.log_probs_out.slice(..total), total),
|
||||
(self.advantages_out.slice(..total), total),
|
||||
(self.returns_out.slice(..total), total),
|
||||
] {
|
||||
let (src_ptr, _s) = src_slice.device_ptr(&self.stream);
|
||||
let nbytes = count * f32_size;
|
||||
unsafe {
|
||||
cudarc::driver::result::memcpy_dtod_async(
|
||||
dst_base + byte_offset as u64, src_ptr, nbytes, self.stream.cu_stream(),
|
||||
).map_err(|e| MLError::ModelError(format!("D2D f32 gather: {e}")))?;
|
||||
}
|
||||
byte_offset += nbytes;
|
||||
}
|
||||
}
|
||||
|
||||
// D2D gather i32 buffers into readback_i32_staging
|
||||
{
|
||||
let (dst_base, _dst_sync) = self.readback_i32_staging.device_ptr(&self.stream);
|
||||
let i32_size = std::mem::size_of::<i32>();
|
||||
let nbytes = total * i32_size;
|
||||
|
||||
let actions_slice = self.actions_out.slice(..total);
|
||||
let (src_a, _s0) = actions_slice.device_ptr(&self.stream);
|
||||
unsafe {
|
||||
cudarc::driver::result::memcpy_dtod_async(
|
||||
dst_base, src_a, nbytes, self.stream.cu_stream(),
|
||||
).map_err(|e| MLError::ModelError(format!("D2D i32 gather actions: {e}")))?;
|
||||
}
|
||||
let dones_slice = self.dones_out.slice(..total);
|
||||
let (src_d, _s1) = dones_slice.device_ptr(&self.stream);
|
||||
unsafe {
|
||||
cudarc::driver::result::memcpy_dtod_async(
|
||||
dst_base + nbytes as u64, src_d, nbytes, self.stream.cu_stream(),
|
||||
).map_err(|e| MLError::ModelError(format!("D2D i32 gather dones: {e}")))?;
|
||||
}
|
||||
}
|
||||
|
||||
// Single DtoH for f32
|
||||
let f32_view = self.readback_f32_staging.slice(..total_f32);
|
||||
let host_f32 = &mut self.readback_f32_host[..total_f32];
|
||||
self.stream
|
||||
.memcpy_dtoh(&states_view, &mut states)
|
||||
.map_err(|e| MLError::ModelError(format!("Download states failed: {e}")))?;
|
||||
.memcpy_dtoh(&f32_view, host_f32)
|
||||
.map_err(|e| MLError::ModelError(format!("DtoH f32: {e}")))?;
|
||||
|
||||
// Single DtoH for i32
|
||||
let i32_view = self.readback_i32_staging.slice(..total_i32);
|
||||
let host_i32 = &mut self.readback_i32_host[..total_i32];
|
||||
self.stream
|
||||
.memcpy_dtoh(&actions_view, &mut actions)
|
||||
.map_err(|e| MLError::ModelError(format!("Download actions failed: {e}")))?;
|
||||
self.stream
|
||||
.memcpy_dtoh(&log_probs_view, &mut log_probs)
|
||||
.map_err(|e| MLError::ModelError(format!("Download log_probs failed: {e}")))?;
|
||||
self.stream
|
||||
.memcpy_dtoh(&advantages_view, &mut advantages)
|
||||
.map_err(|e| MLError::ModelError(format!("Download advantages failed: {e}")))?;
|
||||
self.stream
|
||||
.memcpy_dtoh(&returns_view, &mut returns)
|
||||
.map_err(|e| MLError::ModelError(format!("Download returns failed: {e}")))?;
|
||||
self.stream
|
||||
.memcpy_dtoh(&dones_view, &mut done_flags)
|
||||
.map_err(|e| MLError::ModelError(format!("Download done_flags failed: {e}")))?;
|
||||
.memcpy_dtoh(&i32_view, host_i32)
|
||||
.map_err(|e| MLError::ModelError(format!("DtoH i32: {e}")))?;
|
||||
|
||||
// Slice host buffers
|
||||
let states = host_f32[..states_count].to_vec();
|
||||
let log_probs = host_f32[states_count..states_count + total].to_vec();
|
||||
let advantages = host_f32[states_count + total..states_count + 2 * total].to_vec();
|
||||
let returns = host_f32[states_count + 2 * total..states_count + 3 * total].to_vec();
|
||||
let actions = host_i32[..total].to_vec();
|
||||
let done_flags = host_i32[total..2 * total].to_vec();
|
||||
|
||||
debug!(
|
||||
n_episodes,
|
||||
timesteps,
|
||||
total_experiences = total,
|
||||
"PPO experience collection complete"
|
||||
"PPO experience collection complete (2 DtoH vs 6)"
|
||||
);
|
||||
|
||||
// ---- Step 7: Return batch ----
|
||||
|
||||
@@ -17,7 +17,7 @@ use std::sync::Arc;
|
||||
|
||||
use candle_core::cuda_backend::cudarc;
|
||||
use candle_core::Var;
|
||||
use cudarc::driver::{CudaSlice, CudaStream, DevicePtr, DeviceRepr};
|
||||
use cudarc::driver::{CudaSlice, CudaStream, DevicePtr, DeviceRepr, PushKernelArg};
|
||||
use candle_nn::VarMap;
|
||||
use tracing::info;
|
||||
|
||||
@@ -496,6 +496,304 @@ impl KernelWeightPack {
|
||||
}
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// BF16 Weight Mirror — parallel BF16 copies of all F32 weight buffers
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
/// BF16 mirror of a DuelingWeightSet. Stored as CudaSlice<u16> where each u16
|
||||
/// holds the bit pattern of an __nv_bfloat16 value.
|
||||
///
|
||||
/// Updated automatically after each F32 weight sync via the `f32_to_bf16_kernel`
|
||||
/// CUDA kernel. The training forward pass reads from these BF16 buffers;
|
||||
/// backward/Adam operate on the F32 originals.
|
||||
#[allow(missing_debug_implementations)]
|
||||
pub struct DuelingWeightSetBf16 {
|
||||
pub w_s1: CudaSlice<u16>,
|
||||
pub b_s1: CudaSlice<u16>,
|
||||
pub w_s2: CudaSlice<u16>,
|
||||
pub b_s2: CudaSlice<u16>,
|
||||
pub w_v1: CudaSlice<u16>,
|
||||
pub b_v1: CudaSlice<u16>,
|
||||
pub w_v2: CudaSlice<u16>,
|
||||
pub b_v2: CudaSlice<u16>,
|
||||
pub w_a1: CudaSlice<u16>,
|
||||
pub b_a1: CudaSlice<u16>,
|
||||
pub w_a2: CudaSlice<u16>,
|
||||
pub b_a2: CudaSlice<u16>,
|
||||
}
|
||||
|
||||
/// BF16 mirror of BranchingWeightSet (order + urgency heads).
|
||||
#[allow(missing_debug_implementations)]
|
||||
pub struct BranchingWeightSetBf16 {
|
||||
pub w_bo1: CudaSlice<u16>,
|
||||
pub b_bo1: CudaSlice<u16>,
|
||||
pub w_bo2: CudaSlice<u16>,
|
||||
pub b_bo2: CudaSlice<u16>,
|
||||
pub w_bu1: CudaSlice<u16>,
|
||||
pub b_bu1: CudaSlice<u16>,
|
||||
pub w_bu2: CudaSlice<u16>,
|
||||
pub b_bu2: CudaSlice<u16>,
|
||||
}
|
||||
|
||||
/// BF16 mirror of CuriosityWeightSet.
|
||||
#[allow(missing_debug_implementations)]
|
||||
pub struct CuriosityWeightSetBf16 {
|
||||
pub w1: CudaSlice<u16>,
|
||||
pub b1: CudaSlice<u16>,
|
||||
pub w2: CudaSlice<u16>,
|
||||
pub b2: CudaSlice<u16>,
|
||||
}
|
||||
|
||||
/// Allocate a BF16 buffer matching an F32 buffer's element count.
|
||||
fn alloc_bf16_mirror(
|
||||
f32_buf: &CudaSlice<f32>,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<CudaSlice<u16>, MLError> {
|
||||
let n = f32_buf.len();
|
||||
stream.alloc_zeros::<u16>(n).map_err(|e| {
|
||||
MLError::ModelError(format!("BF16 mirror alloc ({n} elems): {e}"))
|
||||
})
|
||||
}
|
||||
|
||||
/// Convert F32 buffer → BF16 buffer on GPU using a pre-compiled CUDA kernel.
|
||||
///
|
||||
/// Launches `f32_to_bf16_kernel` (defined in `common_device_functions.cuh`,
|
||||
/// compiled via NVRTC as part of the training kernel module).
|
||||
///
|
||||
/// `func`: pre-compiled `CudaFunction` for `f32_to_bf16_kernel`.
|
||||
pub fn convert_f32_to_bf16(
|
||||
src: &CudaSlice<f32>,
|
||||
dst: &mut CudaSlice<u16>,
|
||||
func: &cudarc::driver::CudaFunction,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
let n = src.len();
|
||||
if n == 0 { return Ok(()); }
|
||||
let block = 256u32;
|
||||
let grid = ((n as u32) + block - 1) / block;
|
||||
let cfg = cudarc::driver::LaunchConfig {
|
||||
grid_dim: (grid, 1, 1),
|
||||
block_dim: (block, 1, 1),
|
||||
shared_mem_bytes: 0,
|
||||
};
|
||||
unsafe {
|
||||
stream
|
||||
.launch_builder(func)
|
||||
.arg(src)
|
||||
.arg(dst)
|
||||
.arg(&(n as i32))
|
||||
.launch(cfg)
|
||||
.map_err(|e| MLError::ModelError(format!("f32_to_bf16 launch: {e}")))?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
impl DuelingWeightSetBf16 {
|
||||
/// Allocate BF16 mirrors matching an existing F32 weight set.
|
||||
pub fn alloc_from(f32_set: &DuelingWeightSet, stream: &Arc<CudaStream>) -> Result<Self, MLError> {
|
||||
Ok(Self {
|
||||
w_s1: alloc_bf16_mirror(&f32_set.w_s1, stream)?,
|
||||
b_s1: alloc_bf16_mirror(&f32_set.b_s1, stream)?,
|
||||
w_s2: alloc_bf16_mirror(&f32_set.w_s2, stream)?,
|
||||
b_s2: alloc_bf16_mirror(&f32_set.b_s2, stream)?,
|
||||
w_v1: alloc_bf16_mirror(&f32_set.w_v1, stream)?,
|
||||
b_v1: alloc_bf16_mirror(&f32_set.b_v1, stream)?,
|
||||
w_v2: alloc_bf16_mirror(&f32_set.w_v2, stream)?,
|
||||
b_v2: alloc_bf16_mirror(&f32_set.b_v2, stream)?,
|
||||
w_a1: alloc_bf16_mirror(&f32_set.w_a1, stream)?,
|
||||
b_a1: alloc_bf16_mirror(&f32_set.b_a1, stream)?,
|
||||
w_a2: alloc_bf16_mirror(&f32_set.w_a2, stream)?,
|
||||
b_a2: alloc_bf16_mirror(&f32_set.b_a2, stream)?,
|
||||
})
|
||||
}
|
||||
|
||||
/// Sync all 12 BF16 mirrors from F32 originals using GPU kernel.
|
||||
pub fn sync_from_f32(
|
||||
&mut self,
|
||||
f32_set: &DuelingWeightSet,
|
||||
func: &cudarc::driver::CudaFunction,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
convert_f32_to_bf16(&f32_set.w_s1, &mut self.w_s1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_s1, &mut self.b_s1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_s2, &mut self.w_s2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_s2, &mut self.b_s2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_v1, &mut self.w_v1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_v1, &mut self.b_v1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_v2, &mut self.w_v2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_v2, &mut self.b_v2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_a1, &mut self.w_a1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_a1, &mut self.b_a1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_a2, &mut self.w_a2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_a2, &mut self.b_a2, func, stream)?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl BranchingWeightSetBf16 {
|
||||
/// Allocate BF16 mirrors matching an existing F32 weight set.
|
||||
pub fn alloc_from(f32_set: &BranchingWeightSet, stream: &Arc<CudaStream>) -> Result<Self, MLError> {
|
||||
Ok(Self {
|
||||
w_bo1: alloc_bf16_mirror(&f32_set.w_bo1, stream)?,
|
||||
b_bo1: alloc_bf16_mirror(&f32_set.b_bo1, stream)?,
|
||||
w_bo2: alloc_bf16_mirror(&f32_set.w_bo2, stream)?,
|
||||
b_bo2: alloc_bf16_mirror(&f32_set.b_bo2, stream)?,
|
||||
w_bu1: alloc_bf16_mirror(&f32_set.w_bu1, stream)?,
|
||||
b_bu1: alloc_bf16_mirror(&f32_set.b_bu1, stream)?,
|
||||
w_bu2: alloc_bf16_mirror(&f32_set.w_bu2, stream)?,
|
||||
b_bu2: alloc_bf16_mirror(&f32_set.b_bu2, stream)?,
|
||||
})
|
||||
}
|
||||
|
||||
/// Sync all 8 BF16 mirrors from F32 originals.
|
||||
pub fn sync_from_f32(
|
||||
&mut self,
|
||||
f32_set: &BranchingWeightSet,
|
||||
func: &cudarc::driver::CudaFunction,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
convert_f32_to_bf16(&f32_set.w_bo1, &mut self.w_bo1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_bo1, &mut self.b_bo1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_bo2, &mut self.w_bo2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_bo2, &mut self.b_bo2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_bu1, &mut self.w_bu1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_bu1, &mut self.b_bu1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w_bu2, &mut self.w_bu2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b_bu2, &mut self.b_bu2, func, stream)?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl CuriosityWeightSetBf16 {
|
||||
/// Allocate BF16 mirrors matching an existing F32 weight set.
|
||||
pub fn alloc_from(f32_set: &CuriosityWeightSet, stream: &Arc<CudaStream>) -> Result<Self, MLError> {
|
||||
Ok(Self {
|
||||
w1: alloc_bf16_mirror(&f32_set.w1, stream)?,
|
||||
b1: alloc_bf16_mirror(&f32_set.b1, stream)?,
|
||||
w2: alloc_bf16_mirror(&f32_set.w2, stream)?,
|
||||
b2: alloc_bf16_mirror(&f32_set.b2, stream)?,
|
||||
})
|
||||
}
|
||||
|
||||
/// Sync all 4 BF16 mirrors from F32 originals.
|
||||
pub fn sync_from_f32(
|
||||
&mut self,
|
||||
f32_set: &CuriosityWeightSet,
|
||||
func: &cudarc::driver::CudaFunction,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
convert_f32_to_bf16(&f32_set.w1, &mut self.w1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b1, &mut self.b1, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.w2, &mut self.w2, func, stream)?;
|
||||
convert_f32_to_bf16(&f32_set.b2, &mut self.b2, func, stream)?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Extract raw CUDA device pointer from a BF16 CudaSlice (u16 bit pattern).
|
||||
fn raw_device_ptr_bf16(slice: &CudaSlice<u16>, stream: &CudaStream) -> u64 {
|
||||
let (ptr, guard) = slice.device_ptr(stream);
|
||||
let _no_drop = std::mem::ManuallyDrop::new(guard);
|
||||
ptr
|
||||
}
|
||||
|
||||
/// BF16 device pointer pack for the forward pass.
|
||||
///
|
||||
/// Same layout as `KernelWeightPack` but pointing to BF16 buffers.
|
||||
/// The CUDA forward kernel reads these for BF16 matmul;
|
||||
/// backward/Adam kernel still reads the F32 `KernelWeightPack`.
|
||||
#[repr(C)]
|
||||
#[derive(Clone, Copy)]
|
||||
pub(super) struct KernelWeightPackBf16 {
|
||||
pub online: GpuDuelingPtrs,
|
||||
pub target: GpuDuelingPtrs,
|
||||
pub curiosity: GpuCuriosityPtrs,
|
||||
pub rmsnorm: GpuRMSNormPtrs, // RMSNorm stays F32 (gamma scaling)
|
||||
pub online_br: GpuBranchPtrs,
|
||||
pub target_br: GpuBranchPtrs,
|
||||
}
|
||||
|
||||
#[allow(unsafe_code)]
|
||||
unsafe impl DeviceRepr for KernelWeightPackBf16 {}
|
||||
|
||||
impl KernelWeightPackBf16 {
|
||||
/// Build BF16 weight pointer pack for forward pass.
|
||||
///
|
||||
/// Weight matrices use BF16 pointers; RMSNorm gammas stay F32.
|
||||
pub(super) fn build(
|
||||
online_bf16: &DuelingWeightSetBf16,
|
||||
target_bf16: &DuelingWeightSetBf16,
|
||||
curiosity_bf16: &CuriosityWeightSetBf16,
|
||||
rmsnorm_f32: &RmsNormWeightSet,
|
||||
online_br_bf16: &BranchingWeightSetBf16,
|
||||
target_br_bf16: &BranchingWeightSetBf16,
|
||||
stream: &CudaStream,
|
||||
) -> Self {
|
||||
Self {
|
||||
online: GpuDuelingPtrs {
|
||||
w_s1: raw_device_ptr_bf16(&online_bf16.w_s1, stream),
|
||||
b_s1: raw_device_ptr_bf16(&online_bf16.b_s1, stream),
|
||||
w_s2: raw_device_ptr_bf16(&online_bf16.w_s2, stream),
|
||||
b_s2: raw_device_ptr_bf16(&online_bf16.b_s2, stream),
|
||||
w_v1: raw_device_ptr_bf16(&online_bf16.w_v1, stream),
|
||||
b_v1: raw_device_ptr_bf16(&online_bf16.b_v1, stream),
|
||||
w_v2: raw_device_ptr_bf16(&online_bf16.w_v2, stream),
|
||||
b_v2: raw_device_ptr_bf16(&online_bf16.b_v2, stream),
|
||||
w_a1: raw_device_ptr_bf16(&online_bf16.w_a1, stream),
|
||||
b_a1: raw_device_ptr_bf16(&online_bf16.b_a1, stream),
|
||||
w_a2: raw_device_ptr_bf16(&online_bf16.w_a2, stream),
|
||||
b_a2: raw_device_ptr_bf16(&online_bf16.b_a2, stream),
|
||||
},
|
||||
target: GpuDuelingPtrs {
|
||||
w_s1: raw_device_ptr_bf16(&target_bf16.w_s1, stream),
|
||||
b_s1: raw_device_ptr_bf16(&target_bf16.b_s1, stream),
|
||||
w_s2: raw_device_ptr_bf16(&target_bf16.w_s2, stream),
|
||||
b_s2: raw_device_ptr_bf16(&target_bf16.b_s2, stream),
|
||||
w_v1: raw_device_ptr_bf16(&target_bf16.w_v1, stream),
|
||||
b_v1: raw_device_ptr_bf16(&target_bf16.b_v1, stream),
|
||||
w_v2: raw_device_ptr_bf16(&target_bf16.w_v2, stream),
|
||||
b_v2: raw_device_ptr_bf16(&target_bf16.b_v2, stream),
|
||||
w_a1: raw_device_ptr_bf16(&target_bf16.w_a1, stream),
|
||||
b_a1: raw_device_ptr_bf16(&target_bf16.b_a1, stream),
|
||||
w_a2: raw_device_ptr_bf16(&target_bf16.w_a2, stream),
|
||||
b_a2: raw_device_ptr_bf16(&target_bf16.b_a2, stream),
|
||||
},
|
||||
curiosity: GpuCuriosityPtrs {
|
||||
w1: raw_device_ptr_bf16(&curiosity_bf16.w1, stream),
|
||||
b1: raw_device_ptr_bf16(&curiosity_bf16.b1, stream),
|
||||
w2: raw_device_ptr_bf16(&curiosity_bf16.w2, stream),
|
||||
b2: raw_device_ptr_bf16(&curiosity_bf16.b2, stream),
|
||||
},
|
||||
rmsnorm: GpuRMSNormPtrs {
|
||||
s0: raw_device_ptr(&rmsnorm_f32.gamma_s0, stream),
|
||||
s1: raw_device_ptr(&rmsnorm_f32.gamma_s1, stream),
|
||||
v: raw_device_ptr(&rmsnorm_f32.gamma_v, stream),
|
||||
a: raw_device_ptr(&rmsnorm_f32.gamma_a, stream),
|
||||
},
|
||||
online_br: GpuBranchPtrs {
|
||||
w_o1: raw_device_ptr_bf16(&online_br_bf16.w_bo1, stream),
|
||||
b_o1: raw_device_ptr_bf16(&online_br_bf16.b_bo1, stream),
|
||||
w_o2: raw_device_ptr_bf16(&online_br_bf16.w_bo2, stream),
|
||||
b_o2: raw_device_ptr_bf16(&online_br_bf16.b_bo2, stream),
|
||||
w_u1: raw_device_ptr_bf16(&online_br_bf16.w_bu1, stream),
|
||||
b_u1: raw_device_ptr_bf16(&online_br_bf16.b_bu1, stream),
|
||||
w_u2: raw_device_ptr_bf16(&online_br_bf16.w_bu2, stream),
|
||||
b_u2: raw_device_ptr_bf16(&online_br_bf16.b_bu2, stream),
|
||||
},
|
||||
target_br: GpuBranchPtrs {
|
||||
w_o1: raw_device_ptr_bf16(&target_br_bf16.w_bo1, stream),
|
||||
b_o1: raw_device_ptr_bf16(&target_br_bf16.b_bo1, stream),
|
||||
w_o2: raw_device_ptr_bf16(&target_br_bf16.w_bo2, stream),
|
||||
b_o2: raw_device_ptr_bf16(&target_br_bf16.b_bo2, stream),
|
||||
w_u1: raw_device_ptr_bf16(&target_br_bf16.w_bu1, stream),
|
||||
b_u1: raw_device_ptr_bf16(&target_br_bf16.b_bu1, stream),
|
||||
w_u2: raw_device_ptr_bf16(&target_br_bf16.w_bu2, stream),
|
||||
b_u2: raw_device_ptr_bf16(&target_br_bf16.b_bu2, stream),
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Extraction helpers
|
||||
// ---------------------------------------------------------------------------
|
||||
@@ -890,6 +1188,118 @@ pub fn sync_branching_weights(
|
||||
Ok(())
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Reverse sync: CudaSlice → VarMap (write back GPU-updated weights)
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
/// Write a single CudaSlice back to the corresponding VarMap tensor.
|
||||
///
|
||||
/// Uses device-to-device copy (zero CPU roundtrip): our CudaSlice → Candle Var's
|
||||
/// internal CUDA storage. The Candle Var's device pointer stays unchanged.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// Writes directly to the Candle Var's backing CUDA memory. The caller must
|
||||
/// ensure no concurrent reads from the same Var during this call.
|
||||
fn reverse_sync_one(
|
||||
vars_data: &std::collections::HashMap<String, Var>,
|
||||
name: &str,
|
||||
src: &CudaSlice<f32>,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
let tensor = vars_data
|
||||
.get(name)
|
||||
.ok_or_else(|| MLError::ModelError(format!("Missing weight: {name}")))?
|
||||
.as_tensor();
|
||||
let flat_tensor = tensor
|
||||
.flatten_all()
|
||||
.map_err(|e| MLError::ModelError(format!("Flatten {name}: {e}")))?
|
||||
.to_dtype(candle_core::DType::F32)
|
||||
.map_err(|e| MLError::ModelError(format!("Cast {name} to F32: {e}")))?
|
||||
.contiguous()
|
||||
.map_err(|e| MLError::ModelError(format!("Contiguous {name}: {e}")))?;
|
||||
let n_elems = flat_tensor.elem_count();
|
||||
|
||||
if src.len() != n_elems {
|
||||
return Err(MLError::ModelError(format!(
|
||||
"reverse_sync {name}: CudaSlice len {} != Var tensor elems {n_elems}",
|
||||
src.len()
|
||||
)));
|
||||
}
|
||||
|
||||
let (storage_guard, _layout) = flat_tensor.storage_and_layout();
|
||||
match *storage_guard {
|
||||
candle_core::Storage::Cuda(ref cs) => {
|
||||
let dst_slice: &CudaSlice<f32> = cs.as_cuda_slice()
|
||||
.map_err(|e| MLError::ModelError(format!("as_cuda_slice {name}: {e}")))?;
|
||||
let (dst_ptr, _dst_sync) = dst_slice.device_ptr(stream);
|
||||
let (src_ptr, _src_sync) = src.device_ptr(stream);
|
||||
let num_bytes = n_elems * std::mem::size_of::<f32>();
|
||||
dtod_copy_checked(dst_ptr, src_ptr, num_bytes, stream, name, "reverse_sync")?;
|
||||
}
|
||||
candle_core::Storage::Cpu(_) | candle_core::Storage::Metal(_) => {
|
||||
return Err(MLError::ModelError(format!(
|
||||
"Weight tensor '{name}' is not on CUDA — reverse sync requires CUDA tensors"
|
||||
)));
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Write back all 12 branching-dueling weight tensors from CudaSlice to VarMap.
|
||||
///
|
||||
/// Reverse of `sync_dueling_weights_branching`: copies GPU-updated weights
|
||||
/// from the fused training kernel's CudaSlice buffers back to Candle's VarMap
|
||||
/// so that Polyak target updates can read current online weights.
|
||||
pub fn reverse_sync_dueling_weights_branching(
|
||||
vars: &VarMap,
|
||||
weights: &DuelingWeightSet,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
let vars_data = vars.data().lock().map_err(|e| {
|
||||
MLError::ModelError(format!("Failed to lock VarMap: {e}"))
|
||||
})?;
|
||||
|
||||
reverse_sync_one(&vars_data, "shared_0.weight", &weights.w_s1, stream)?;
|
||||
reverse_sync_one(&vars_data, "shared_0.bias", &weights.b_s1, stream)?;
|
||||
reverse_sync_one(&vars_data, "shared_1.weight", &weights.w_s2, stream)?;
|
||||
reverse_sync_one(&vars_data, "shared_1.bias", &weights.b_s2, stream)?;
|
||||
reverse_sync_one(&vars_data, "value_fc.weight", &weights.w_v1, stream)?;
|
||||
reverse_sync_one(&vars_data, "value_fc.bias", &weights.b_v1, stream)?;
|
||||
reverse_sync_one(&vars_data, "value_out.weight", &weights.w_v2, stream)?;
|
||||
reverse_sync_one(&vars_data, "value_out.bias", &weights.b_v2, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_0_fc.weight", &weights.w_a1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_0_fc.bias", &weights.b_a1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_0_out.weight", &weights.w_a2, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_0_out.bias", &weights.b_a2, stream)?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Write back all 8 branching weight tensors (branches 1+2) from CudaSlice to VarMap.
|
||||
///
|
||||
/// Reverse of `sync_branching_weights`.
|
||||
pub fn reverse_sync_branching_weights(
|
||||
vars: &VarMap,
|
||||
weights: &BranchingWeightSet,
|
||||
stream: &Arc<CudaStream>,
|
||||
) -> Result<(), MLError> {
|
||||
let vars_data = vars.data().lock().map_err(|e| {
|
||||
MLError::ModelError(format!("Failed to lock VarMap: {e}"))
|
||||
})?;
|
||||
|
||||
reverse_sync_one(&vars_data, "branch_1_fc.weight", &weights.w_bo1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_1_fc.bias", &weights.b_bo1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_1_out.weight", &weights.w_bo2, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_1_out.bias", &weights.b_bo2, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_2_fc.weight", &weights.w_bu1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_2_fc.bias", &weights.b_bu1, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_2_out.weight", &weights.w_bu2, stream)?;
|
||||
reverse_sync_one(&vars_data, "branch_2_out.bias", &weights.b_bu2, stream)?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Extract RMSNorm gamma weights from a distributional dueling `VarMap`.
|
||||
///
|
||||
/// Looks for keys: `shared_rmsnorm_0.weight`, `shared_rmsnorm_1.weight`,
|
||||
|
||||
Reference in New Issue
Block a user