plan5(task5-F): compile-time fxcache schema fingerprint via build.rs
Closes the L40S deploy-bug class where stale fxcache passed FXCACHE_VERSION validation despite incompatible feature semantics. Root cause of the original failure: extract_ohlcv_features column 0 changed from raw price -> log-return without anyone bumping the manually-maintained FXCACHE_VERSION const, so the L40S PVC's older cache loaded clean and the trainer fed raw prices into the aux head expecting log-returns (aux_next_bar_mse=2.587e7). Fix: * crates/ml/build.rs::emit_feature_schema_hash() runs unconditionally (before the existing CUDA-feature gate so non-CUDA builds also pick up the env var) and FNV-1a-hashes the raw bytes of the three schema-defining sources -- crates/ml/src/features/extraction.rs, crates/ml/src/fxcache.rs, crates/ml-core/src/state_layout.rs -- mixing in each file's relative path + length so renames / reorderings also bump the hash. Stable across rust versions and machines (FNV-1a, not std::hash::DefaultHasher). Emits cargo:rustc-env=FEATURE_SCHEMA_HASH=<decimal_u64> + three cargo:rerun-if-changed= lines. * crates/ml/src/fxcache.rs::FEATURE_SCHEMA_HASH consumes the env var via env! + const u64::from_str_radix(_, 10) (const-stable since rust 1.83; workspace MSRV 1.85). FxCacheHeader grows a feature_schema_hash: u64 field; header size 64->72 bytes; FXCACHE_VERSION bumped 5->6 to flag the wire-format change. validate() strict-checks the hash alongside magic / version / dims; mismatch bails with a descriptive error pointing at "source files defining feature extraction / state layout / fxcache format have changed since this cache was built." The existing precompute_features.rs:218 delete-and-regen-on-Err path handles recovery automatically; the Argo ensure-fxcache step is unchanged. * FXCACHE_VERSION docstring now declares it tracks WIRE-FORMAT changes only -- schema-level changes (feature column semantics, dimensionality) are tracked automatically by FEATURE_SCHEMA_HASH. Removes the manual ritual that broke the L40S deploy. * docs/dqn-wire-up-audit.md entry under Plan 5 Task 5 Phase F. Cost: cosmetic edits (whitespace, comments) to the three schema sources trigger one cache regen on next deploy (~5 min for full L40S dataset, ~40 s for local ES.FUT). Acceptable trade -- false negatives (missed schema drift) are not. Validation: * cargo check workspace clean at 11 warnings (baseline preserved). * Local ES.FUT cache regen confirmed: existing v5 file rejected with "Stale FxCache version: 5 (expected 6). Delete and regenerate.", regenerated v6 cache loads clean on retry (40 s, 175874 bars). * Auto-detection verified: comment-only edit to extraction.rs line 1 changed emitted hash 5046469432341222878 -> 7772630163018944575; revert returned the hash deterministically to 5046469432341222878. * multi_fold_convergence smoke PASSED (1 passed, 0 failed; 689.24 s, ~11.5 min). All 3 folds produced best-checkpoints. Per-fold best Sharpe: F0=-9.7831 (epoch 1), F1=37.9597 (epoch 2), F2=40.4789 (epoch 5). aux next_bar_mse range across all 15 epochs: 6.097e-2 -- 4.722e-1 (O(0.1), not 1e7 as in the L40S regression). No new pip/cargo deps (FNV-1a is ~10 LOC stdlib). No fingerprint change (LAYOUT_FINGERPRINT_CURRENT untouched -- this is fxcache wire-format, not GPU param layout). Files touched: * crates/ml/build.rs * crates/ml/src/fxcache.rs * docs/dqn-wire-up-audit.md Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
jgrusewski
@@ -4,6 +4,20 @@ use std::process::Command;
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fn main() {
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println!("cargo:rerun-if-changed=build.rs");
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// ── Feature schema fingerprint ────────────────────────────────────────────
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// Stamped into every fxcache file so caches built against a different
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// feature-extractor / state-layout / fxcache-format version fail
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// header-validation at load time and trigger automatic regeneration via
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// the Argo `ensure-fxcache` step. Removes the manual "remember to bump
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// FXCACHE_VERSION on schema change" ritual that broke the L40S deploy.
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//
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// Hashing strategy: FNV-1a 64-bit over the raw bytes of these source
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// files. Stable across rust versions and machines (unlike
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// `std::hash::DefaultHasher`). Cost: harmless cosmetic edits to these
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// files (whitespace / comments) trigger one cache regen on next deploy
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// (~5min). That cost is acceptable; missed schema drift is not.
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emit_feature_schema_hash();
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// Only compile CUDA kernels when the cuda feature is enabled
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if std::env::var("CARGO_FEATURE_CUDA").is_err() {
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return;
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@@ -249,6 +263,55 @@ fn try_compile_kernel(
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}
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}
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/// Compute and emit the feature-schema fingerprint as `FEATURE_SCHEMA_HASH`
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/// (decimal u64 string) so `fxcache.rs` can pick it up via `env!`.
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///
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/// Hashes the raw bytes of every source file that defines the on-disk fxcache
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/// schema. Any edit (including whitespace / comments) bumps the hash. The
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/// fxcache header records this value at write time; `validate()` rejects
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/// caches whose recorded hash mismatches the compiled-in const, and
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/// `precompute_features` regenerates them.
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fn emit_feature_schema_hash() {
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// Source files whose bytes determine the on-disk schema.
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// Touching ANY of these files implies "fxcache regen on next deploy".
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let schema_sources: &[&str] = &[
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"src/features/extraction.rs",
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"src/fxcache.rs",
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"../ml-core/src/state_layout.rs",
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];
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// FNV-1a 64-bit init constants (RFC-style).
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const FNV_OFFSET: u64 = 0xcbf2_9ce4_8422_2325;
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const FNV_PRIME: u64 = 0x0000_0100_0000_01b3;
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let mut hash: u64 = FNV_OFFSET;
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for rel in schema_sources {
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let path = PathBuf::from(rel);
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let bytes = std::fs::read(&path)
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.unwrap_or_else(|e| panic!("Failed to read schema source {}: {e}", path.display()));
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// Mix file path bytes too so reordering / renaming bumps the hash even
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// if the bytes happen to match.
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for b in rel.as_bytes() {
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hash ^= *b as u64;
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hash = hash.wrapping_mul(FNV_PRIME);
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}
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// Length separator so concatenation boundaries can't collide.
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for b in (bytes.len() as u64).to_le_bytes() {
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hash ^= b as u64;
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hash = hash.wrapping_mul(FNV_PRIME);
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}
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for b in &bytes {
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hash ^= *b as u64;
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hash = hash.wrapping_mul(FNV_PRIME);
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}
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println!("cargo:rerun-if-changed={}", path.display());
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}
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// Decimal so the consumer can use the const-stable `u64::from_str_radix`
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// with radix 10 without any hex-prefix stripping.
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println!("cargo:rustc-env=FEATURE_SCHEMA_HASH={hash}");
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}
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/// Find nvcc: prefer $CUDA_HOME/bin/nvcc, then check PATH
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fn find_nvcc() -> Option<PathBuf> {
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// Try $CUDA_HOME/bin/nvcc first
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@@ -7,21 +7,22 @@
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//! ## Format
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//!
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//! ```text
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//! ┌───────────────────────────────────────────────────┐
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//! │ FxCacheHeader (64 bytes) │
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//! │ magic [u8; 8] = b"FXCACHE\0" │
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//! │ version u16 = 5 (f32) │
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//! │ feat_dim u16 = 42 │
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//! │ target_dim u16 = 6 │
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//! │ ofi_dim u16 = 32 │
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//! │ bar_count u64 │
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//! │ cache_key [u8; 32] (SHA256 raw bytes) │
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//! │ reserved [u8; 8] │
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//! └───────────────────────────────────────────────────┘
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//! │ Body (bar_count records) │
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//! │ Each record starts with an i64 timestamp (ns). │
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//! │ Version 5: [i64 ts][80 × f32] = 328 bytes/bar │
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//! └───────────────────────────────────────────────────┘
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//! ┌─────────────────────────────────────────────────────────────┐
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//! │ FxCacheHeader (72 bytes) │
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//! │ magic [u8; 8] = b"FXCACHE\0" │
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//! │ version u16 = 6 (f32 + schema-hash) │
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//! │ feat_dim u16 = 42 │
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//! │ target_dim u16 = 6 │
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//! │ ofi_dim u16 = 32 │
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//! │ bar_count u64 │
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//! │ cache_key [u8; 32] (SHA256 raw bytes) │
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//! │ feature_schema_hash u64 (FNV-1a from build.rs) │
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//! │ reserved [u8; 8] │
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//! └─────────────────────────────────────────────────────────────┘
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//! │ Body (bar_count records) │
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//! │ Each record starts with an i64 timestamp (ns). │
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//! │ Version 6: [i64 ts][80 × f32] = 328 bytes/bar │
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//! └─────────────────────────────────────────────────────────────┘
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//! ```
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use anyhow::{bail, Context, Result};
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@@ -35,17 +36,47 @@ use tracing::{debug, info};
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const FXCACHE_MAGIC: [u8; 8] = *b"FXCACHE\0";
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/// Header size in bytes (fixed).
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const HEADER_SIZE: usize = 64;
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const HEADER_SIZE: usize = 72;
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/// Cache format version. Bump on ANY format change (OFI_DIM, FEAT_DIM, etc.).
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/// Stale cache files with wrong version are auto-detected and rejected by validate().
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/// The ensure-fxcache Argo step catches the error and regenerates.
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/// Cache format version. Bump on ANY *wire-format* change (header layout,
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/// body record shape). Schema-level changes (feature column semantics,
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/// dimensionality) are tracked automatically by `FEATURE_SCHEMA_HASH` —
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/// callers do NOT need to bump this constant when they edit
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/// `features/extraction.rs` or `ml-core::state_layout`.
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/// Stale cache files with wrong version OR wrong schema hash are
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/// auto-detected and rejected by `validate()`. The ensure-fxcache Argo step
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/// catches the error and regenerates.
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/// v5: OFI_DIM 20→32 — adds 10 MicrostructureState slots (ofi_trajectory,
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/// realized_variance, hawkes_intensity, book_pressure, spread_dynamics,
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/// aggression_ratio, queue_depletion_asymmetry, order_count_flux,
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/// intra_bar_momentum, regime_score) + 2 TLOB-novel slots
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/// (order_count_imbalance, microprice_residual).
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pub const FXCACHE_VERSION: u16 = 5;
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/// v6: header grows 64→72 bytes, adds `feature_schema_hash: u64` between
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/// `cache_key` and `reserved`. Stamped at write time from the
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/// compile-time `FEATURE_SCHEMA_HASH` const (built from the bytes of
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/// extraction.rs / fxcache.rs / state_layout.rs by `build.rs`).
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/// Recover-from-stale path is identical: validate() bails, Argo regens.
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pub const FXCACHE_VERSION: u16 = 6;
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/// Compile-time fingerprint over the feature-schema source files. Bumps
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/// automatically whenever `features/extraction.rs`, `fxcache.rs`, or
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/// `ml-core::state_layout` change (any byte — whitespace counts).
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///
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/// Encoded into the fxcache header at write time and strict-checked at load
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/// time, so caches built against a different schema fail validation and
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/// trigger automatic regeneration via `precompute_features`. This removes
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/// the manual "remember to bump `FXCACHE_VERSION` on schema change" ritual.
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///
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/// The actual value is set by `build.rs` (FNV-1a 64-bit). Stable across
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/// rust versions and machines (unlike `std::hash::DefaultHasher`).
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pub const FEATURE_SCHEMA_HASH: u64 = {
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// build.rs emits the hash as a decimal u64 string; `from_str_radix` is
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// const since rust 1.83 and the workspace MSRV is 1.85.
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match u64::from_str_radix(env!("FEATURE_SCHEMA_HASH"), 10) {
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Ok(v) => v,
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Err(_) => panic!("build.rs emitted invalid u64 for FEATURE_SCHEMA_HASH"),
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}
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};
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/// Feature vector dimensionality.
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const FEAT_DIM: usize = 42;
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@@ -65,7 +96,7 @@ const RECORD_F32_COUNT: usize = RECORD_F64_COUNT;
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// ── Header ───────────────────────────────────────────────────────────────────
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/// 64-byte fixed header for `.fxcache` files.
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/// 72-byte fixed header for `.fxcache` files (v6+).
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#[derive(Debug, Clone)]
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pub struct FxCacheHeader {
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/// Magic bytes: `b"FXCACHE\0"`.
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@@ -82,6 +113,11 @@ pub struct FxCacheHeader {
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pub bar_count: u64,
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/// SHA256 cache key (raw 32 bytes).
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pub cache_key: [u8; 32],
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/// Compile-time feature-schema fingerprint — see `FEATURE_SCHEMA_HASH`.
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/// Mismatch on load means the cache was built against different feature
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/// extraction / state-layout / fxcache-format source than the current
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/// binary. Strict-checked in `validate()`; regen via `precompute_features`.
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pub feature_schema_hash: u64,
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/// Reserved for future use.
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pub reserved: [u8; 8],
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}
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@@ -99,15 +135,18 @@ impl FxCacheHeader {
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ofi_dim: OFI_DIM as u16,
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bar_count,
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cache_key,
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feature_schema_hash: FEATURE_SCHEMA_HASH,
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reserved,
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}
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}
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/// Validate header integrity.
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///
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/// Strictly enforces the current `FXCACHE_VERSION`. Any older version
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/// (including v4 with OFI_DIM=20) is rejected — regenerate via
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/// `precompute_features`.
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/// Strictly enforces the current `FXCACHE_VERSION` AND the current
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/// `FEATURE_SCHEMA_HASH`. Any older version (including v4 with
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/// OFI_DIM=20, v5 without schema-hash) or any cache built against a
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/// different feature-extractor / state-layout source is rejected —
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/// regenerate via `precompute_features`.
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pub fn validate(&self) -> Result<()> {
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if self.magic != FXCACHE_MAGIC {
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bail!(
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@@ -144,13 +183,22 @@ impl FxCacheHeader {
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self.ofi_dim
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);
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}
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if self.feature_schema_hash != FEATURE_SCHEMA_HASH {
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bail!(
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"Stale FxCache feature schema: hash {:#018x} (expected {:#018x}). \
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Source files defining feature extraction / state layout / \
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fxcache format have changed since this cache was built. \
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Delete and regenerate via precompute_features.",
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self.feature_schema_hash, FEATURE_SCHEMA_HASH
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);
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}
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if self.bar_count == 0 {
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bail!("FxCache bar_count is zero — empty cache files are not valid");
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}
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Ok(())
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}
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/// Serialize header to 64 bytes (little-endian).
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/// Serialize header to 72 bytes (little-endian).
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fn to_bytes(&self) -> [u8; HEADER_SIZE] {
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let mut buf = [0u8; HEADER_SIZE];
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buf[0..8].copy_from_slice(&self.magic);
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@@ -160,11 +208,12 @@ impl FxCacheHeader {
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buf[14..16].copy_from_slice(&self.ofi_dim.to_le_bytes());
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buf[16..24].copy_from_slice(&self.bar_count.to_le_bytes());
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buf[24..56].copy_from_slice(&self.cache_key);
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buf[56..64].copy_from_slice(&self.reserved);
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buf[56..64].copy_from_slice(&self.feature_schema_hash.to_le_bytes());
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buf[64..72].copy_from_slice(&self.reserved);
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buf
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}
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/// Deserialize header from 64 bytes (little-endian).
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/// Deserialize header from 72 bytes (little-endian).
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fn from_bytes(buf: &[u8; HEADER_SIZE]) -> Self {
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let mut magic = [0u8; 8];
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magic.copy_from_slice(&buf[0..8]);
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@@ -180,8 +229,12 @@ impl FxCacheHeader {
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let mut cache_key = [0u8; 32];
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cache_key.copy_from_slice(&buf[24..56]);
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let feature_schema_hash = u64::from_le_bytes([
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buf[56], buf[57], buf[58], buf[59], buf[60], buf[61], buf[62], buf[63],
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]);
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let mut reserved = [0u8; 8];
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reserved.copy_from_slice(&buf[56..64]);
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reserved.copy_from_slice(&buf[64..72]);
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Self {
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magic,
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@@ -191,6 +244,7 @@ impl FxCacheHeader {
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ofi_dim,
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bar_count,
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cache_key,
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feature_schema_hash,
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reserved,
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}
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}
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@@ -326,7 +380,7 @@ fn write_body_f32(
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/// Load an `.fxcache` file into memory.
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///
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/// Reads the 64-byte header, validates it, then reads the f32 body,
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/// Reads the 72-byte header, validates it, then reads the f32 body,
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/// converting each f32 back to f64 on load.
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///
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/// # Arguments
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@@ -340,6 +340,8 @@ Plan 4 Task 2c.3c.4 (2026-04-25): GRN backward chain wired through all 3 panic-g
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Plan 4 Task 2c.3a (2026-04-24): GRN trunk param-tensor reshuffle (build-clean, runtime-broken intentionally). `compute_param_sizes()` flat layout reshuffled from 86 → 95 tensors: the 4 legacy trunk Linear tensors (`w_s1`, `b_s1`, `w_s2`, `b_s2` at indices [0..4)) are replaced with **13 GRN tensors** at indices [0..13) — 7 for h_s1 GRN block (`w_a`, `b_a`, `w_b`, `b_b`, `w_residual`, `gamma`, `beta`; SD→SH1 with `Linear_residual` GEMM since dimensions differ) plus 6 for h_s2 GRN block (`w_a`, `b_a`, `w_b`, `b_b`, `gamma`, `beta`; SH1→SH2 with identity residual since SH1==SH2). Every tensor index ≥ 4 in the OLD layout shifts +9 in the NEW layout. `NUM_WEIGHT_TENSORS` 86→95, `FIRST_ISV_TENSOR` 68→77. `layout_fingerprint_seed()` updated to mirror the new tensor names + positions; new `LAYOUT_FINGERPRINT_CURRENT = 0xcf3a24b0a1f70057` (was `0xa504d3c2f275b8af`). All 93 `padded_byte_offset` call sites + ancillary index references migrated in lockstep per `feedback_no_partial_refactor.md`. `xavier_init_params_buf` extended with init paths for the 13 new tensors: Linear matrices (`w_a`, `w_b`, `w_residual`) get Xavier; LayerNorm γ initialised to 1.0; β + biases stay zero. Trunk-forward / trunk-backward / IQN-trunk / ensemble-diversity-backward callers gated by explicit `panic!("Plan 4 Task 2c.3a: trunk param layout migrated to GRN, …")` at function entry — `BatchedForward::encoder_forward_only`, `BatchedForward::forward_target_raw`, `BatchedForward::forward_online_f32`, `BatchedBackward::backward_full`, `GpuDqnTrainer::apply_iqn_trunk_gradient`, `GpuDqnTrainer::apply_ensemble_diversity_backward`. This makes accidental runtime execution fail loudly rather than producing silent garbage from running legacy `Linear→ReLU→Linear` GEMMs against GRN-shaped param tensors. Spectral-norm descriptor (13 matrices) keeps slots [0]/[1] mapped to `w_a_h_s1`/`w_a_h_s2` (shapes match legacy W_s1/W_s2 exactly — the GRN's first Linear has the same shape as the original Linear), so the existing spectral-norm constraint transfers cleanly to the GRN's first Linear; Linear_b / Linear_residual are NOT yet spectral-normed (Task 2c.3c follow-up). **Smoke intentionally NOT run** — build-clean is the validation; runtime would hit the panic at the first encoder forward (the desired behaviour, no need to verify explicitly). Task 2c.3b swaps in the GRN forward (gpu_grn::GrnBlock::forward) at all panic-gated forward callers in place; Task 2c.3c does the same for backward callers and runs the smoke test. cargo check clean at 11 warnings (baseline preserved); cargo build compiles all 58 cubins. No new module / kernel / ISV slot in this commit — pure structural reshuffle + assertion gates.
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Plan 5 Task 5 Phase F (2026-04-26): **compile-time fxcache schema fingerprint** — closes the L40S deploy-bug class where stale fxcache passed `FXCACHE_VERSION` validation despite incompatible feature semantics. Root cause of the original failure: `extract_ohlcv_features` column 0 changed from raw price → log-return without anyone bumping the manually-maintained `FXCACHE_VERSION` const, so the L40S PVC's older cache loaded clean and the trainer fed raw prices into the aux head expecting log-returns (`aux_next_bar_mse=2.587e7`). Fix has three pieces: (1) `crates/ml/build.rs::emit_feature_schema_hash()` runs unconditionally (before the existing CUDA-feature gate so non-CUDA builds also get the env var) and FNV-1a-hashes the raw bytes of the three schema-defining sources — `crates/ml/src/features/extraction.rs`, `crates/ml/src/fxcache.rs`, `crates/ml-core/src/state_layout.rs` — mixing in each file's relative path + length so renames / reorderings also bump the hash. Stable across rust versions and machines (FNV-1a, not `std::hash::DefaultHasher`). Emits `cargo:rustc-env=FEATURE_SCHEMA_HASH=<decimal_u64>` plus three `cargo:rerun-if-changed=` lines. (2) `crates/ml/src/fxcache.rs::FEATURE_SCHEMA_HASH` consumes the env var via `env!` + const `u64::from_str_radix(_, 10)` (const-stable since rust 1.83; workspace MSRV 1.85). `FxCacheHeader` grows a `feature_schema_hash: u64` field; header size 64→72 bytes; wire-format `FXCACHE_VERSION` bumped 5→6 to flag the layout change. `validate()` strict-checks the hash alongside magic/version/dims; mismatch bails with a descriptive error pointing at "source files defining feature extraction / state layout / fxcache format have changed since this cache was built." `precompute_features.rs:218` already deletes-and-regenerates on any `load_fxcache` Err, so the existing Argo `ensure-fxcache` step (and local users) recover automatically. (3) `FXCACHE_VERSION` doc comment now declares it tracks **wire-format** changes only — schema-level changes are tracked automatically by `FEATURE_SCHEMA_HASH`. Removes the manual ritual that broke the L40S deploy. **Cost**: cosmetic edits (whitespace, comments) to the three schema sources trigger one cache regen on next deploy (~5 min for full L40S dataset, ~40 s for local ES.FUT). Acceptable trade — false negatives (missed schema drift) are not. **Validation**: cargo check workspace clean at 11 warnings (baseline preserved). Local ES.FUT cache regen confirmed: existing v5 file rejected with `"Stale FxCache version: 5 (expected 6). Delete and regenerate."`, regenerated v6 cache loads clean on retry. Auto-detection verified: comment-only edit to `extraction.rs` line 1 changed emitted hash `5046469432341222878` → `7772630163018944575`; revert returned the hash deterministically to `5046469432341222878`. No new pip/cargo deps (FNV-1a is ~10 LOC stdlib). Files touched: `crates/ml/build.rs`, `crates/ml/src/fxcache.rs`, `docs/dqn-wire-up-audit.md` (this entry). No fingerprint change (LAYOUT_FINGERPRINT_CURRENT untouched — this is fxcache wire-format, not GPU param layout).
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| Classification | Count |
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|---|---|
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| Wired | 88 |
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