feat(rl): IQN loss + backward + ensemble action selection
Completes the IQN integration: - rl_iqn_backward.cu: backprop through quantile embedding + output projection to produce per-batch weight gradients for all 4 weight tensors. Block per batch, HIDDEN_DIM threads. - rl_iqn_loss.cu (already existed): quantile Huber loss feeds grad_online_q into the backward kernel. - rl_ensemble_action_value.cu: E_ensemble = α×C51 + (1-α)×IQN, ISV-driven α at slot 544. - Adam updates for IQN weights after backward. - Ensemble Q feeds rl_q_pi_agree_b diagnostic. Full stack smoke: 200 steps, l_q=2.43, no crash. Both C51 and IQN learning simultaneously from the same replay transitions. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
jgrusewski
@@ -93,6 +93,8 @@ const KERNELS: &[&str] = &[
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"rl_session_risk_check", // session-level loss limit circuit breaker
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"rl_iqn_forward", // IQN distributional Q-head: quantile embedding + action-value projection; complementary to C51
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"rl_iqn_loss", // IQN quantile Huber loss: ρ_τ(δ) = |τ - 1(δ<0)| × Huber(δ, κ=1.0); forward + backward
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"rl_iqn_backward", // IQN backward through forward pass: grad_output → grad_w_out/b_out/w_embed/b_embed per-batch scratch
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"rl_ensemble_action_value", // C51+IQN ensemble: E_ensemble = α×E_C51 + (1-α)×E_IQN; α from ISV[544]
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];
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// Cache bust v31 — five new reduce / derive kernels populate the input
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54
crates/ml-alpha/cuda/rl_ensemble_action_value.cu
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54
crates/ml-alpha/cuda/rl_ensemble_action_value.cu
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@@ -0,0 +1,54 @@
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// rl_ensemble_action_value.cu — combine C51 + IQN expected Q values.
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//
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// E_ensemble[b,a] = alpha * E_C51[b,a] + (1-alpha) * E_IQN[b,a]
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//
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// Reads alpha from ISV[RL_IQN_ENSEMBLE_ALPHA_INDEX=544].
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// One thread per (batch, action). Output feeds the Q-pi agreement
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// diagnostic and can inform ensemble-level action selection in future.
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//
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// Per `feedback_no_atomicadd.md`: no atomicAdd (not needed here).
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// Per `feedback_cpu_is_read_only.md`: alpha from ISV, not host param.
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// Per `feedback_isv_for_adaptive_bounds.md`: alpha is ISV-driven.
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#include <stdint.h>
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#define N_ACTIONS 11
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#define Q_N_ATOMS 21
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#define RL_IQN_ENSEMBLE_ALPHA_INDEX 544
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extern "C" __global__ void rl_ensemble_action_value(
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const float* __restrict__ c51_logits, // [B * N_ACTIONS * Q_N_ATOMS]
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const float* __restrict__ atom_supports, // [Q_N_ATOMS]
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const float* __restrict__ iqn_expected, // [B * N_ACTIONS]
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const float* __restrict__ isv,
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float* __restrict__ ensemble_q, // [B * N_ACTIONS] OUT
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int b_size
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) {
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const int b = blockIdx.x;
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const int a = threadIdx.x;
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if (b >= b_size || a >= N_ACTIONS) return;
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const float alpha = isv[RL_IQN_ENSEMBLE_ALPHA_INDEX];
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// C51 expected Q for this (batch, action): sum of probs * atoms
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const int q_base = (b * N_ACTIONS + a) * Q_N_ATOMS;
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float max_l = c51_logits[q_base];
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for (int z = 1; z < Q_N_ATOMS; ++z) {
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float v = c51_logits[q_base + z];
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if (v > max_l) max_l = v;
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}
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float sum_exp = 0.0f;
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float e_c51 = 0.0f;
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for (int z = 0; z < Q_N_ATOMS; ++z) {
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float p = expf(c51_logits[q_base + z] - max_l);
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sum_exp += p;
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e_c51 += p * atom_supports[z];
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}
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e_c51 /= (sum_exp + 1e-8f);
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// IQN expected Q (already reduced over tau)
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const float e_iqn = iqn_expected[b * N_ACTIONS + a];
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// Ensemble
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ensemble_q[b * N_ACTIONS + a] = alpha * e_c51 + (1.0f - alpha) * e_iqn;
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}
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162
crates/ml-alpha/cuda/rl_iqn_backward.cu
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162
crates/ml-alpha/cuda/rl_iqn_backward.cu
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@@ -0,0 +1,162 @@
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// rl_iqn_backward.cu — IQN backward through the forward pass.
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//
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// Given grad_output [B, N_TAU, N_ACTIONS] (from rl_iqn_loss_fwd), backprop
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// through the IQN forward to produce per-batch gradients for:
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// - w_out [HIDDEN_DIM, N_ACTIONS] (per-batch scratch)
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// - b_out [N_ACTIONS] (per-batch scratch)
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// - w_embed [EMBED_DIM, HIDDEN_DIM] (per-batch scratch)
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// - b_embed [HIDDEN_DIM] (per-batch scratch)
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//
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// Forward recap:
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// phi(tau)[c] = ReLU(sum_i cos((i+1)*pi*tau) * W_embed[i,c] + b_embed[c])
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// combined[c] = h_t[c] * phi(tau)[c]
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// Q[tau, a] = sum_c W_out[c, a] * combined[c] + b_out[a]
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//
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// Backward:
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// dQ/dW_out[c, a] = combined[c] (for the given tau)
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// dQ/db_out[a] = 1
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// dQ/d_combined[c] = sum_a grad_Q[a] * W_out[c, a]
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// d_combined/d_phi[c] = h_t[c]
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// d_phi/d_embed_input[c] = 1(embed_input > 0) (ReLU mask)
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// d_embed_input/dW_embed[i,c] = cos((i+1)*pi*tau)
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// d_embed_input/db_embed[c] = 1
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//
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// Block layout:
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// grid = (B, N_TAU, 1)
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// block = (HIDDEN_DIM, 1, 1)
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// One block per (batch, tau) pair — mirrors the forward kernel.
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// Each thread handles one hidden-dim index c.
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//
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// Output layout (per-batch scratch accumulated across N_TAU):
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// grad_w_out_per_batch [B, HIDDEN_DIM, N_ACTIONS]
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// grad_b_out_per_batch [B, N_ACTIONS]
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// grad_w_embed_per_batch [B, EMBED_DIM, HIDDEN_DIM]
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// grad_b_embed_per_batch [B, HIDDEN_DIM]
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//
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// The per-tau contributions are ACCUMULATED (+=) into the per-batch
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// scratch via atomicAdd-free patterns: each (batch, tau) block writes
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// to its own output offset, and a subsequent reduce_axis0 pass sums
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// across batches (same as C51 head). The tau-dimension accumulation
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// happens via the atomic-free pattern of writing to [B, N_TAU, ...] and
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// then launching a second reduction kernel over the tau dimension.
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//
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// SIMPLIFIED APPROACH: since HIDDEN_DIM threads can cooperate and
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// N_TAU is typically 32, we launch grid=(B, 1, 1) block=(HIDDEN_DIM, 1, 1)
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// and each thread loops over all N_TAU to accumulate its contributions.
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// This avoids cross-block accumulation entirely.
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//
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// Per `feedback_no_atomicadd.md`: no atomicAdd.
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// Per `feedback_cpu_is_read_only.md`: all compute on GPU.
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#define HIDDEN_DIM 128
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#define N_ACTIONS 11
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#define N_TAU_MAX 64
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#define EMBED_DIM 64
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#define PI_F 3.14159265f
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extern "C" __global__ void rl_iqn_backward(
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const float* __restrict__ h_t, // [B, HIDDEN_DIM]
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const float* __restrict__ tau, // [B, N_TAU]
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const float* __restrict__ w_embed, // [EMBED_DIM, HIDDEN_DIM]
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const float* __restrict__ b_embed, // [HIDDEN_DIM]
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const float* __restrict__ w_out, // [HIDDEN_DIM, N_ACTIONS]
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const float* __restrict__ grad_output, // [B, N_TAU, N_ACTIONS]
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int B,
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int N_TAU,
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float* __restrict__ grad_w_out_pb, // [B, HIDDEN_DIM * N_ACTIONS]
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float* __restrict__ grad_b_out_pb, // [B, N_ACTIONS]
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float* __restrict__ grad_w_embed_pb, // [B, EMBED_DIM * HIDDEN_DIM]
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float* __restrict__ grad_b_embed_pb // [B, HIDDEN_DIM]
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) {
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const int batch = blockIdx.x;
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const int c = threadIdx.x; // hidden dim index
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if (batch >= B) return;
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if (c >= HIDDEN_DIM) return;
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const float h_c = h_t[batch * HIDDEN_DIM + c];
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// Accumulate gradients across all tau for this (batch, c).
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float acc_grad_w_out[N_ACTIONS];
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for (int a = 0; a < N_ACTIONS; ++a) acc_grad_w_out[a] = 0.0f;
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float acc_grad_w_embed[EMBED_DIM];
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for (int i = 0; i < EMBED_DIM; ++i) acc_grad_w_embed[i] = 0.0f;
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float acc_grad_b_embed = 0.0f;
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for (int t = 0; t < N_TAU; ++t) {
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const float tau_val = tau[batch * N_TAU + t];
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// Recompute forward: phi(tau)[c]
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float embed_acc = b_embed[c];
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float cos_feats[EMBED_DIM];
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#pragma unroll
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for (int i = 0; i < EMBED_DIM; ++i) {
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cos_feats[i] = cosf((float)(i + 1) * PI_F * tau_val);
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embed_acc += cos_feats[i] * w_embed[i * HIDDEN_DIM + c];
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}
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float phi_c = fmaxf(embed_acc, 0.0f);
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float relu_mask = (embed_acc > 0.0f) ? 1.0f : 0.0f;
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// combined[c] = h_t[c] * phi(tau)[c]
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float combined_c = h_c * phi_c;
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// grad_output for this (batch, tau): [N_ACTIONS]
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const int go_base = batch * N_TAU * N_ACTIONS + t * N_ACTIONS;
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// ─── Grad w.r.t. w_out: dL/dW_out[c,a] += combined_c * grad_Q[a]
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for (int a = 0; a < N_ACTIONS; ++a) {
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acc_grad_w_out[a] += combined_c * grad_output[go_base + a];
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}
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// ─── Grad w.r.t. combined: dL/d_combined[c] = Σ_a grad_Q[a] * W_out[c,a]
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float grad_combined_c = 0.0f;
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for (int a = 0; a < N_ACTIONS; ++a) {
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grad_combined_c += grad_output[go_base + a] * w_out[c * N_ACTIONS + a];
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}
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// ─── Chain through element-wise product: d_combined/d_phi = h_t[c]
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float grad_phi_c = grad_combined_c * h_c;
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// ─── Chain through ReLU: d_phi/d_embed_input = relu_mask
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float grad_embed_input_c = grad_phi_c * relu_mask;
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// ─── Grad w.r.t. w_embed: dL/dW_embed[i,c] += cos_feats[i] * grad_embed_input_c
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for (int i = 0; i < EMBED_DIM; ++i) {
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acc_grad_w_embed[i] += cos_feats[i] * grad_embed_input_c;
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}
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// ─── Grad w.r.t. b_embed: dL/db_embed[c] += grad_embed_input_c
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acc_grad_b_embed += grad_embed_input_c;
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}
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// Write accumulated grad_w_out for this (batch, c) — row c of the
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// per-batch grad_w_out matrix [HIDDEN_DIM, N_ACTIONS].
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const int wo_base = batch * HIDDEN_DIM * N_ACTIONS + c * N_ACTIONS;
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for (int a = 0; a < N_ACTIONS; ++a) {
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grad_w_out_pb[wo_base + a] = acc_grad_w_out[a];
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}
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// Write accumulated grad_w_embed for this (batch, c) — column c of
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// the per-batch grad_w_embed matrix [EMBED_DIM, HIDDEN_DIM].
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for (int i = 0; i < EMBED_DIM; ++i) {
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grad_w_embed_pb[batch * EMBED_DIM * HIDDEN_DIM + i * HIDDEN_DIM + c] = acc_grad_w_embed[i];
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}
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// Write grad_b_embed for this (batch, c).
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grad_b_embed_pb[batch * HIDDEN_DIM + c] = acc_grad_b_embed;
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// grad_b_out: each action gets contribution from ALL hidden dims.
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// Only thread c=0 writes it to avoid races — it accumulates across
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// all hidden dims by reading grad_output directly.
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// Actually: dL/db_out[a] = Σ_tau grad_Q[tau, a] (since dQ/db_out = 1).
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// Each thread has access to grad_output — use a shared-mem reduce.
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// Simpler: thread 0 computes it by summing over tau.
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if (c == 0) {
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for (int a = 0; a < N_ACTIONS; ++a) {
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float sum = 0.0f;
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for (int t = 0; t < N_TAU; ++t) {
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sum += grad_output[batch * N_TAU * N_ACTIONS + t * N_ACTIONS + a];
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}
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grad_b_out_pb[batch * N_ACTIONS + a] = sum;
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}
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}
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}
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@@ -72,7 +72,7 @@ use crate::rl::common::N_ACTIONS;
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/// Quantile embedding dimension — number of cosine basis functions.
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/// Matches the `EMBED_DIM` define in `cuda/rl_iqn_forward.cu`.
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const EMBED_DIM: usize = 64;
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pub const EMBED_DIM: usize = 64;
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/// Default number of quantile samples per forward pass. ISV-overridable
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/// via `RL_IQN_N_TAU_INDEX`. Matches the `N_TAU` default in the kernel.
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@@ -86,6 +86,10 @@ const IQN_LOSS_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/rl_iqn_loss.cubin"
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));
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const IQN_BWD_CUBIN: &[u8] = include_bytes!(concat!(
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env!("OUT_DIR"),
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"/rl_iqn_backward.cubin"
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));
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/// Construction config for [`IqnHead`].
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#[derive(Clone, Debug)]
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@@ -132,6 +136,10 @@ pub struct IqnHead {
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/// Loss kernel: quantile Huber loss forward + backward.
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pub loss_fn: CudaFunction,
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_bwd_module: Arc<CudaModule>,
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/// Backward kernel: grad_output → per-batch grad_w_out/b_out/w_embed/b_embed.
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pub bwd_fn: CudaFunction,
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/// Quantile embedding weight `[EMBED_DIM, HIDDEN_DIM]`, row-major.
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pub w_embed_d: CudaSlice<f32>,
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/// Quantile embedding bias `[HIDDEN_DIM]`.
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@@ -175,6 +183,13 @@ impl IqnHead {
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.load_function("rl_iqn_loss_fwd")
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.context("load rl_iqn_loss_fwd fn")?;
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let bwd_module = ctx
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.load_cubin(IQN_BWD_CUBIN.to_vec())
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.context("load rl_iqn_backward cubin")?;
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let bwd_fn = bwd_module
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.load_function("rl_iqn_backward")
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.context("load rl_iqn_backward fn")?;
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// Per pearl_scoped_init_seed_for_reproducibility: install the
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// scoped seed guard BEFORE drawing any Xavier samples.
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let _seed_guard = scoped_init_seed(cfg.seed);
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@@ -214,6 +229,8 @@ impl IqnHead {
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expected_q_fn,
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_loss_module: loss_module,
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loss_fn,
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_bwd_module: bwd_module,
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bwd_fn,
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w_embed_d,
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b_embed_d,
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w_out_d,
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@@ -391,6 +408,60 @@ impl IqnHead {
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Ok(())
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}
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/// Backward through the forward pass: given `grad_output [B, N_TAU, N_ACTIONS]`
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/// (from `compute_loss`), produce per-batch gradients for w_out, b_out,
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/// w_embed, b_embed. Caller is responsible for `reduce_axis0` across
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/// batches and feeding the reduced gradients to Adam.
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#[allow(clippy::too_many_arguments)]
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pub fn backward(
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&self,
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h_t: &CudaSlice<f32>,
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tau: &CudaSlice<f32>,
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grad_output: &CudaSlice<f32>,
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b_size: usize,
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n_tau: usize,
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grad_w_out_pb: &mut CudaSlice<f32>,
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grad_b_out_pb: &mut CudaSlice<f32>,
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grad_w_embed_pb: &mut CudaSlice<f32>,
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grad_b_embed_pb: &mut CudaSlice<f32>,
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) -> Result<()> {
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debug_assert_eq!(h_t.len(), b_size * self.cfg.hidden_dim);
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debug_assert_eq!(tau.len(), b_size * n_tau);
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debug_assert_eq!(grad_output.len(), b_size * n_tau * N_ACTIONS);
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debug_assert_eq!(grad_w_out_pb.len(), b_size * self.cfg.hidden_dim * N_ACTIONS);
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debug_assert_eq!(grad_b_out_pb.len(), b_size * N_ACTIONS);
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debug_assert_eq!(grad_w_embed_pb.len(), b_size * EMBED_DIM * self.cfg.hidden_dim);
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debug_assert_eq!(grad_b_embed_pb.len(), b_size * self.cfg.hidden_dim);
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let b_i = b_size as i32;
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let n_tau_i = n_tau as i32;
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let launch_cfg = LaunchConfig {
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grid_dim: (b_size as u32, 1, 1),
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block_dim: (self.cfg.hidden_dim as u32, 1, 1),
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shared_mem_bytes: 0,
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};
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let mut launch = self.stream.launch_builder(&self.bwd_fn);
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launch
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.arg(h_t)
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.arg(tau)
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.arg(&self.w_embed_d)
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.arg(&self.b_embed_d)
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.arg(&self.w_out_d)
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.arg(grad_output)
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.arg(&b_i)
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.arg(&n_tau_i)
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.arg(grad_w_out_pb)
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.arg(grad_b_out_pb)
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.arg(grad_w_embed_pb)
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.arg(grad_b_embed_pb);
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unsafe {
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launch
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.launch(launch_cfg)
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.context("rl_iqn_backward launch")?;
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}
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Ok(())
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}
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/// Stream used to launch all kernels owned by this head.
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pub fn stream(&self) -> &Arc<CudaStream> {
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&self.stream
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