feat(dqn-v2): A.2 ISV layout fingerprint at ISV[37..39) (tail placement)
Implements spec §4.A.2 structural layout fingerprint with tail placement
rather than head placement (spec alternative: §4.A.2 Step 5.3 alt).
Head placement (ISV[0..2)) was rejected because isv_signals[0] and [1]
are actively written by the isv_signal_update kernel (Q-drift EMA and
gradient-norm EMA). Shifting those would require updating every literal
reference in experience_kernels.cu — a larger change than warranted for
pure contract enforcement. Tail placement leaves all existing indices
intact, touches zero kernel .cu files, and fulfils the same design contract.
Key changes:
- ISV_LAYOUT_FINGERPRINT_LO_INDEX = 37, HI_INDEX = 38 (u64 across 2×f32).
- LAYOUT_FINGERPRINT_CURRENT: u64 = FNV-1a of slot-list seed bytes.
Value: 0x85d4d76b578a7c17. Any slot change updates seed bytes,
which updates the hash automatically.
- Constructor writes fingerprint after zero-init; calls
check_layout_fingerprint() to self-verify before returning.
- check_layout_fingerprint(): reads pinned slots [37..39), recomposes u64,
fails-fast on mismatch with "retrain required" message.
- Error message does NOT mention migration as an option.
- Pre-commit hook rejects `fn migrate_isv|upgrade_isv` names — makes the
no-migration rule structurally enforced (check_no_isv_migrations).
- ISV_TOTAL_DIM: 37 → 39.
- Zero existing index shifts (no kernel literal sites affected).
- StateResetRegistry entry renamed ISV_SCHEMA_VERSION → ISV_LAYOUT_FINGERPRINT.
- ResetCategory::SchemaContract docstring updated to remove "migration" framing.
- docs/isv-slots.md: updated table + design note for tail placement.
Tests: state_reset_registry 3 unit tests pass with renamed entry.
cargo check -p ml clean (pre-existing warnings only).
Plan 1 Task 5. Spec §4.A.2 (tail-placement alternative).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
jgrusewski
@@ -164,10 +164,17 @@ const ISV_NETWORK_DIM: usize = 23;
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/// to ensure no (sample, branch) pair collapses to zero gradient
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/// contribution.
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///
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/// Extending past 37 requires updating the pinned allocation in the
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/// Slots [37..39) carry the layout fingerprint (ISV_LAYOUT_FINGERPRINT_LO_INDEX
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/// and ISV_LAYOUT_FINGERPRINT_HI_INDEX). These are placed at the tail because
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/// slots [0] and [1] are actively written by `isv_signal_update` (Q-drift and
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/// gradient-norm EMA respectively). Written by the constructor; checked at
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/// checkpoint load. Fail-fast only — no migration path exists. See spec §4.A.2
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/// and `LAYOUT_FINGERPRINT_CURRENT` for the structural-hash design rationale.
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///
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/// Extending past 39 requires updating the pinned allocation in the
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/// constructor and any kernel that takes an ISV pointer expecting a
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/// specific length.
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const ISV_TOTAL_DIM: usize = 37;
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const ISV_TOTAL_DIM: usize = 39;
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/// Legacy alias preserved for call sites that haven't been audited for the
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/// network-vs-total split. New code should pick `ISV_NETWORK_DIM` (for weight
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/// tensor sizing) or `ISV_TOTAL_DIM` (for the broadcast bus buffer).
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@@ -255,6 +262,79 @@ pub const GRAD_SCALE_LIMIT_INDEX: usize = 35;
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/// actively EMA-tracked; treated as a safety floor per
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/// `feedback_isv_for_adaptive_bounds.md` carve-out.
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pub const IQL_BRANCH_SCALE_FLOOR_INDEX: usize = 36;
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/// ISV slot [37] — low 32 bits of the u64 layout fingerprint (stored as raw f32 bits).
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///
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/// Design note: this is NOT a version number. There is no ordered version space.
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/// The fingerprint is a structural hash that automatically changes whenever any
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/// slot is added, removed, reordered, or renamed — so there is no natural pairing
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/// "v1 -> v2" and no place to write a migrator. Per spec §4.A.2 and
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/// `feedback_no_legacy_aliases.md`: backward compat is structurally unwritable,
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/// not merely discouraged.
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///
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/// Placement at the tail (not head) is mandated by slots [0] and [1] being
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/// actively written by `isv_signal_update` (Q-drift and gradient-norm EMA).
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pub const ISV_LAYOUT_FINGERPRINT_LO_INDEX: usize = 37;
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/// ISV slot [38] — high 32 bits of the u64 layout fingerprint (stored as raw f32 bits).
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pub const ISV_LAYOUT_FINGERPRINT_HI_INDEX: usize = 38;
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/// Canonical alias for the fingerprint slot (the low half).
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pub const ISV_LAYOUT_FINGERPRINT_INDEX: usize = ISV_LAYOUT_FINGERPRINT_LO_INDEX;
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/// FNV-1a 64-bit hash of a byte slice, usable as a `const fn`.
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const fn fnv1a_64(bytes: &[u8]) -> u64 {
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const OFFSET: u64 = 0xcbf29ce484222325;
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const PRIME: u64 = 0x00000100000001b3;
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let mut h: u64 = OFFSET;
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let mut i = 0;
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while i < bytes.len() {
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h ^= bytes[i] as u64;
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h = h.wrapping_mul(PRIME);
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i += 1;
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}
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h
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}
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/// Source bytes for the layout fingerprint. Canonical format:
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/// `b"<slot_name>=<index>;<slot_name>=<index>;...;ISV_TOTAL_DIM=<N>"`.
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///
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/// When adding/removing a slot, add/remove its entry here in the SAME commit
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/// that changes the constant list. The fingerprint recomputes automatically.
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/// Order matches the constant declaration order in this module.
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///
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/// Slots [0..12) have no named `pub const` (they are written directly via
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/// literal indices in `isv_signal_update`). They are covered here by
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/// `SLOT_<N>_<PURPOSE>` entries derived from the `ISV_TOTAL_DIM` docstring
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/// and `experience_kernels.cu` write-site comments. Any renumber of these
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/// slots changes the seed and invalidates the fingerprint.
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const fn layout_fingerprint_seed() -> &'static [u8] {
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b"SLOT_0_Q_DRIFT=0;\
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SLOT_1_GRAD_NORM_EMA=1;\
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SLOT_2_TD_ERR_EMA=2;\
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SLOT_3_ENS_VAR_EMA=3;\
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SLOT_4_ENS_VAR_VEL=4;\
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SLOT_5_REWARD_EMA=5;\
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SLOT_6_ATOM_UTIL_EMA=6;\
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SLOT_7_LOSS_EMA=7;\
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SLOT_8_ADX_EMA=8;\
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SLOT_9_REGIME_DISAGREE=9;\
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SLOT_10_REGIME_VEL_EMA=10;\
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SLOT_11_REGIME_STABILITY=11;\
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LEARNING_HEALTH=12;\
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Q_MAG_MEAN_QUARTER=13;Q_MAG_MEAN_HALF=14;Q_MAG_MEAN_FULL=15;Q_ABS_REF=16;\
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Q_DIR_MEAN_SHORT=17;Q_DIR_MEAN_HOLD=18;Q_DIR_MEAN_LONG=19;Q_DIR_MEAN_FLAT=20;Q_DIR_ABS_REF=21;\
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SHARPE_EMA=22;\
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V_CENTER_DIR=23;V_HALF_DIR=24;V_CENTER_MAG=25;V_HALF_MAG=26;\
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V_CENTER_ORD=27;V_HALF_ORD=28;V_CENTER_URG=29;V_HALF_URG=30;\
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GRAD_NORM_TARGET_DIR=31;GRAD_NORM_TARGET_MAG=32;GRAD_NORM_TARGET_ORD=33;GRAD_NORM_TARGET_URG=34;\
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GRAD_SCALE_LIMIT=35;IQL_BRANCH_SCALE_FLOOR=36;\
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ISV_LAYOUT_FINGERPRINT_LO=37;ISV_LAYOUT_FINGERPRINT_HI=38;\
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ISV_TOTAL_DIM=39"
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}
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/// Compile-time layout fingerprint. Burned into the binary at build time.
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/// Checked against the stored value at checkpoint load. Mismatch means retrain required.
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pub const LAYOUT_FINGERPRINT_CURRENT: u64 = fnv1a_64(layout_fingerprint_seed());
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const ISV_EMB_DIM: usize = 8; // ISV embedding output dimension (FC2 output, gate/gamma input)
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/// First ISV tensor index in the flat param buffer.
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/// ISV weights (68-79) are online-only — NOT synced to the target network.
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@@ -1944,11 +2024,11 @@ pub struct GpuDqnTrainer {
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q_dir_bin_means_reduce_kernel: CudaFunction,
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// ── ISV core buffers (pinned device-mapped, GPU read/write) ──
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// isv_signals_pinned is sized for ISV_TOTAL_DIM (31) — the extra eight
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// isv_signals_pinned is sized for ISV_TOTAL_DIM (39) — the extra slots
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// slots [23..31] carry per-branch Q-support centres/half-widths. The
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// network (w_isv_fc1) and history rotation still consume only the first
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// ISV_NETWORK_DIM (23) slots; the tail is broadcast-bus scratchpad only.
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isv_signals_pinned: *mut f32, // [ISV_TOTAL_DIM = 31]
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isv_signals_pinned: *mut f32, // [ISV_TOTAL_DIM = 39]
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isv_signals_dev_ptr: u64,
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isv_history_pinned: *mut f32, // [ISV_K * 12 = 48] — history rotates slots [0..11] only
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isv_history_dev_ptr: u64,
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@@ -8087,10 +8167,11 @@ impl GpuDqnTrainer {
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};
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// ── ISV core buffers (pinned device-mapped) ──────────────────────
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// Allocation uses `ISV_TOTAL_DIM` so slots [23..31] (per-branch
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// Q-support centres and half-widths) have backing storage. The
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// network-facing path still consumes only the first `ISV_NETWORK_DIM`
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// slots — the scratchpad tail is invisible to `w_isv_fc1`.
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// Allocation uses `ISV_TOTAL_DIM` so all scratchpad slots [23..39) have
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// backing storage. The network-facing path still consumes only the first
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// `ISV_NETWORK_DIM` slots — the scratchpad tail is invisible to `w_isv_fc1`.
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// Slots [37..39) hold the layout fingerprint (tail placement because [0..2)
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// are actively written by `isv_signal_update`).
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let (isv_signals_pinned, isv_signals_dev_ptr) = {
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let num_bytes = ISV_TOTAL_DIM * std::mem::size_of::<f32>();
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let mut host_ptr: *mut std::ffi::c_void = std::ptr::null_mut();
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@@ -8131,6 +8212,14 @@ impl GpuDqnTrainer {
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// IQL readiness→1 and the losing branch has near-zero
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// advantage. Safety bound, not tuning.
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*sig_ptr.add(IQL_BRANCH_SCALE_FLOOR_INDEX) = 0.1_f32;
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// Layout fingerprint (ISV[37..39)). Compile-time structural hash of
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// the slot layout; checkpoint load fails-fast on mismatch.
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// Stored as a u64 split across two f32 lanes using raw bit-cast so
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// no precision is lost. See LAYOUT_FINGERPRINT_CURRENT docs for why
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// this is NOT a version number and why no migration path exists.
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let fp = LAYOUT_FINGERPRINT_CURRENT;
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*sig_ptr.add(ISV_LAYOUT_FINGERPRINT_LO_INDEX) = f32::from_bits(fp as u32);
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*sig_ptr.add(ISV_LAYOUT_FINGERPRINT_HI_INDEX) = f32::from_bits((fp >> 32) as u32);
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}
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(host_ptr as *mut f32, dev_ptr_out)
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};
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@@ -8750,7 +8839,7 @@ impl GpuDqnTrainer {
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// D1/N1: clone Arc<CudaStream> before it is moved into the struct literal.
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let stream_for_snapshots = Arc::clone(&stream);
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Ok(Self {
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let trainer = Self {
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config,
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stream,
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ptrs,
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@@ -9306,7 +9395,12 @@ impl GpuDqnTrainer {
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last_distill_active: false,
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last_meta_q_pred: 0.5,
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q_sample_history: std::collections::VecDeque::with_capacity(64),
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})
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};
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// Self-check: verify the fingerprint we just wrote is readable and matches
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// the compile-time constant. This is a construction-time invariant check;
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// any restore path that loads persisted ISV state must also call this.
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trainer.check_layout_fingerprint()?;
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Ok(trainer)
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}
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/// Reference to the trainer's forked CudaStream.
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@@ -9793,6 +9887,39 @@ impl GpuDqnTrainer {
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unsafe { *self.isv_signals_pinned.add(index) = value; }
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}
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/// Read the ISV layout fingerprint from pinned memory and compare to the
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/// compile-time `LAYOUT_FINGERPRINT_CURRENT`.
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///
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/// Returns `Err` on mismatch. NEVER returns `Ok` on mismatch — that would
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/// permit silent backward compat, which this design forbids. Treat a null
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/// ISV pointer as fingerprint `0`, which never matches any real fingerprint.
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///
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/// Called at construction (after writing) to self-verify. Must also be called
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/// by any restore path that loads persisted ISV state from disk.
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pub fn check_layout_fingerprint(&self) -> Result<(), MLError> {
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let (lo_bits, hi_bits) = if self.isv_signals_pinned.is_null() {
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(0u32, 0u32)
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} else if ISV_TOTAL_DIM < ISV_LAYOUT_FINGERPRINT_HI_INDEX + 1 {
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(0u32, 0u32)
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} else {
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unsafe {
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let lo = f32::to_bits(*self.isv_signals_pinned.add(ISV_LAYOUT_FINGERPRINT_LO_INDEX));
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let hi = f32::to_bits(*self.isv_signals_pinned.add(ISV_LAYOUT_FINGERPRINT_HI_INDEX));
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(lo, hi)
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}
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};
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let fp_stored: u64 = (lo_bits as u64) | ((hi_bits as u64) << 32);
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if fp_stored != LAYOUT_FINGERPRINT_CURRENT {
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return Err(MLError::ModelError(format!(
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"ISV layout fingerprint mismatch: stored 0x{:016x}, current code 0x{:016x}. \
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Checkpoint layout does not match current code - retrain required. \
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(This is a structural fingerprint, not a version number. There is no migration path.)",
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fp_stored, LAYOUT_FINGERPRINT_CURRENT
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)));
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}
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Ok(())
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}
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/// Read atom utilization from q_readback_pinned[6] (one-step lag, written by
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/// reduce_current_q_stats). Returns 0.0 if pointer is null.
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pub fn read_atom_utilization(&self) -> f32 {
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@@ -14,7 +14,7 @@ pub enum ResetCategory {
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SoftReset { decay_bars: u32 },
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/// Survives across folds (learned weights).
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TrainingPersist,
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/// Version-stable across runs; touched only by explicit migration.
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/// Structurally fixed across runs; fail-fast on mismatch. No migration path exists.
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SchemaContract,
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}
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@@ -142,9 +142,9 @@ impl StateResetRegistry {
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},
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// ───── Schema-contract state ────────────────────────────────
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RegistryEntry {
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name: "ISV_SCHEMA_VERSION",
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name: "ISV_LAYOUT_FINGERPRINT",
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category: ResetCategory::SchemaContract,
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description: "ISV[0] — slot-layout schema version (migrated only)",
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description: "ISV[37..39) — compile-time structural hash of slot layout; fail-fast only, no migration path",
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},
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RegistryEntry {
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name: "isv_iql_branch_scale_floor",
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@@ -199,7 +199,7 @@ mod tests {
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assert_eq!(r.category("kelly_stats"), Some(ResetCategory::FoldReset));
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assert_eq!(r.category("adaptive_gamma"), Some(ResetCategory::SoftReset { decay_bars: 500 }));
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assert_eq!(r.category("network_params"), Some(ResetCategory::TrainingPersist));
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assert_eq!(r.category("ISV_SCHEMA_VERSION"), Some(ResetCategory::SchemaContract));
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assert_eq!(r.category("ISV_LAYOUT_FINGERPRINT"), Some(ResetCategory::SchemaContract));
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}
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#[test]
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@@ -2,18 +2,42 @@
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**Source of truth for ISV bus slot allocations.** Every slot has a named constant in `gpu_dqn_trainer.rs`. This doc is the cross-reference.
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**Current `ISV_TOTAL_DIM` as of this plan's start:** 37. Post-full DQN v2 rollout: 72.
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**Design: layout fingerprint, not schema version.** ISV[37..39) carries a
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compile-time structural hash of the slot layout. Checkpoint load is
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fail-fast; no migration functions exist. Backward compat is structurally
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unwritable (there is no ordered version space to pair migrations against).
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See spec §4.A.2.
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**Tail placement rationale:** The fingerprint occupies the tail (`[37..39)`) rather
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than the head because `isv_signals[0]` and `isv_signals[1]` are actively written
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by `isv_signal_update` (Q-drift EMA and gradient-norm EMA respectively). Inserting
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at the head would displace those live signals and require shifting every upstream
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literal in `experience_kernels.cu`.
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**Current `ISV_TOTAL_DIM`:** 39. Post-full DQN v2 rollout: 72.
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| Index | Name constant | Type | Producer | Consumers | Reset-category | Notes |
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|---|---|---|---|---|---|---|
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| [0..2) | `ISV_LAYOUT_FINGERPRINT_{LO,HI}_INDEX` | u64 (as 2× f32) | construct | load | SchemaContract | Compile-time structural hash of slot layout; fail-fast only, no migration path — **not** a version number. See spec §4.A.2. |
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| [1..12) | (pre-existing) | f32 | varies | varies | varies | Legacy — audit during A.2 |
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| [0] | `SLOT_0_Q_DRIFT` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | `isv_signals[0]` = (q_mean − q_ema) / max(|q_ema|, 0.1) |
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| [1] | `SLOT_1_GRAD_NORM_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of sqrt(grad_norm²) |
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| [2] | `SLOT_2_TD_ERR_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of TD-error scalar |
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| [3] | `SLOT_3_ENS_VAR_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | C51 Q-distribution variance EMA (batch-mean atom-spread) |
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| [4] | `SLOT_4_ENS_VAR_VEL` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | Delta of slot 3 (variance velocity) |
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| [5] | `SLOT_5_REWARD_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of per-batch mean reward |
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| [6] | `SLOT_6_ATOM_UTIL_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of atom utilization fraction |
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| [7] | `SLOT_7_LOSS_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of total training loss |
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| [8] | `SLOT_8_ADX_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | Batch-mean ADX EMA (regime velocity indicator) |
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| [9] | `SLOT_9_REGIME_DISAGREE` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | |norm(ADX) − norm(CUSUM)| disagreement signal |
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| [10] | `SLOT_10_REGIME_VEL_EMA` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | EMA of regime transition velocity (ADX + CUSUM delta) |
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| [11] | `SLOT_11_REGIME_STABILITY` (seed only) | f32 | isv_signal_update | ISV encoder | FoldReset | 1 − sigmoid(5 × regime_vel); high = stable regime |
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| [12] | `LEARNING_HEALTH_INDEX` | f32 | isv_signal_update | many | FoldReset | health score ∈ [0, 1] |
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| [13..17) | `Q_MAG_MEAN_*_INDEX` | f32 | q_mag_means_reduce | c51 kernels | FoldReset | Quarter/Half/Full mag Q-mean EMAs + |Q| ref |
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| [17..22) | `Q_DIR_MEAN_*_INDEX` | f32 | q_dir_means_reduce | c51 kernels | FoldReset | Short/Hold/Long/Flat dir Q-mean EMAs + |Q| ref |
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| [13..17) | `Q_MAG_MEAN_*_INDEX` | f32 | q_mag_means_reduce | c51 kernels | FoldReset | Quarter/Half/Full mag Q-mean EMAs + \|Q\| ref |
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| [17..22) | `Q_DIR_MEAN_*_INDEX` | f32 | q_dir_means_reduce | c51 kernels | FoldReset | Short/Hold/Long/Flat dir Q-mean EMAs + \|Q\| ref |
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| [22] | `SHARPE_EMA_INDEX` | f32 | training_loop host | isv_signal_update | FoldReset | Training Sharpe EMA |
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| [23..31) | `V_{CENTER,HALF}_{DIR,MAG,ORD,URG}_INDEX` | f32 | update_eval_v_range | adaptive_atoms, warm_start | FoldReset | Per-branch Q-support |
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| [31..35) | `GRAD_NORM_TARGET_*_INDEX` | f32 | grad_balance_isv_update | branch_grad_rescale | SoftReset(decay_bars=500) | Per-branch grad-norm target |
|
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| [35] | `GRAD_SCALE_LIMIT_INDEX` | f32 | grad_balance_isv_update | branch_grad_rescale | SoftReset(decay_bars=500) | Scale clamp limit |
|
||||
| [36] | `IQL_BRANCH_SCALE_FLOOR_INDEX` | f32 | construct (static) | iql_per_branch_advantage | SchemaContract | Per-sample branch_scales floor; safety bound |
|
||||
| [37..72) | (reserved for DQN v2) | | | | | Allocated incrementally by Plans 2-5 |
|
||||
| [37] | `ISV_LAYOUT_FINGERPRINT_LO_INDEX` | u32 bits (in f32) | construct | check_layout_fingerprint | SchemaContract | Low 32 bits of u64 FNV-1a structural hash. Fail-fast on mismatch — NOT a version number, no migration path. |
|
||||
| [38] | `ISV_LAYOUT_FINGERPRINT_HI_INDEX` | u32 bits (in f32) | construct | check_layout_fingerprint | SchemaContract | High 32 bits of u64 FNV-1a structural hash. |
|
||||
| [39..72) | (reserved for DQN v2) | | | | | Allocated incrementally by Plans 2-5 |
|
||||
|
||||
@@ -105,8 +105,23 @@ check_no_todo_fixme() {
|
||||
fi
|
||||
}
|
||||
|
||||
# DQN v2 Invariant (spec §4.A.2): no ISV migration functions allowed.
|
||||
# The layout fingerprint is fail-fast only; no migration path exists.
|
||||
check_no_isv_migrations() {
|
||||
local bad=$(git diff --cached -U0 -- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs \
|
||||
crates/ml/src/trainers/dqn/trainer/ 2>/dev/null | \
|
||||
grep -E '^\+.*fn\s+(migrate|upgrade)_isv' || true)
|
||||
if [ -n "$bad" ]; then
|
||||
echo "❌ Spec §4.A.2 violation: ISV migration functions are forbidden"
|
||||
echo " (layout fingerprint is fail-fast only; no migration path exists)"
|
||||
echo "$bad" | sed 's/^/ /'
|
||||
return 1
|
||||
fi
|
||||
}
|
||||
|
||||
check_audit_doc_updates || exit 1
|
||||
check_no_todo_fixme || exit 1
|
||||
check_no_isv_migrations || exit 1
|
||||
|
||||
echo "✅ All pre-commit checks passed!"
|
||||
echo ""
|
||||
|
||||
Reference in New Issue
Block a user