07ac5ceea5dd7cb8fdc8f22eb3bf759d69a944a1
2498 Commits
| Author | SHA1 | Message | Date | |
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jgrusewski
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07ac5ceea5 |
test(state_reset): contract test — every RegistryEntry has dispatch arm
Surfaced the SP7 T7 dispatch-arm bug at runtime (unknown-name panic at fold boundary). This test enumerates RegistryEntry names from StateResetRegistry::new() and asserts each has a match arm in reset_named_state, catching the bug at `cargo test -p ml --lib` instead of mid-training. Source-introspection design — no production-code change. Test fails fast if a future contributor adds a registry entry without the corresponding dispatch arm. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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023c62da28 |
test(magnitude_distribution): assert on EVAL_INTENT (pre-Kelly-cap), not EVAL_DIST
Pre-existing test bug: line 164 asserted `ef >= 0.05` (post-Kelly-cap eval_dist), which gates on Kelly cold-start warmup completing within the smoke's training horizon — not on whether the Q-head learned to prefer Full magnitude. On the local-laptop smoke (1 quarter MBP-10), Kelly warmup never completes, pinning eval_dist[Full] = 0 even when Q(Full) > Q(Half) clearly. Per `project_magnitude_eval_collapse_kelly_capped`, the diagnostic split landed in #212: intent_dist measures policy learning, eval_dist measures policy + Kelly-cap. Tests asserting on Q-learning success must use intent_dist; the test was never updated. Smoke now PASSES with intent_full=0.057 (intent_full=0.866 in the prior re-run — both above the 0.05 threshold; Q(Full) is clearly preferred when Kelly cap doesn't suppress it). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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6e479c55c7 |
sp7(state): T2 bug-fix — add 4 missing reset_named_state dispatch arms
T2 (commit
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jgrusewski
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148aa1f464 |
test(integration): migrate CudaSlice→MappedF32Buffer in tests blocked since Bug-1 close-out
Three compile errors in crates/ml/tests/smoke_test_real_data.rs at lines 568, 644, and 715 — all three were calls to `collect_experiences_gpu(&market_buf, &target_buf, ...)` where `market_buf` and `target_buf` were `CudaSlice<f32>` allocated via `stream.alloc_zeros + memcpy_htod`. The production API changed in |
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jgrusewski
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2de9a58922 |
sp7(wire): T7 polish — fix 2 stale docstrings around compute_adaptive_budgets
Two clarity-only edits surfaced by code review: - M1: compute_adaptive_budgets header docstring claimed floors of "0.05 C51, 0.05 IQN, 0.02 CQL, 0.02 Ens" — stale post-T7 (IQN is now 0.11, others are sentinel-aware bootstrap). Rewritten to reflect the SP7 contract: IQN keeps BASE_IQN=0.11 structural floor; C51/CQL/ENS use sentinel-aware bootstrap. - M2: last_ens_budget_eff docstring misattributed ENS to "SP5 Pearl 2 (flatness-modulated)" — Pearl 2 stopped writing BUDGET_ENS_BASE in T6. Rewritten to state ENS has no active controller driver in SP7; bootstrap-only. Comment-only — zero runtime effect. cargo check clean. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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55b8457fdf |
sp7(wire): launch loss-balance controller + sentinel-aware consumer (atomic)
Atomic per feedback_no_partial_refactor — launch site + consumer floor
change + stale doc are three halves of the same contract:
(a) launch_loss_balance_controller wired into the per-step pipeline
after launch_sp5_pearl_2_budget (FLATNESS_BASE populated) and after
backward (grad_decomp pinned slots populated).
(b) compute_adaptive_budgets replaces hard floors (0.02/0.05) with
sentinel-aware bootstrap. The controller may now drive budgets near
zero when the structural target says so. IQN keeps BASE_IQN=0.11
structural floor (reference, can't be 0).
(c) All 4 stale "B4/G5" budget-eff docstrings rewritten to reflect
actual ownership: last_iqn_budget_eff (Pearl 2 flatness),
last_cql_budget_eff (SP7 controller), last_c51_budget_eff (SP7
controller), last_ens_budget_eff (Pearl 2 flatness +
sentinel-aware bootstrap). The previous claims (e.g.,
"0.10×(1−regime)×health") were never implemented; per
feedback_trust_code_not_docs, code wins over docs.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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d704ffd1bc |
docs(dqn): T6 polish — fix 4 stale Pearl 2 prose references in gpu_dqn_trainer.rs
Four comment/docstring sites still described the pre-SP7 Pearl 2 as writing "20 floats / 5 outputs / c51/cql/ens" after the T6 kernel- signature shrink. Updated to reflect the current 6-arg kernel writing 8 floats (IQN + flatness only) into scratch[115..119, 127..131). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |
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jgrusewski
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805a7429f4 |
sp7(pearl_2): contract change — drop CQL/C51/ENS args (atomic)
Kernel signature reduced from 9 to 6 args; pearl_2_budget_update now writes only budget_iqn[4] and flatness[4]. Launcher migrated atomically: arg list shrinks, apply_pearls smoothing loop shrinks from 5 slot-blocks to 2. SCRATCH_PEARL_2_C51, SCRATCH_PEARL_2_CQL, SCRATCH_PEARL_2_ENS deleted as orphan constants per feedback_wire_everything_up. The corresponding producer scratch slots (111..115, 119..127) become reserved-for-future inside the buffer. CQL/C51/ENS budget ownership now lives in the SP7 loss-balance controller (loaded in T5; wired in T7). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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40871595e8 |
sp7(trainer): T5 polish — rename cql_dev → cql_sx_dev + base_wiener annotation
Two clarity-only edits surfaced by code review: - Rename `cql_dev` → `cql_sx_dev` in `launch_loss_balance_controller`. The launcher uses `grad_decomp_result_dev_ptr + 6 * f32_size` which is the cql_sx (post-budget) slot, not cql (pre-budget at offset 3). The variable name now reflects that. - Add `// 213` inline annotation on `base_wiener_offset` to match the pattern used by all four sibling launchers (lines 11062, 11194, 11303). No semantic impact — pointer arithmetic and parameter order unchanged. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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ab6fbcb668 |
sp7(trainer): load loss-balance controller kernel + launcher fn
LOSS_BALANCE_CONTROLLER_CUBIN static, kernel slot in GpuDqnTrainer, 6 SCRATCH_LB_* index constants (218..242), pub(crate) launch_loss_balance_controller that runs the producer + 24 apply_pearls_ad smoothing launches. SP5_SCRATCH_TOTAL bumped 218→242 with updated docblock and allocation comment to match the 24 new slots. Component pointers into grad_decomp_result_pinned: IQN at offset 0, CQL_SX at offset 6, C51 at offset 9 (3-float layout per launch_grad_decomp docstring). Producer-only — call site in training_loop.rs lands at T7 atomically with the consumer floor change and stale-doc deletion per feedback_no_partial_refactor. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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8e4d5cb45b |
sp7(build): compile loss_balance_controller_kernel cubin
Adds the kernel to the build.rs manifest after pearl_1_ext_num_atoms_kernel and before the SP5 Layer D producers (matching the chronological SP5/SP7 producer ordering). nvcc-compiled cubin lands under $OUT_DIR/loss_balance_controller_kernel.cubin and is loaded by gpu_dqn_trainer.rs in T5. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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21059320e2 |
sp7(cuda): T3 polish — comment-only clarifications
Three comment-only edits surfaced by code review: - M1: Annotate `tid >= 8` guard with `// 8 = 2 heads × 4 branches`. - M2: Header pseudocode `actual_ratio = h_norm / iqn_norm` clarified — the implementation correctly omits the inline `fmaxf` because the outer guard already enforces `iqn_n >= EPS_DIV`. Comment now states the invariant explicitly. - M3: Header "No atomicAdd" line now cites `feedback_no_atomicadd` for consistency with sibling pearl kernels. Comment-only — zero runtime effect. cargo check clean. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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63226f17cb |
sp7(cuda): loss-balance controller kernel (producer-only)
Single-block 8-thread kernel: 2 heads (CQL, C51) × 4 branches. Reads 3-float views into grad_decomp_result_pinned for IQN/CQL_SX/C51, plus FLATNESS_BASE for the per-branch target modulator. Writes new budgets + raw Wiener observations (diff² and sample²) to producer scratch. Per-branch flatness-modulated target ratio (CQL → ANCHOR×(1-flatness), C51 → ANCHOR×flatness). Wiener-optimal α from per-branch EMA state slots, clamped to [1e-4, 0.5]. Cold-start seeds at consumer-side bootstrap (0.02 CQL, 0.05 C51) on first observation; sentinel-aware. Producer-only commit; build.rs entry, kernel slot, launch site land in subsequent tasks. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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60804788eb |
sp7(state): T2 polish — descriptions reflect current state vs future T6/T7
Rewrite the three sp5_budget_c51/cql/ens registry descriptions to be
accurate at HEAD
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jgrusewski
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aa28540175 |
sp7(state): register loss-balance controller state slots + fix stale doc
4 new ResetEntries × 4 slots each cover ISV[297..313). Sentinel 0 triggers Pearl A first-observation bootstrap on fold boundary, matching the existing Pearl 2/3/4/5/6/8 pattern. Also: corrected the stale sp5_budget_cql description claiming a non-existent "regime_stability allocator" (per feedback_trust_code_not_docs); clarified sp5_budget_c51 / sp5_budget_ens to reflect SP7 ownership. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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6e7690d82d |
sp7(isv): T1 polish — alignment + audit-doc stub softening
Minor item 1: Remove extra column-alignment spaces from the 4 SP7 constants (LB_DIFF_VAR_CQL_BASE, LB_SAMPLE_VAR_CQL_BASE, LB_DIFF_VAR_C51_BASE, LB_SAMPLE_VAR_C51_BASE) so they match the no-alignment style of surrounding SP5 constants (BUDGET_C51_BASE etc.). Constant values (297, 301, 305, 309) and inline comments are unchanged. Minor item 2: Soften the Fix 31 T7 stub in dqn-wire-up-audit.md from "sentinel-aware consumer" to "sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7)" so the audit entry does not forward-reference specific constant names before they land. Cargo check: clean (zero warnings, zero errors). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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9822b2eea7 |
sp7(isv): refresh SP5_PRODUCER_COUNT docstring for T1 slot growth
Update stale (118) → 137 unique-slot count and [174..294) = 120 → [174..313) = 139 range in the SP5_PRODUCER_COUNT docstring. Update inline comment unique-slot count 121 → 137 with SP7 T1 breakdown entry. Append SP7 Task 1 history paragraph matching the established Layer D D3 paragraph style. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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a92abedbae |
sp7(isv): allocate 16 ISV slots for loss-balance controller state
LB_DIFF_VAR_CQL_BASE=297, LB_SAMPLE_VAR_CQL_BASE=301, LB_DIFF_VAR_C51_BASE=305, LB_SAMPLE_VAR_C51_BASE=309. Bumps SP5_SLOT_END 297 → 313 and SP5_PRODUCER_COUNT 123 → 139. Helper fns mirror the existing budget_*/flatness/q_var_per_branch pattern. Layout fingerprint extended. slot_layout_no_overlaps_and_total_correct asserts the new total. Audit doc Fix 31 stub added; will be extended commit-by-commit through Tasks 2-9 of the SP7 plan. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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2fb7d7f57c |
fix(data): Fix 30 Stale-B — backtest_plan_kernel raw_close from prices_buf (post-MappedF32Buffer migration)
Closes Fix 29 audit row #13 — the last ⚠ Stale row from the Bug-1 contract drift triage. Pre-fix, `backtest_plan_state_isv` extracted raw_close as `features[bar*feat_dim + 0]`. Post Bug-1 (commit `5a5dd0fed`) `features[..+0]` is z-normed log-return, NOT raw_close. The resulting `equity = cash + position*raw_close` and `unrealized = position*(raw_close - entry_price)` formulas mixed z-normed-log-return as a dollar price, corrupting val plan_isv slots [PNL_VS_TARGET] (slot 1) and [PNL_VS_STOP] (slot 2). Other plan_isv slots (progress, conviction, drift, regime, remaining) don't depend on raw_close and were correct pre-fix. Resolution: route raw_close from the upload-once `prices` buffer (layout `[n*max_len*4]` raw OHLC). Close is at column index 3 — the same index `backtest_env_kernel.cu` already reads from for portfolio mark-to-market (line 64 of that kernel; OHLC layout is canonical across the val backtest path). Reading from `prices` aligns the val plan_isv path with env_step's source-of-truth, eliminating the mixed-units pathology end-to-end. Sites fixed: - crates/ml/src/cuda_pipeline/backtest_plan_kernel.cu:74-100 Kernel signature: `const float* features` and `int feat_dim` parameters dropped, replaced by `const float* prices` (the [n*max_len*4] raw OHLC buffer). Raw_close read becomes `prices[(w*max_len + current_step)*4 + 3]`. Multi-line comment block documents the Bug-1 origin and the env_step parity reference. The `bool have_close` / `prices != nullptr` guard semantics preserved — callers without OHLC data fall back to `unrealized = 0` exactly as pre-fix. - crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs:~1956 Single launcher (`evaluate_dqn_graphed` chunk loop, the only invocation site of `plan_state_isv_kernel`) updated to pass `&self.prices_buf.dev_ptr` instead of `&self.features_buf.dev_ptr` and to drop the now-unused `feat_dim_i32` local + `.arg()` call. Inline comment explains the Bug-1 origin. - docs/dqn-wire-up-audit.md Stale-B row appended to Fix 30's table. The standalone Stale-B DEFERRED paragraph at the bottom replaced by the commit summary + the Fix 30 closure note (all 4 ⚠ Stale and 1 ❓ Ambiguous rows from Fix 29's deferred follow-ups now resolved). Migration scope per `feedback_no_partial_refactor`: kernel signature changed → every consumer migrates in the same commit. Single launcher; verified via `grep -rn backtest_plan_state_isv` (only the kernel definition + the gpu_backtest_evaluator launcher + load site appear). Verification: - SQLX_OFFLINE=true cargo check -p ml --offline (43.68s) clean. - SQLX_OFFLINE=true cargo build -p ml --release --offline --features cuda (1m 30s) clean; cubin recompiled via nvcc. - Pre-commit DtoD-via-pinned guard passes (the prereq commit `4d966e62f` migrated `gpu_backtest_evaluator.rs`'s buffers to MappedF32Buffer, eliminating the 5 `_via_pinned` callers that had blocked any prior staging of this file). Refs Fix 29 row #13. `feedback_no_partial_refactor` (single launcher migrated alongside kernel signature change in one commit), `feedback_no_functionality_removal` (PNL_VS_TARGET / PNL_VS_STOP slots preserved — only their data source corrected; the audit's "drop the slots" alternative explicitly rejected), `feedback_no_hiding` (no fallback to z-normed reads remaining; kernel either gets real raw_close or falls through to `have_close=false` with `unrealized=0`, identical to pre-fix smoke-test semantics where prices==NULL), `feedback_no_cpu_compute_strict` n/a (zero new host-side compute), `feedback_no_htod_htoh_only_mapped_pinned` already satisfied (`prices_buf` is `MappedF32Buffer` post the prereq migration), `feedback_trust_code_not_docs` (the kernel comment said "raw_close from features buffer" for months — accurate-when-written pre-Bug-1, stale-after-Bug-1; verify-against-code disambiguates). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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4d966e62f4 |
refactor(cuda): migrate gpu_backtest_evaluator buffers to MappedF32Buffer (Fix 30 Stale-B prereq)
Prerequisite for the deferred Fix 30 Stale-B kernel-side fix
(`backtest_plan_kernel.cu` raw_close source). The DtoD-via-pinned
pre-commit guard (`scripts/pre-commit-hook.sh::check_no_dtod_via_pinned`,
commit `5275932f4`) blocks any commit that stages `gpu_backtest_evaluator.rs`
against the file's 5 pre-existing `clone_to_device_*_via_pinned` callers
that landed before the guard. Stale-B has to stage this file (to thread
`prices_buf` into the `backtest_plan_state_isv` launcher), so the
migration must land first as its own atomic commit per
`feedback_no_partial_refactor`.
Migration scope. Single file, four buffer fields:
- prices_buf CudaSlice<f32> → MappedF32Buffer [n*max_len*4]
- features_buf CudaSlice<f32> → MappedF32Buffer [n*max_len*feat_dim]
- portfolio_buf CudaSlice<f32> → MappedF32Buffer [n*8] (kernel-mutated)
- window_lens_buf CudaSlice<i32> → MappedI32Buffer [n]
Init sites (lines ~651-664 post-edit). 4 `clone_to_device_*_via_pinned`
calls replaced with `MappedF32Buffer::new(host.len())` +
`write_from_slice(host)`. No memcpy_dtod_async + stream.synchronize()
pair at construction — mapped-pinned coherence makes the kernel see
host writes after the next stream-sync barrier.
Reset site (`reset_evaluation_state`, line ~1485 post-edit). In-place
`self.portfolio_buf.write_from_slice(&portfolio_init)` replaces the
prior buffer-replacement
`self.portfolio_buf = clone_to_device_f32_via_pinned(...)`. No alloc
churn per epoch; the device pointer stays stable across resets which
matches MappedF32Buffer's intended use.
Consumer sites (17 kernel arg passes). `arg(&self.X_buf)` →
`arg(&self.X_buf.dev_ptr)` so the launcher receives the device pointer
the kernel expects. Sites: launch_gather (×2), launch_gather_chunk,
launch_env_step, env_batch_kernel chunked path, plan_state_isv kernel,
metrics_kernel. CUdeviceptr (u64) is passed by reference exactly as
metrics_dev_ptr already does at the metrics launch site (~line 2497).
Kernel-mutated MappedF32Buffer precedent. portfolio_buf is mutated by
the env_step kernel every step. The same file's `plan_diag_buf` (a
MappedF32Buffer) is also kernel-written via dev_ptr (lines ~1230-1256)
and host-read via host_ptr — direct precedent. The IQN τ migration
(commit `facbf76eb`) confirms cuMemHostAlloc DEVICEMAP for kernel
reads. The mapped_pinned.rs module docstring states explicitly:
"Kernels write through dev_ptr (with __threadfence_system())".
What this change touches:
- crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs
Field types (lines 299-321), init block (lines 641-665), reset
(lines 1462-1471), 17 kernel arg passes across 6 launchers.
- docs/dqn-wire-up-audit.md
Fix 30 Stale-B paragraph extended with the prereq commit summary.
Stale-B itself remains DEFERRED (kernel-side fix lands next).
Verification:
- SQLX_OFFLINE=true cargo check -p ml --offline (44.38s) clean.
- SQLX_OFFLINE=true cargo build -p ml --release --offline
--features cuda (53.78s) clean.
- grep -n "clone_to_device_.*_via_pinned\|upload_.*_via_pinned"
crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs returns
zero hits.
- grep -n "self\.\(prices\|features\|window_lens\|portfolio\)_buf"
shows every kernel-arg site followed by `.dev_ptr`. The only
non-`.dev_ptr` references are the field declarations, the
constructor moves into `Self { ... }`, and the
`write_from_slice` calls in `reset_evaluation_state`.
- Pre-commit DtoD-via-pinned guard now passes on staging this file.
Eliminates the last 5 `_via_pinned` callers in
`gpu_backtest_evaluator.rs`. Per
`feedback_no_htod_htoh_only_mapped_pinned`, `feedback_no_partial_refactor`
(every consumer of a field-type change migrates in one commit),
`feedback_no_hiding` (no `--no-verify`; the migration IS the fix the
guard is asking for).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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c4aa71b9df |
cleanup(cuda): Fix 30 Ambiguous-A — delete orphan phantom_liquidity_gbm
Closes Fix 29 audit row #18. The synthetic-data overlay kernel `phantom_liquidity_gbm` in `dqn_utility_kernels.cu:1050-1096` was flagged ❓ Ambiguous because its writer wrote `log_ret` to `market_features[bar*market_dim + 0]` and `+3` — the WRITER's downstream consumer contract was unverifiable post Bug 1 (commit `5a5dd0fed`) which redefined feature index 0 from raw log-return to z-normed log-return. Investigation result: zero callers in the entire codebase. The audit grep `grep -rn "phantom_liquidity_gbm" crates/ml/src/ services/ crates/ bin/` returns ONLY the kernel definition itself — no `load_function`, no `launch_builder`, no Rust-side launcher. The kernel has been compiled but never invoked since at least early 2026. Resolution: delete the kernel definition and replace with an explanatory comment block. Per `feedback_no_hiding` an orphan kernel with an ambiguous post-Bug-1 contract is exactly the failure mode the rule warns against — a future re-wirer would have written synthetic z-normed log-returns into a slot the production pipeline expects raw log-returns at, re-introducing the very Bug-1 drift the audit was triaging. Per `feedback_wire_everything_up` a kernel that compiles but is unconsumed is either wired in the same commit or deleted; this kernel was never wired since its writer existed. The replacement comment block (23 lines) documents the design intent (GBM-based synthetic-data augmentation) so any future re-introduction has the spec available, plus the re-introduction conditions: caller wiring must land in the same commit, and the writer/consumer contract for `market_features[..+0]` (z-normed vs raw log-return) must be explicit at the kernel boundary. What this change touches: - crates/ml/src/cuda_pipeline/dqn_utility_kernels.cu:1037-1096 47-line kernel definition + ══ comment header deleted; 23-line DELETED notice replaces it. Net -24 lines. - docs/dqn-wire-up-audit.md Fix 30 Ambiguous-A row appended with the dead-code-deleted resolution. Stale-B deferral note also added (separate paragraph) documenting the pre-existing `_via_pinned` guard block requires a dedicated `gpu_backtest_evaluator.rs` migration commit before the Stale-B kernel-side fix can land. Verification: - SQLX_OFFLINE=true cargo build -p ml --release --offline --features cuda (1m 30s) clean; cubin recompiled via nvcc. - Pre-commit guards pass. - Final grep for `phantom_liquidity_gbm` returns only the comment block in the kernel file. Refs Fix 29 row #18 deferred follow-up. `feedback_no_hiding` (delete orphans, do not leave them as ambiguous landmines), `feedback_wire_everything_up` (every module/feature/kernel built must be wired to a production path or removed), `feedback_no_functionality_removal` does NOT apply: a kernel with zero callers is not a functional feature, and the audit doc retains the design intent so any future re-introduction can rebuild the mechanism with the correct post-Bug-1 contract. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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7e54dedd22 |
fix(data): Fix 30 Stale-C — scripted_policy raw_close from fxcache targets
Closes Fix 29 audit row #12. Pre-fix, `scripted_policy_select` read `state[MARKET_START]` as `close_now` and computed `recent_ret = (close_now - prev_close) / prev_close`. Post Bug-1 (commit `5a5dd0fed`) `state[MARKET_START]` is z-normed log-return at the WRITER, not raw_close, so the formula mixed two unrelated signals (z-normed return vs dollar price). The seed-phase MOMENTUM / MEAN_REV / VWAP_DEV branches degenerated to noise-floor below the ±0.0001f cutoffs, leaving 60% of seed-phase episodes (the non-UNIFORM 20%+20%+20%) effectively in DIR_HOLD instead of expressing the intended scripted-policy diversity. Resolution: route raw_close from the same fxcache target buffer the env_step kernel reads from. Kernel signature gains `const float* targets`, `const int* episode_starts`, `int t`, `int total_bars` parameters. Per-thread `bar_idx = episode_starts[i] + t` (matching `experience_kernels.cu:1769`'s indexing convention), then `close_now = targets[bar_idx*6 + TARGET_RAW_CLOSE]`. Bounds-clamp to `[0, total_bars-1]` mirrors env_step's out-of-bounds early-return. Sites fixed: - crates/ml/src/cuda_pipeline/scripted_policy_kernel.cu Kernel signature extended; close_now read source switched; `FXCACHE_TARGET_STRIDE` / `FXCACHE_TARGET_RAW_CLOSE` mirrored as #defines (kernels can't import Rust constants; co-locating the literals in a comment-block keeps the cross-language contract visible at the call site for any future TARGET_DIM bump). The previous `bar_idx` parameter renamed `t`; the LCG seed now mixes per-thread `bar_idx = episode_starts[i] + t` instead of the per-step `t` — stronger entropy across episodes, no behavioural regression (UNIFORM policy still produces 4-direction uniform). - crates/ml/src/cuda_pipeline/gpu_experience_collector.rs:~3735 Single launcher updated to pass `&targets_buf.dev_ptr`, `&self.episode_starts_buf`, `t as i32`, and `total_bars` (already in scope from line 3301). Inline comment explains Bug-1 origin. Migration scope per `feedback_no_partial_refactor`: single launcher; no other call sites. Verified via `grep -rn scripted_policy_select crates/ml/src/`. NO new `PS_*` slot or `PORTFOLIO_STRIDE` bump required — the targets buffer is the canonical raw_close source and routing it directly avoids cascading through the ~12 PORTFOLIO_STRIDE consumers (kelly_cap_update_kernel, trade_stats_kernel, gpu_experience_collector, ml-core mirror, etc.). This is the "route raw_close directly" branch of the audit's contract decision; the alternative "add an extra state slot" branch was explicitly rejected as cascade-heavy for a seed-phase-only signal. Verification: - SQLX_OFFLINE=true cargo check -p ml --offline (43.87s) clean. - SQLX_OFFLINE=true cargo build -p ml --release --offline --features cuda (1m 30s) clean; cubin recompiled via nvcc. - No host-side compute added; all reads on GPU. - `targets_buf` is mapped pinned by upstream caller (per `feedback_no_htod_htoh_only_mapped_pinned`). Refs Fix 29 row #12. `feedback_no_partial_refactor` (single launcher migrated in same commit), `feedback_no_functionality_removal` (`recent_ret` signal preserved — only its data source is fixed; the CUSUM-substitution alternative path explicitly rejected because the recent_ret signal IS the scripted-policy contract, not an implementation accident), `feedback_no_hiding` (no fallback to z-normed-log-return reads; kernel either gets real raw_close or clamps to total_bars-1 boundary), `feedback_no_cpu_compute_strict` n/a (zero new host-side compute), `feedback_trust_code_not_docs` (the kernel comment said `state[MARKET_START + 0] = close_now` for months — accurate-when-written, stale-after-Bug-1; verify-against-code disambiguates). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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73e3ea87a4 |
fix(data): Fix 30 Stale-A — host-side target[0] → TARGET_RAW_CLOSE swap
Closes Fix 29 audit rows #14 and #15 (Bug-1 contract drift in val/HPO close-price extraction). Both sites read `target[0]` thinking it is raw_close, but post Bug-1 (commit `5a5dd0fed`) `target[0]` is preproc_close (z-normed log-return). The `fv[3]` fallback path is unreachable on every production code path because `set_val_data_from_slices` (in `dqn/trainer/mod.rs:1704`) always yields `Vec<f64>` of length 6 from `[f64; 6]` slices post `TARGET_DIM=6` bump (commit `063fd2716`), so `target.len() >= 2` is an always-true guard. Per `feedback_no_hiding` the dead fallback is removed in the same edit rather than left as a silent wrong-units path. Sites fixed: - crates/ml/src/trainers/dqn/trainer/metrics.rs:576 (val window_prices for GpuBacktestEvaluator) - crates/ml/src/hyperopt/adapters/dqn.rs:2492 (HPO adapter val_close_prices for window-aggregated backtest) Both now read `target[TARGET_RAW_CLOSE]` (col 2). Both import the named constant from `crate::fxcache` so a future column rename moves the call site with the writer (Fix 27 prevention pattern). Verification: - SQLX_OFFLINE=true cargo check -p ml --offline (8.03s) clean. - No GPU code changed; cubin not affected. Affects val Sharpe annualization + window equity curves on training metrics; affects HPO val score on every trial. Pre-fix would yield "prices" of magnitude ~stddev(log_return) (~7e-5 for ES 1-min) feeding into PnL math that expects dollar prices, producing degenerate backtest output. Post-fix prices are real raw_close values. References Fix 27 Bug B (host-side Welford) — same kind of bug surfaced at val/HPO consumer rather than training Welford. References feedback_no_hiding (delete unreachable fallbacks rather than leaving silent wrong-units fall-through), feedback_no_partial_refactor (both consumers of the same (fv, target) tuple convention migrate together), feedback_trust_code_not_docs (the `target.len() >= 2` guard read as defensive but was masking a contract drift). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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ab378327ec |
fix(data): vol_normalizer double-normalization removed (post-Bug-1)
The kernel block at experience_kernels.cu:698-704 divided market_features[0..3] by vol_normalizer at runtime — designed for the pre-Bug-1 pipeline where features arrived as RAW log returns (~±0.001). After Bug 1 fix (commit |
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jgrusewski
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2683d46378 |
diag(dqn): DIAG_AUX_LABEL one-shot — pin source of label_scale=5481 leak
Production training run train-multi-seed-bn42w showed label_scale=5481
(raw_close magnitude) at epoch 4 vs smoke's ~25 at the same commit
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jgrusewski
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29b1d34c6d |
fix(data): target stride/column drift — host + GPU consumer cleanup
Two latent bugs converged in the cancelled 50-epoch run (train-multi-seed-p5qzw at |
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jgrusewski
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2e9e276a0c |
fix(sp5): Layer D Task D4 — atomic 3-kernel wiring of D1+D2+D3
Wires the 3 Layer D producer kernels into the production hot path AND removes the host-side EMA arithmetic for sharpe/max_dd/low_dd_ratio in the same commit per feedback_no_partial_refactor + feedback_no_cpu_compute_strict. Sites migrated (host → GPU kernel + ISV slot): training_sharpe_ema → launch_training_metrics_ema → ISV[294] max_dd_ema → launch_training_metrics_ema → ISV[295] low_dd_ratio → launch_training_metrics_ema → ISV[296] LearningHealth.compose → launch_health_composition → ISV[290..294) trade-PnL aggregation → launch_sp5_pnl_aggregation → ISV[286..290) Behavior preserved within float precision: every EMA β decay constant, warmup/clamp wrapper, and downstream consumer formula migrates verbatim. The kernels reproduce the host computations bit-for-bit (verified by the GPU-gated unit tests landed in D1/D2/D3 at |
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jgrusewski
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66f7e64d13 |
fix(sp5): D1 rewrite — match production per-bar semantics, fix D4 blocker
The original D1 kernel (commit
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jgrusewski
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f42b5fff8d |
feat(sp5): Layer D Task D3 — Training metrics EMA kernel (additive)
Third of 3 Layer D producer kernels. Replaces host-side training_sharpe_ema, max_dd_ema, low_dd_ratio updates (host-side EMAs in training_loop.rs) with a fused GPU kernel chained through apply_pearls_ad_kernel. Per feedback_no_cpu_compute_strict. Note: agent investigated training_loop.rs and found the third metric is low_dd_ratio (not gamma_blend as the original plan brief named). The authored kernel reproduces the actual host-side EMA triplet present in the codebase. Additive only — no consumer wiring, no behavior change. The kernel + launcher are loaded into GpuDqnTrainer and the slots are reserved on the ISV bus, but the host-side updates continue to run unchanged. D4 (atomic Layer D commit) wires this and D1+D2 to call sites in the same atomic refactor per feedback_no_partial_refactor. Also note: training_loop.rs gains two state-reset-registry dispatch arms (sp5_health_composition for D2 + sp5_training_metrics_ema for D3) — registry plumbing required by the new entries, NOT consumer wiring of the kernels themselves; same pattern as SP5 Layer A bug-fix #281. What this lands: - training_metrics_ema_kernel.cu (single-block 3-thread fused EMA) - Rust launcher launch_training_metrics_ema() - 3 new ISV slots (TRAINING_SHARPE_EMA_INDEX..LOW_DD_RATIO_INDEX, 294..297) - ISV_TOTAL_DIM 294 → 297, SP5_PRODUCER_COUNT 120 → 123 (linear span) - LAYOUT_FINGERPRINT_SEED bump (auto via slot string) - StateResetRegistry entries for D2 (sp5_health_composition) + D3 (sp5_training_metrics_ema) with reset_named_state dispatch arms - build.rs cubin registration - GPU-gated unit test in sp5_producer_unit_tests.rs (analytical EMA) - SP5 contiguity slot test training_metrics_ema_slots_contiguous_and_above_health_block - Audit doc append Formula fidelity: kernel reproduces the host-side EMA update for sharpe/max_dd/low_dd_ratio bit-for-bit within float precision. β decay constants and any warmup/clamp logic migrate as Invariant 1 anchors with no algorithmic change. Verified by unit test asserting kernel output matches an analytical EMA sequence within 1e-6 rel-err. Tests: cargo check + cargo build clean; ISV slot + state_reset_registry unit tests pass (8/8 incl. new contiguity check); GPU correctness test fires on next L40S smoke. Refs: SP5 plan §D Task D3, builds on D1 ( |
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jgrusewski
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e49756ac90 |
feat(sp5): Layer D Task D2 — Health composition kernel (additive)
Second of 3 Layer D producer kernels. Replaces multi-step host arithmetic
in LearningHealth composition (q_gap_ema + q_var_ema + grad_norm_ema →
composed health score) with a fused GPU kernel chained through
apply_pearls_ad_kernel. Per feedback_no_cpu_compute_strict.
Additive only — no consumer wiring, no behavior change. The kernel +
launcher are loaded into GpuDqnTrainer and the slots are reserved on the
ISV bus, but the host-side composition continues to run unchanged. D4
(atomic Layer D commit) wires this and D1+D3 to call sites in the same
atomic refactor per feedback_no_partial_refactor.
What this lands:
- health_composition_kernel.cu (single-block fused composition)
- Rust launcher launch_health_composition()
- 4 new ISV slots (HEALTH_SCORE_INDEX..GRAD_NORM_NORM_INDEX, slots 290..294)
- ISV_TOTAL_DIM 290 → 294, SP5_PRODUCER_COUNT 116 → 120 (linear span)
- LAYOUT_FINGERPRINT_SEED bump (auto via slot string)
- StateResetRegistry entries (sentinel 0.0; per-fold reset enabled)
- build.rs cubin registration
- GPU-gated unit test in sp5_producer_unit_tests.rs (formula fidelity)
- Audit doc append
Formula fidelity: kernel reproduces the host-side LearningHealth::compose
(or equivalent) computation bit-for-bit within float precision. Migration
is structural only — no algorithmic change. Verified by unit test
asserting kernel output matches a Rust copy of the host formula within
1e-6 rel-err.
Tests: cargo check + cargo build clean; ISV slot + state_reset_registry
unit tests pass; GPU correctness test fires on next L40S smoke.
Refs: SP5 plan §D Task D2, builds on D1 (
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jgrusewski
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5ee795f14f |
feat(sp5): Layer D Task D1 — PnL aggregation kernel (additive)
First of 3 Layer D producer kernels. Replaces host-side trade-PnL
aggregation loop in training_loop.rs with a GPU kernel chained through
apply_pearls_ad_kernel for smoothing. Per feedback_no_cpu_compute_strict.
Additive only — no consumer wiring, no behavior change. The kernel +
launcher are loaded into GpuDqnTrainer and the slots are reserved on the
ISV bus, but the host-side aggregation continues to run unchanged. D4
(atomic Layer D commit) wires this and the other two D2/D3 kernels to
call sites in the same atomic refactor per feedback_no_partial_refactor.
What this lands:
- pnl_aggregation_kernel.cu (single-block tree-reduce, no atomicAdd)
- Rust launcher launch_sp5_pnl_aggregation()
- 4 new ISV slots (PNL_TOTAL_INDEX..PNL_MAX_DD_INDEX, slots 286..290)
- ISV_TOTAL_DIM 286 → 290; SP5_PRODUCER_COUNT semantics formalised as
wiener-buffer linear-span (110 → 116; the unique-slot count diverged
from the linear span at D1 — pre-D1 they coincided by accident at the
Pearl 6 carve-out's introduction)
- LAYOUT_FINGERPRINT_FRAGMENT extended with PNL_* entries
- StateResetRegistry sp5_pnl_aggregation entry + dispatch arm
(sentinel 0.0; fold-reset; PnL is NOT cross-fold persistent unlike
Pearl 6 Kelly stats, so it takes the standard sentinel-bootstrap
path per pearl_first_observation_bootstrap)
- build.rs cubin registration
- GPU-gated unit test pnl_aggregation_kernel_correctness with
analytical ground truth (no CPU reference per
feedback_no_cpu_test_fallbacks)
- Audit doc append documenting D1 + the SP5_PRODUCER_COUNT semantic
clarification
Tests: cargo check + cargo build --release --features cuda clean;
ISV slot + state_reset_registry unit tests 6/6 pass (incl new
pnl_aggregation_slots_contiguous_and_above_kelly_block); GPU
correctness test fires on next L40S smoke alongside existing 17 SP5
producer unit tests.
Refs: SP5 plan §D Task D1, validated SP5 Layer A/B at
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jgrusewski
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5845e44031 |
fix(data): DBN spread-instrument filter — root cause of Bug 2 contamination
Direct inspection of ES.FUT_2024-Q1.dbn.zst (databento python client, offline
kubectl-cp from PVC) pinpoints the source of the 8,799 corrupt bars that
sanitize_bars (Fix 25) caught at the bar-level gate.
Q1 file content:
Outrights (correct): ESH4/ESM4/ESU4/ESZ4/ESH5 — 43,353 records (76.87%)
price range $5,063–$5,478
Spreads (poison): ESH4-ESM4/ESM4-ESU4/... — 13,048 records (23.13%)
price range $47.30–$219.70
Calendar spreads trade at the price DIFFERENCE between adjacent contracts
(~$60-150 cost-of-carry roll basis). Databento's stype_in=parent resolution
for ES.FUT returns BOTH outrights AND every spread combination in the same
DBN stream. The legacy decoder keyed only by ts_event + dedup-by-volume;
during low-volume overnight windows + active rollover periods, spread bars
beat the outright on volume and survived the dedup. 780 spread bars
survived in Q1 alone; ~8,800 across 2024-2026.
Fix: build dbn::TsSymbolMap from metadata once, resolve each record's
instrument_id → symbol, skip any symbol containing `-` (spread separator).
Same-ts dedup-by-volume continues to handle legitimate front/back-month
overlap among outrights.
Adds `time = "0.3"` to ml/Cargo.toml (dbn::TsSymbolMap uses time::Date).
Why complementary to the Fix 25 sanitize_bars gate:
- Spread filter (this commit) catches the cause precisely by symbol pattern,
but only for instruments where parent-symbol resolution is the source.
- sanitize_bars catches the symptom universally by close-ratio bound, but
can't distinguish a low-basis spread from a fast-moving outright in
extreme cases.
Both layers active: spread filter dispatches at parser level, sanitize as
defense-in-depth backstop for unknown future contamination shapes.
Validation: `cargo check -p ml --example train_baseline_rl` clean.
Refs: Bug 2 chain (#191, #194, label_scale=5443 leaks), today's
sanitize_bars find (Fix 25). Closes the contamination-source investigation.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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8434737a69 |
fix(data): structural defense at data-loading boundary — 5 layers
Stops chasing one-off corruption bugs. Three+ historical fixes patched specific writers (#191 fxcache column-0, Bug 1 target schema, label_scale=5443 leaks, today's state[0] heavy-tail). Each new corruption shape found the next hole. This installs a structural defense so corruption is REJECTED at the data-loading boundary regardless of source. Five independent layers, each mandatory: 1. Bar-level sanity (baseline_common::sanitize_bars): drop bars with non-positive OHLC, high<low, non-finite values, or close/prev_close outside [0.5, 2.0]. Catches DBN parse glitches, broker tick errors, near-zero-open bars at source. 2. safe_log_return result clamp (extraction.rs:1246): ratio.ln().clamp(±0.1). Real-market 1-bar log returns rarely exceed ±0.05; ±0.1 traps every legitimate move while rejecting the corruption shape (corrupt bar with bar.open ≈ 0 → ln = -30 → previously normalized to -30000-magnitude state[0] outliers). 3. validate_features pre-norm bound (extraction.rs:538): |val| ≤ 5.0 post-extraction. Pre-norm features come from safe_normalize ([0,1]/[-1,1]), safe_clip (max ±3), or clamped log-returns (±0.1); ±5 catches extractor invariant breaks. 4. NormStats::normalize post-norm clamp (walk_forward.rs:688): ((val - mean) / std).clamp(±20.0). Even if upstream produces outliers, every value uploaded to GPU is bounded. 5. Shared validate_normalized_features gate (walk_forward.rs): single source-of-truth invariant enforced at THREE sites: - fxcache fast path (after discover_and_load) - DBN fallback (after normalize_batch) - precompute writer (before fxcache write — never persist a poisoned cache) Removed: DIAG_BUG2 + DIAG_BUG2_v2 one-shot diagnostics (~125 lines of host-side download + outlier scan in training_loop.rs). Replaced by structural defense — instrumentation isn't needed when corruption can't reach state[0]. FEATURE_SCHEMA_HASH auto-bumps via build.rs FNV-1a hash over SCHEMA_FILES (extraction.rs included). All pre-fix .fxcache files on PVC are invalidated at load time; ensure-fxcache regen produces clean cache with new clamps applied. Why this finally closes the chapter: per-writer fixes are reactive (land after corruption hits prod). Boundary validation is proactive — every future regression to extraction or normalization trips the gate at load, not at epoch 5 of a 50-epoch run. The 5 layers are independent: a bug in any one leaves the others as backstop. Validation: cargo check -p ml --all-targets --offline clean. NormStats unit tests (walk_forward.rs:706+) still pass — clamp + validate are additive; existing test inputs are well within bounds. Refs: SP5 Bug 2 (state[0] std=570 outliers on smoke-test-xb78r), historical #191 #210 #214 #193 #195 chains. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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129b7fd3d0 |
diag(dqn): DIAG_BUG2_v2 — outlier disambiguation H1 vs H2
Augments the existing DIAG_BUG2 one-shot block with two narrower scans
that disambiguate where state[0] heavy-tail (mean=6e-3, std=570,
mean_abs=20 over 3200 samples on smoke-test-xb78r) actually originates.
H1 (data-source corruption): scan features_buf.host_ptr for bars where
|feat[bar*42 + 0]| > 100. host_ptr aliases the same physical memory
the kernel reads (mapped-pinned) — direct read of the data
state_gather sees. Reports up to 10 outlier bar indices + mean/std/
max_abs over up to 2M bars.
H2 (kernel/gather bug): scan gpu_batch.states/next_states (already
DtoH-downloaded) for sample indices where |state[i*sd + 0]| > 100.
Reports up to 10 outlier sample indices.
Verdict line logged: feat-outliers nonempty → H1; state-outliers
nonempty AND feat-outliers empty → H2.
Context: smoke-test-xb78r at HEAD
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jgrusewski
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cba9f25ed9 |
refactor(cuda): features/targets_raw_cuda + 10 cold-path inits → MappedF32Buffer + Bug 2 diag
Two related blocks landing together (Bug 2 diagnostic forces the structural
conversion of touched files; pre-commit guard at
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jgrusewski
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5a5dd0fed1 |
fix(fxcache): target column [0:1] log-return-normalized, not raw price
Bug 1 of the eval-Hold-collapse diagnosis. The fxcache target schema documented in experience_kernels.cu:1556 + cuda_pipeline/mod.rs:508 specifies: target[0] = preproc_close — log-return-normalized close (network input) target[1] = preproc_next — log-return-normalized next close target[2] = raw_close — raw price for portfolio simulation target[3] = raw_next — raw price target[4] = raw_open — raw price target[5] = mid_price_open — MBP-10 midpoint (fallback raw_open) Both writers — `precompute_features.rs:360` and `data_loading.rs:510` — violated the contract by storing raw OHLCV close prices in slots [0:1]. Empirical fxcache inspection: target[0..4] mean=$5967, stddev=$582 (raw prices throughout). The raw-price values at target[0:1] were never directly consumed by training (production aux head reads next_states[i][0] = MARKET feat[0] = log_return), but they corrupted any code reading targets per the documented contract. Both writers now compute (raw_curr / prev_close).ln() and (raw_next / raw_curr).ln() for the preproc columns. FXCACHE_VERSION bumped 7→8 to invalidate existing caches and trigger ensure-fxcache regen. A second bug — eval label_scale=5300 (raw price magnitude) at production binary despite source state[0] tracing back to z-normalized log_return — remains unresolved. Bug 2 instrumentation lands in the next commit; that runtime trace will pin which production-binary code path injects raw_close into state[0] post-gather. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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5275932f4c |
guard+cleanup(cuda): DtoD-via-pinned pre-commit guard + delete orphan HER
Two related changes installing the structural guard against the SP6 Pearl 5 IQN τ failure mode (root cause fixed at |
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jgrusewski
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facbf76eb5 |
fix(sp6): IQN τ buffers — MappedF32Buffer per feedback_no_htod_htoh_only_mapped_pinned
Pearl 5's online_taus/target_taus/cos_features were declared as CudaSlice<f32> (device-only), populated via upload_f32_via_pinned which does a DtoD copy from a separate mapped-pinned staging buffer. The DtoD inside CUDA Graph capture triggers CUDA_ERROR_STREAM_CAPTURE_INVALIDATED and the 'continuing ungraphed' fallback observed in smoke-test-hhr5q. This violates feedback_no_htod_htoh_only_mapped_pinned: the rule is mapped-pinned (cuMemHostAlloc DEVICEMAP) for ALL CPU↔GPU paths. No DtoD copies, no HtoD copies, no exceptions. Fix: convert all 3 buffers (online_taus, target_taus, cos_features) to MappedF32Buffer per-branch [MappedF32Buffer; 4] arrays. Host writes go directly to host_ptr; IQN kernel reads dev_ptr of the same memory — no copy step at all. The mem::swap pattern is replaced with pure selection: activate_branch_taus sets active_branch_idx; kernel launch sites index online_taus_per_branch[active_branch_idx].dev_ptr. Eliminates upload_f32_via_pinned calls for these buffers entirely. Refresh becomes a host write to mapped-pinned host_ptr at fold boundary; subsequent kernel launches see the write through the mapped-pinned coherence guarantee after stream sync. cargo check + cargo build --release + cargo test --lib (sp4 sp5 state_reset_registry: 13/13) all clean. Sanity grep for upload_f32_via_pinned in gpu_iqn_head.rs returns zero. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |
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jgrusewski
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b861567890 |
fix(sp6): clean compile — wire-or-delete all 13 ml + 2 ml-dqn warnings
W1 SEMANTIC: Pearl 2 iqn_branch[b] is now consumed at Pearl 5 per-pass IQN budget. Previous code used iqn_trunk/4 in both parallel + sequential IQN paths, silently averaging Pearl 2's per-branch IQN differentiation. Now: iqn_budget_per_branch = iqn_branch[branch_idx] / 4.0 inside the per-branch loop — sum across 4 branches = iqn_trunk magnitude preserved, per-branch differentiation preserved. iqn_trunk renamed _iqn_trunk in the destructure (still in-scope comments only). W2 DELETE: ATOM_NUM_ATOMS_BASE + NOISY_SIGMA_BASE imports removed from fused_training.rs:44 — consumers are atoms_update_kernel.cu (Layer B) and experience_kernels.cu; imports were speculative additions. W3 DELETE: v_blocks at gpu_iql_trainer.rs:756 — both kernel launches used v_blocks2; v_blocks was stale dead code. W4 DELETE: OrderRouter import from ml-dqn/src/dqn.rs — import only, never used in the file body. W5 DELETE: get_snapshots_for_timestamp import from data_loading.rs — imported but never called; only OFICalculator + get_trades_for_bar used. W6 DELETE: update_target_networks method (42 lines) from ml-dqn/dqn.rs — orphan with zero call sites; real path uses fused CUDA EMA kernel. Cascaded: convergence_half_life import deleted (now unused). W7-W13 FILE-LEVEL #![allow(unsafe_code)]: cublas_algo_deterministic.rs and sp4_wiener_ema.rs — workspace unsafe_code = "warn" fires for every unsafe impl/fn; both files require unsafe for CUDA/cuBLAS interop; pattern matches mapped_pinned.rs, gpu_iqn_head.rs, gpu_weights.rs, etc. W14-W15 VISIBILITY SCOPE: ControllerPrevValues + ControllerFireCounts in trainer/mod.rs changed pub → pub(crate); consumed only within ml. Per feedback_no_hiding: zero #[allow(...)] item-level suppressions added; 2 file-level #![allow(unsafe_code)] follow established crate convention. cargo check (ml + ml-dqn) + cargo build --release + cargo test --lib all CLEAN (0 warnings; 13/13 lib tests pass). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |
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jgrusewski
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8df28b81c8 |
merge: SP6 Pearl 5 — IQN τ per-branch (replaces SP5 broken upload pattern)
Brings in worktree-agent-acd65ada (commit
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jgrusewski
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76d58406bd |
merge: SP6 Pearl 3 — NoisyLinear per-branch σ array
Brings in worktree-agent-a4d8a879 (commit
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jgrusewski
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becd488320 |
merge: SP6 Pearl 2 — SAXPY per-branch loss budgets
Brings in worktree-agent-a284432c (commit
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jgrusewski
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82ca733255 |
fix(sp5): Layer A bug — add 21 reset_named_state dispatch arms
L40S smoke at SP5 Layer B HEAD (
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jgrusewski
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f62860ea82 |
feat(sp6): Pearl 2 — SAXPY per-branch loss budgets (correction-factor pattern)
SP6 sub-project 1 (Pearl 2): converts the 4 SAXPY launchers from a single
scalar budget (mean of 4 ISV branch slots) to per-branch differentiated
scaling via the correction-factor pattern.
Problem: SP5 Layer B read ISV[190..210) per-branch budget slots but
collapsed them to a scalar via sum/4.0, then passed the single scalar to
apply_c51_budget_scale / apply_cql_saxpy / apply_iqn_trunk_gradient.
Branch HEAD parameters received the same budget as trunk, defeating
per-branch differentiation.
Fix: compute_adaptive_budgets() now returns ([f32;4], [f32;4], [f32;4],
[f32;4], f32, f32, f32, f32) — four per-branch arrays + four trunk-mean
scalars. The trunk mean (D3 decision) is used for the full-buffer trunk/value
SAXPY call (preserving SP5 Layer B behavior for shared params). Branch HEAD
parameter slices receive a correction sub-launch:
correction = branch_budget[b] / trunk_mean (skip if |correction-1| <= 1e-6)
After both launches, branch HEAD slice is effectively scaled by
branch_budget[b], trunk/value is scaled by trunk_mean. No double-scaling.
New helpers added to GpuDqnTrainer:
apply_c51_budget_scale_branch(branch_idx, correction): scale_f32_ungraphed
on branch-slice [f32 elements], offset via padded_byte_offset.
apply_cql_saxpy_branch(branch_idx, correction): saxpy_f32_aux on
branch-slice of both grad_buf and cql_grad_scratch.
IQN trunk gradient: uses iqn_trunk (mean of 4 branch IQN budgets) — IQN
backward flows through trunk only; per-branch IQN routing is beyond SP6 scope.
HEALTH_DIAG: three new per-epoch info! lines emit per-branch c51/iqn/cql
budget arrays (dir/mag/ord/urg) after the intent_dist line.
State: per-branch budget arrays cached on GpuDqnTrainer
(last_*_budget_per_branch: [f32;4]) and on DqnTrainer
(last_*_budget_per_branch: Option<[f32;4]>) for diagnostics.
docs/isv-slots.md: updated Pearl 2 slot rows to reflect SP6 consumer wiring.
Verification: cargo check + release build clean (13 warnings, pre-existing).
13 sp5+sp4+state_reset_registry lib tests pass. sp5_producer_unit_tests
--no-run clean. Sanity grep for old sum/4.0 averaging pattern: empty.
Files changed (6): gpu_dqn_trainer.rs, fused_training.rs, constructor.rs,
mod.rs, training_loop.rs, docs/isv-slots.md. No Pearl 3 or Pearl 5 files touched.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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jgrusewski
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89fadec24a |
feat(sp6): Pearl 5 — IQN τ per-branch schedule (4 forward passes, ÷4 budget normalization)
GpuIqnHead gains 12 new CudaSlice<f32> buffers (online_taus_branch[4], target_taus_branch[4], cos_features_branch[4]) allocated at construction time via alloc_f32. Each slab is [B,N] for taus and [D,N] for cos_features — same sizes as the existing main buffers. refresh_taus_for_branch(branch_idx, tau5): uploads one branch's 5-quantile τ schedule from ISV[IQN_TAU_BASE + b*5 .. +5] to per-branch slabs with cold-start floor (FIXED_TAUS[q] when ISV slot is zero). No cross-branch averaging. activate_branch_taus(b) / deactivate_branch_taus(b): symmetric mem::swap helpers install/restore one branch's slab into self.online_taus/target_taus/cos_features for a per-branch IQN forward pass. activate→deactivate(b) is its own inverse. fused_training.rs: - Tau refresh block calls refresh_taus_for_branch(b, tau5) for all 4 branches, then refresh_taus_from_isv for the averaged main buffer (CVaR backward compat). - grad_decomp_snapshot_iqn() moved BEFORE the parallel/sequential fork so the snapshot is taken before any of the 4 per-branch apply_iqn_trunk_gradient calls. - Parallel path: 4 sequential IQN passes on iqn_stream; after each pass, event sync to main stream, apply_iqn_trunk_gradient(iqn_budget/4), re-fork so next pass starts after main has consumed d_h_s2_buf. iqn_done_event recorded after all 4 passes. - Sequential path: 4 sequential IQN passes on main stream; apply_iqn_trunk_gradient (iqn_budget/4) inline after each pass while d_h_s2_buf holds that branch's result. - Post-join: single apply_iqn_trunk_gradient removed (now inline); target_ema_update and PER loss cast remain. ÷4 normalization: both apply_iqn_trunk_gradient call sites use iqn_budget_per_branch = iqn_budget / 4.0_f32 so 4 × (budget/4) = budget total — matching SP5 Layer B gradient magnitude contract exactly. docs/isv-slots.md: add SP6 Pearl 5 consumer wiring section under the SP5 table. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |
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jgrusewski
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ed3fa066b9 |
feat(sp6): Pearl 3 — NoisyLinear per-branch σ array
Replace ExperienceCollectorConfig.noise_sigma: f32 with noise_sigma_per_branch: [f32; 4] (branch order: dir/mag/ord/urg). add_advantage_noise kernel (experience_kernels.cu) now takes const float* noise_sigma[4] + b0/b1/b2/b3 branch-size params. Each thread derives its branch_idx from action offset using cumulative branch size offsets; applies that branch's sigma. Sigma=0 fast-exits with no PRNG work. GpuExperienceCollector gains noise_sigma_dev: MappedF32Buffer[4] (mapped-pinned, zero HtoD copy per feedback_no_htod). CPU writes the 4 sigma values via write_from_slice before each kernel launch; kernel reads via dev_ptr. training_loop.rs reads ISV[NOISY_SIGMA_BASE..+4] = ISV[210..214) directly — one slot per branch — instead of averaging all 4 into a scalar. Cold-start floor 0.01 is Invariant 1 (numerical stability). Falls back to [hyperparams.noise_sigma; 4] when fused_ctx unavailable. Default::default() supplies [0.1; 4]. mod.rs test (line 895) uses Default::default() unchanged — no explicit field to update. docs/isv-slots.md updated to reflect SP6 Pearl 3 consumer wired. Files changed: 4 (experience_kernels.cu, gpu_experience_collector.rs, training_loop.rs, docs/isv-slots.md). No Pearl 2 or Pearl 5 files touched. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |
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jgrusewski
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3ad5e011b9 |
fix(sp5): Layer B fix-up — close 3 review findings before Layer C
Comprehensive review of Layer B (commit
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jgrusewski
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99367b9c60 |
feat(sp5): Layer B — atomic consumer migration to ISV-driven adaptive signals
SP5 Layer B: all consumers of ISV slots 174..286 migrated in one atomic
commit per feedback_no_partial_refactor.
Pearl 1 (C51 atom span, done prior session):
atoms_update_kernel.cu: reads v_center/v_half from ISV[174+b]/ISV[178+b]
Pearl 1-ext (per-branch num_atoms):
atoms_update_kernel.cu: reads ISV[274+b], rounds to valid {16,32,64},
uses eff_na for softmax/cumsum; output stride still global num_atoms
Pearl 2 (per-branch loss budgets):
fused_training.rs: compute_adaptive_budgets() reads ISV[190..194/198/202]
averaged over 4 branches; Invariant-1 floors 0.05/0.05/0.02/0.02
Pearl 3 (per-branch NoisyNet sigma):
training_loop.rs: ExperienceCollectorConfig.noise_sigma reads
mean(ISV[210..214]) with 0.01 floor; falls back to hyperparams.noise_sigma
when fused_ctx absent
Pearl 4 (per-group Adam beta1/beta2/epsilon):
gpu_dqn_trainer.rs: per-group reads inside launch_adam_update loop via
ISV[226+g], ISV[234+g], ISV[242+g]
gpu_iqn_head.rs: iqn_beta1/beta2/epsilon threaded into
execute_training_pipeline + train_iqn_step_gpu
gpu_attention.rs: attn_beta1/beta2/epsilon threaded into adam_step
gpu_tlob.rs: same as attention (shares ParamGroup::Attn=6)
fused_training.rs: 4 call sites read ISV[226+g..242+g] for IQN+Attn+TLOB
gpu_curiosity_trainer.rs: cur_beta1/beta2/epsilon params added to
launch_adam_step + train_on_collector_buffers
gpu_experience_collector.rs: train_curiosity_gpu threads cur_beta1/2/eps
training_loop.rs: reads ISV[233/241/249] for Curiosity=7 at call site
Pearl 5 (per-branch IQN tau schedule):
gpu_iqn_head.rs: new refresh_taus_from_isv() averages 4 branches per
quantile, applies FIXED_TAUS cold-start floor, re-uploads online_taus/
target_taus/cos_features in-place via upload_f32_via_pinned
fused_training.rs: reads ISV[250..270) before IQN prepare_buffers
Pearl 6 (Kelly cap) + Pearl 8 (trail distance) done in prior session:
trade_physics.cuh, experience_kernels.cu, backtest_env_kernel.cu
Audit doc: dqn-wire-up-audit.md SP5 Layer B entry added.
All 930 passing lib tests still pass; 14 pre-existing failures unchanged.
Compile: SQLX_OFFLINE=true cargo check -p ml --offline clean.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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jgrusewski
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19e5cde91e |
docs(sp5): Layer A close-out — replace stale scratch-buf comment
Code-quality review of A8 caught that gpu_dqn_trainer.rs:15154 still read `// to SP5_SCRATCH_TOTAL (103) = 71 + 16 (q_branch_stats) + 16 (pearl_1_atom)` — pre-existing from A1 that wasn't updated as the constant grew through A2-A8 (103 → 111 → 131 → 171 → 199 → 203 → 207). The runtime allocation is correct (uses the constant, not the literal), so this was readability-only. Replaced the 2-line stale comment with the complete scratch-buffer layout map covering all SP5 Layer A producer outputs: [0..71) SP4 producers [71..87) q_branch_stats (Pearl 1 / A1) [87..103) pearl_1_atom_update (Pearl 1 / A1) [103..107) pearl_3_sigma σ (Pearl 3 / A2) [107..111) pearl_3_sigma SF (Pearl 3 / A2) [111..131) pearl_2_budget (Pearl 2 / A3) [131..147) pearl_4 cosine + l2 (auxiliary, A4) [147..171) pearl_4 β1/β2/ε (Pearl 4 / A4) [171..199) pearl_5 skew/kurt+τ (Pearl 5 / A5) Pearl 6 (A6) writes directly to ISV — no scratch. [199..203) pearl_8 trail_dist (Pearl 8 / A7) [203..207) pearl_1-ext num_atoms (Pearl 1-ext / A8) Closes the last residual A1-vintage comment debt; gives Layer B implementers a self-contained map of the scratch contract. Comment-only change. cargo check clean. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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2e84fd35d4 |
feat(sp5): Task A8 — Pearl 1-ext per-branch num_atoms — Layer A complete
Final SP5 Layer A producer. Per-branch C51 num_atoms derived from
per-branch ATOM_V_HALF (Pearl 1, Task A1). Threshold cascade:
v_half < 0.1 → 64 atoms (narrow Q, high resolution)
v_half < 1.0 → 32 atoms (moderate)
v_half ≥ 1.0 → 16 atoms (wide Q, modest resolution)
4 ISV slots [ATOM_NUM_ATOMS_BASE=274..278). Pearls A+D smooths the
discrete output during transitions; Layer B's atoms_update consumer
rounds to nearest valid count.
producer_step_scratch_buf grew 203 → 207. wiener_state_buf already
at 543 (sized at A1 for entire SP5 block).
StateResetRegistry: 1 new FoldReset entry (sp5_atom_num_atoms).
atoms_update consumer migration deferred to Layer B.
LAYER A COMPLETE. 8 producers + 3 auxiliary kernels (q_branch_stats,
grad_cosine_sim, q_skew_kurtosis) populating 110 ISV slots [174..286)
with 4 cross-fold-persistent slots carved out (Kelly).
Refs: SP5 spec
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