docs(dqn): T6 polish — fix 4 stale Pearl 2 prose references in gpu_dqn_trainer.rs
Four comment/docstring sites still described the pre-SP7 Pearl 2 as writing "20 floats / 5 outputs / c51/cql/ens" after the T6 kernel- signature shrink. Updated to reflect the current 6-arg kernel writing 8 floats (IQN + flatness only) into scratch[115..119, 127..131). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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@@ -304,17 +304,16 @@ static SP5_PEARL_1_ATOM_CUBIN: &[u8] =
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static SP5_PEARL_3_SIGMA_CUBIN: &[u8] =
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include_bytes!(concat!(env!("OUT_DIR"), "/pearl_3_sigma_kernel.cubin"));
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/// SP5 Task A3 (2026-05-01): Pearl 2 per-branch loss budget cubin.
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/// SP5 Task A3 + SP7 (2026-05-03): Pearl 2 IQN budget + flatness producer cubin.
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/// Single-block 4-thread kernel. Reads Q_VAR_PER_BRANCH[b] (Pearl 1's
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/// q_branch_stats output, ISV[222..226)) + NOISY_SIGMA[b] (Pearl 3 output,
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/// ISV[210..214)). Computes per-branch flatness = clamp(var_q / (σ²+EPS_DIV),
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/// 0, 1) and derives (budget_iqn, budget_c51, budget_cql=0, budget_ens,
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/// flatness) per branch. Writes 20 floats to
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/// producer_step_scratch_buf[111..131). Chained apply_pearls_ad_kernel
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/// (20 single-slot launches) smooths via Pearls A+D into ISV[190..210).
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/// 0, 1) and derives (budget_iqn, flatness) per branch. Writes 8 floats to
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/// producer_step_scratch_buf[115..119, 127..131). Chained apply_pearls_ad_kernel
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/// (8 single-slot launches) smooths via Pearls A+D into ISV[194..198, 206..210).
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/// SP7: C51/CQL/ENS budget ownership transferred to loss_balance_controller_kernel.
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/// Must run AFTER launch_sp5_pearl_1_atom (Q_VAR) AND
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/// launch_sp5_pearl_3_sigma (NOISY_SIGMA).
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/// Layer A only — loss-budget consumer migration deferred to Layer B.
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static SP5_PEARL_2_BUDGET_CUBIN: &[u8] =
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include_bytes!(concat!(env!("OUT_DIR"), "/pearl_2_budget_kernel.cubin"));
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@@ -1069,7 +1068,7 @@ pub const SP5_WIENER_TOTAL_FLOATS: usize =
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/// 4 floats for pearl_3_sigma output (SCRATCH_PEARL_3_SIGMA=103, sigma × 4 branches)
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/// 4 floats for pearl_3_sf output (SCRATCH_PEARL_3_SF=107, sigma_fraction × 4 branches)
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/// Task A3 adds:
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/// 20 floats for pearl_2_budget output (5 outputs × 4 branches at [111..131))
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/// 8 floats for pearl_2_budget output (2 outputs × 4 branches; SP7 retired C51/CQL/ENS slots)
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/// [111..115) reserved-for-future (T6 retired SCRATCH_PEARL_2_C51)
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/// budget_iqn[4] → SCRATCH_PEARL_2_IQN=115
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/// [119..127) reserved-for-future (T6 retired SCRATCH_PEARL_2_CQL/_ENS)
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@@ -14331,9 +14330,9 @@ impl GpuDqnTrainer {
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.map_err(|e| MLError::ModelError(format!("pearl_3_sigma_update load: {e}")))?
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};
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// SP5 Task A3 (2026-05-01): load pearl_2_budget loss budget controller kernel.
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// SP5 Task A3 + SP7 (2026-05-03): load pearl_2_budget IQN budget + flatness kernel.
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// Single-block 4-thread kernel; reads Q_VAR_PER_BRANCH (ISV[222..226)) +
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// NOISY_SIGMA (ISV[210..214)) from ISV; writes 20 floats to scratch[111..131).
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// NOISY_SIGMA (ISV[210..214)) from ISV; writes 8 floats to scratch[115..119, 127..131).
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// Must be invoked AFTER pearl_1_atom (Q_VAR) AND pearl_3_sigma (NOISY_SIGMA).
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let pearl_2_budget_kernel = {
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let module = stream.context().load_cubin(SP5_PEARL_2_BUDGET_CUBIN.to_vec())
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@@ -16082,7 +16081,7 @@ impl GpuDqnTrainer {
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// [87..103) pearl_1_atom_update (Pearl 1 / A1)
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// [103..107) pearl_3_sigma σ (Pearl 3 / A2)
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// [107..111) pearl_3_sigma SF (Pearl 3 / A2)
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// [111..131) pearl_2_budget (Pearl 2 / A3 — c51/iqn/cql/ens/flatness)
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// [111..131) pearl_2_budget (Pearl 2 / A3 — iqn/flatness; SP7 retired c51/cql/ens)
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// [131..147) pearl_4 cosine + l2 (auxiliary grad_cosine_sim, A4)
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// [147..171) pearl_4 β1/β2/ε (Pearl 4 / A4)
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// [171..199) pearl_5 skew/ex_kurt + IQN τ schedule (A5)
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@@ -3910,6 +3910,8 @@ extended. No producer kernel yet — that arrives in the next commit.
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apply_pearls smoothing loop shrinks from 5 slot-blocks to 2 (IQN +
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flatness). SCRATCH_PEARL_2_C51/_CQL/_ENS deleted as orphans per
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feedback_wire_everything_up. CQL/C51/ENS budget ownership now lives
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entirely in the SP7 controller.
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entirely in the SP7 controller. T6 polish: 4 stale prose references
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(cubin static docstring, scratch layout header, constructor load
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comment, scratch map) updated to reflect 8-float / 2-output contract.
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- T7: launch site + sentinel-aware bootstrap with bootstrap constants matching the kernel's cold-start basis (defined in T7) + stale doc.
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- T9–T10: smoke + 50-epoch verification.
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