a54f53e4eda68bfe800f16144e9bc5cb56d7287a
4760 Commits
| Author | SHA1 | Message | Date | |
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jgrusewski
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a54f53e4ed |
feat(sp15-wave4.1c): behavioral KL test — dd_pct trunk integration shifts policy distribution
Closes out Wave 4.1 (Phase 1.5.b consumer migration). Wave 4.1a ( |
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jgrusewski
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eb9515e41c |
feat(sp15-wave4.1b): consumer migration — s1_input_dim 102→103, GRN w_s1 reshape, 4 forward + 3 backward sites
Atomic consumer migration that flips production callers of bn_tanh_concat_kernel
over to Wave 4.1a's bn_tanh_concat_dd_kernel and bumps s1_input_dim from 102 to
103 across the entire trunk forward + backward path. Eliminates the documented
Wave 4.1a transient orphan.
Changes:
- s1_input_dim formula bump (bn_dim + portfolio_dim → bn_dim + portfolio_dim + 1)
at compute_param_sizes, trainer ctor's CublasGemmSet, xavier_init_params_buf,
the experience collector's CublasGemmSet, and CublasBackwardSet::new for the
backward gemm cache. cuBLAS gemm caches re-key automatically (fresh HashMap).
- GRN w_a_h_s1[0] / w_residual_h_s1[4] reshape [shared_h1, 102] → [shared_h1, 103]
via compute_param_sizes + xavier_init's fan_dims. Xavier-uniform init covers
the new dd_pct column (bounded [0,1] — Xavier's small-magnitude assumption is
appropriate; differs from SP14's aux_softmax_diff zero-init which was driven
by the bidirectional ±1 range).
- bn_concat_dim() accessor +1 (TLOB backward row stride).
- 5 concat_dim local-var bumps (1 alloc + 3 forward + 2 backward + 1 in
experience collector).
- 4 forward-call migrations to launch_sp15_bn_concat_dd: DDQN argmax pass
(~27158), online forward (~27467), target forward (~27666), experience
collector forward (~3853). Each takes self.isv_signals_dev_ptr; the kernel
reads ISV[DD_PCT_INDEX=406] on-device and broadcasts.
- 3 GRN backward sites (main, ensemble, CQL) flow through encoder_backward_chain
which uses s1_input_dim — bumped automatically. dd_pct column gradient is
silently discarded by vsn_d_gated_state_portfolio_pad_kernel (reads
[bn_dim..bn_dim+portfolio_dim) only) and bn_tanh_backward_kernel (reads
[0..bn_dim) only). Correct: dd_pct sources from ISV bus, no learnable input.
- Legacy bn_tanh_concat_kernel field DELETED from trainer struct alongside its
loader, tuple-element, destructuring, assignment (5 mechanical sites for the
one dead field). Function tuple shrinks 44→43 elements. Kernel symbol stays
in the cubin source for SP15 oracle parity tests.
- mag_concat / OFI concat audit verdict: DECOUPLED from s1_input_dim. They
widen shared_h2, not the trunk INPUT dim.
- test_gpu_backtest_evaluator_state_dim_calculation migrated to assert
STATE_DIM == 128 (was 96, stale per feedback_trust_code_not_docs).
Atomic per feedback_no_partial_refactor: every consumer of s1_input_dim and
bn_concat_buf row-stride migrated together. Eliminates Wave 4.1a transient-
orphan launcher per feedback_wire_everything_up. Legacy field deleted per
feedback_no_legacy_aliases.
Tests: cargo check clean (18 pre-existing unrelated warnings). Wave 4.1a
oracle parity test (bn_tanh_concat_dd_kernel_writes_dd_pct_column) still
passes. ML lib suite went from 945 pass / 14 fail (pre-Wave-4.1b baseline) to
947 pass / 12 fail post-Wave-4.1b — improved by +2 (state_dim_calculation
migration + ensemble checkpoint round-trip flake resolved).
Refs: SP15 Wave 4.1a (
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jgrusewski
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a8da1cb9cf |
feat(sp15-wave4.1a): bn_tanh_concat appends dd_pct column from ISV — bottleneck-aware Phase 1.5 consumer migration
The standalone dd_pct_concat_kernel from Phase 1.5 was bottleneck-
incompatible — it operated on raw [B, 128] state, but production trunk
consumes [B, s1_input_dim] = [B, 102] post-bottleneck. Wave 4.1a fixes
this at the kernel level; Wave 4.1b lands the consumer migration
(s1_input_dim 102→103, GRN w_s1 reshape, 3 forward + 3 backward sites).
Spec correction (per feedback_trust_code_not_docs): the spec's
'state_dim 48→49' is stale terminology pre-STATE_DIM 48→112→128
evolution. Production s1_input_dim is bottleneck_dim + (STATE_DIM −
market_dim) = 16 + (128 − 42) = 102. Wave 4.1b will bump this to 103.
NEW bn_tanh_concat_dd_kernel in dqn_utility_kernels.cu:
- Fuses dd_pct append into the same launch as bn_tanh + portfolio
concat (output shape [B, bn_dim + portfolio_dim + 1])
- Reads isv[DD_PCT_INDEX=406] (set by Wave 1.3.b dd_state_kernel
per-step), broadcasts the scalar across batch as the appended
last column
DELETED standalone dd_pct_concat_kernel.cu + launch_sp15_dd_pct_concat
+ cubin manifest entry per feedback_no_legacy_aliases (zero production
callers — only test consumer; bottleneck-on path is canonical).
Test helpers added (used by Wave 4.1c behavioral KL test).
Phase 1.5 oracle test migrated to bn_tanh_concat_dd_kernel contract:
test name bn_tanh_concat_dd_kernel_writes_dd_pct_column passes on
RTX 3050 Ti.
Layout fingerprint already covers Phase 1.5 via the existing
TRUNK_INPUT_DD_PCT=sp15_phase_1_5; marker — pre-SP15 checkpoints
already break.
fxcache schema_hash auto-bumps from file content hashes (per task
P5T5 Phase F mechanism); no manual schema bump needed.
Atomic per feedback_no_partial_refactor for the kernel-signature
contract change. Consumer wiring (s1_input_dim propagation, GRN
reshape, forward/backward call sites) deferred to Wave 4.1b's atomic
commit per the established 3a/3b split precedent — kernel + launcher
land first.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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4320820ae2 |
feat(sp15-wave3b): host-side wire-up — eliminates 5 orphan launchers via GpuBacktestEvaluator constructor signature change
Second half of the Wave 3 val-cost-streams refactor (3a kernel-side
foundation landed at
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jgrusewski
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e968f4ded9 |
feat(sp15-wave3a): kernel-side foundation — baseline output buffers + position_history derivation
Wave 3a half of the val-cost-streams refactor (3b host-side wire-up
follows). Atomically migrates the kernel-side contracts; 5 launchers
remain orphan transiently awaiting 3b production callers.
Baseline kernels (1.4):
- 4 baseline_*_kernel signatures gain 'out: float*' parameter writing
per-window [mean, std, raw_sharpe] (matches 1.1.b sharpe_per_bar shape)
- ISV writes to slots 409, 410, 412, 416 removed entirely
(per-window output is correct for WindowMetrics consumption;
ISV-scalar writes were spec scaffolding for a single-fold-aggregate
version that 1.4.b's per-window contract supersedes)
- 4 ISV slot constants removed from sp15_isv_slots.rs
- state_reset_registry: NO entries to remove (verified via grep —
the 4 slots never had registry entries / dispatch arms in the first
place; they were single-fold-aggregate scalars defaulted at every
fold start by the constructor-write that initialises the ISV bus).
Task 4 from the dispatch is a no-op; the
every_fold_and_soft_reset_entry_has_dispatch_arm regression test
continues to pass unchanged.
- 4 oracle tests migrated to output-buffer assertion
- layout_fingerprint_seed string updated (4 retired entries removed,
4 trunk-shared entries retained; layout-break-class change)
New action_decoding_helpers.cuh:
- Extracts factored_action_to_dir_idx + factored_action_to_position
__device__ helpers (the latter is a higher-level position state-
machine helper not previously available)
- Mirrors trade_physics.cuh::decode_direction_4b semantics exactly so
on-policy and counterfactual paths agree on factored-action meaning
- Single source of truth for action→direction→position mapping;
consumers #include the header
New position_history_derivation_kernel.cu (post-loop derivation for
cost_net_sharpe consumer in Wave 3b):
- Reads actions_history_buf, reconstructs per-bar position_history
(-1/0/+1), side_ind (1.0 on position change), rt_ind (1.0 on
transition-to-flat from non-flat) via sequential walk (single
block per window, no atomicAdd per feedback_no_atomicadd)
- New launcher launch_sp15_position_history_derivation in
gpu_dqn_trainer.rs
- New cubin manifest entry in build.rs
- 1 oracle test covering 8-bar Short→Hold→Long→Hold→Flat→Long→Flat→
Short sequence; expected position/side_ind/rt_ind triples match
hand-computed values
Atomic per feedback_no_partial_refactor for the ISV-contract change
(every consumer of slots 409/410/412/416 migrated in this commit; their
consumers were the 4 oracle tests, all migrated). The orphan launcher
transient state for the 5 baselines + derivation kernel is explicitly
the 3a/3b split point — production callers land in 3b's
GpuBacktestEvaluator::new constructor signature change.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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334b496647 |
feat(sp15-wave2): fused post-SP11 reward-axis composer (layered architecture)
Closes the deferred-consumer gap left by Phase 3.1
(r_quality_discipline_split_kernel, commit
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jgrusewski
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f01a292f6f |
feat(sp15-p3.5.b+3.5.3.b): wire hold_floor (inline) + cooldown mask into experience_action_select
Phase 3.5 (hold_floor_kernel) + Phase 3.5.3 (cooldown_kernel) landed the producer + state machinery; both deferred the action-selection consumer wiring. This task wires both atomically. Architectural decision: hold_floor is now an INLINE __device__ computation inside experience_action_select reading ISV slots 426/427/428/429 directly. The standalone hold_floor_kernel.cu + launch_sp15_hold_floor + HOLD_FLOOR_CUBIN are deleted — launching a kernel to write one f32 just to read it back was unnecessary. ISV slots + state_reset_registry entries remain; only the launch path is removed per feedback_wire_everything_up + feedback_no_legacy_aliases. Entropy source: per-step Shannon entropy of softmax(e_dir) computed inline from the 4 e_dir floats already in registers (Pass 1 of the Thompson direction selector). High entropy = uncertain policy → Hold gets the floor lift; low entropy = confident policy → floor ≈ 0. q_eff_dir scratch preserves e_dir for downstream consumers (out_conviction, out_q_gaps, out_magnitude_conviction) — adding hold_floor there would corrupt the Kelly-cap warmup floor with a meta-confidence mask. cooldown mask: when ISV[COOLDOWN_BARS_REMAINING=435] > 0, action_select hard short-circuits to dir_idx = DIR_HOLD before Pass 2 — sidesteps the temperature-blend numerics where a finite-sentinel-on-non-Hold approach would let pure-Thompson (τ=1) samples dominate the masked direction. Cooldown supersedes hold_floor — when forcing Hold the floor is moot. 3 new oracle tests: - action_select_applies_hold_floor_inline (no cooldown) - action_select_forces_hold_during_cooldown - action_select_no_force_hold_when_cooldown_zero Atomic per feedback_no_partial_refactor: action_select changes + hold_floor_kernel deletion + cubin manifest update + 3 oracle tests + audit doc all in this commit. No parallel paths, no feature flags. Eliminates Phase 3.5 + Phase 3.5.3 deferred consumers. The cooldown_kernel itself remains (it maintains the consecutive_losses streak + decrements COOLDOWN_BARS_REMAINING per bar); only its consumer is now wired. Verified: cargo check -p ml --features cuda clean; ml lib suite holds 946 pass / 13 fail = baseline; all 6 oracle tests pass on RTX 3050 Ti (3 pre-existing cooldown + 3 new action_select). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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d7f60d4dd7 |
feat(sp15-p1.6.b+1.7.b): wire dev-eval (Q8 final-fold) + test-eval (per-fold) into trainer
Phase 1.6 (CLI flags + dev_features/holdout_features stash) and Phase
1.7 (set_test_data_from_slices observer + test_features stash) landed
the data-flow scaffolding; both deferred the actual eval consumer.
This task wires both atomically as parallel evaluator instances:
- dev_evaluator: Option<GpuBacktestEvaluator> -- lazy-init after final
fold, fires once against Q8 dev_features (when dev_quarters > 0)
- test_evaluator: Option<GpuBacktestEvaluator> -- lazy-init per fold,
fires inside the fold loop against the WF test slice (when
fold.test_end > fold.test_start)
Architectural choice: parallel evaluator instances (NOT window-swap on
val_evaluator). Window-swap would require invalidating the CUDA graph
between val and dev/test runs -- fragile, and a direct violation of
pearl_no_host_branches_in_captured_graph. Parallel instances mirror
val_evaluator's lazy-init pattern (TLOB sync, ISV signal pointer,
training_mode = false toggle). Implementation lives behind a single
shared helper `launch_extra_eval` keyed on an `ExtraEvalKind` enum so
Dev / Test share TLOB / ISV / config setup verbatim.
HEALTH_DIAG additions:
HEALTH_DIAG[N]: dev_eval dev_sharpe_net=... dev_calmar=... dev_max_dd=... dev_trades=...
HEALTH_DIAG[N]: test_slice fold=K test_sharpe_net=... test_calmar=... test_max_dd=... test_trades=...
The *_sharpe_net key uses the fused-metrics-kernel cost-aware Sharpe
(post-Phase-1.1.b split -- already includes tx_cost_bps + spread_cost
via the env-step PnL feed); when Phase 1.2.b cost-net sharpe lands, the
key name is preserved so the aggregator-script contract holds.
Atomic per feedback_no_partial_refactor: both eval calls + both
evaluator fields + both HEALTH_DIAG lines + audit doc all in this
commit. No parallel paths, no feature flags. Dev_eval runs synchronously
via evaluate_dqn_graphed (one-shot, no async pipelining benefit since
it doesn't fire per-epoch); val path stays async.
Sealed Q9 holdout remains untouched -- Phase 4.3 will load Q9 via a
separate eval-only entry point (NOT train_walk_forward). The Phase 1.6
debug_assert sealed-slice guard catches accidental future refactors.
Verified: cargo check -p ml --features cuda clean; ml lib suite holds
946 pass / 13 fail baseline; the existing Phase 1.7 oracle test
set_test_data_from_slices_fires_observer_and_stashes still passes.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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132609724e |
feat(sp15-p1.3.b): wire dd_state per-step launch + drop equity-recompute bug + env-0 canonical observable
Path A of the blocked 1.3.b investigation: fixes two architectural issues atomically and wires the launcher. (1) Bug fix: dd_state_kernel.cu was recomputing new_equity = PS_PREV_EQUITY + pnl_step and writing it back, but experience_env_step already maintains PS_PREV_EQUITY (experience_kernels.cu:3473-3475) — wiring as-is would silently double-accumulate equity every step. Kernel now READS PS_PREV_EQUITY / PS_PEAK_EQUITY only; does not modify them. pnl_step parameter dropped from both kernel and launcher signatures. (2) Per-env shape decision: kernel is single-thread/single-block; production has N envs but DD ISV slots [401..407) are scalars. Picks 'env 0 as canonical observable' — kernel reads pos_state[0 * PS_STRIDE + ...]. Per-env redesign (per-env tiles + reduction kernel) deferred to Phase 1.3.b-followup if L40S smoke shows single-env DD aggregation is insufficient. (3) Wire-up: launch added at gpu_experience_collector.rs step 5b in launch_timestep_loop, immediately after env_step writes PS_PREV_EQUITY, outside the exp-fwd graph capture region (which ends at line ~3829, well before env_step). Atomic per feedback_no_partial_refactor: kernel signature change + oracle test update + launcher call site update all in this commit. Eliminates the Phase 1.3 orphan launcher per feedback_wire_everything_up. Downstream Phase 3.3 / 3.5.2 / 3.5.4 / 3.5.5 readers will receive live DD values when their consumer wiring lands. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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eda1eccb1a |
merge(sp15): bring phase2a (LobBar + behavioral test scaffold + 17 tests) into phase1
Brings in Phase 2A.1 (LobBar canonical ABI + 4 synthetic market generators), Phase 2A.2 (oracle + harness + pre-commit hook), and Phase 2B (17 #[ignore] behavioral test contracts) so the phase1 honest-numbers branch has access to the LobBar (price, half_spread, ofi) ABI needed for Phase 1.2.b cost-net sharpe consumer wiring. Path 2 of the BLOCKED 1.2.b investigation: the cost-net kernel needs GPU-resident streams (half_spread, ofi, rt_ind, side_ind, position) that do not exist on phase1; Phase 2A.1's LobBar provides the canonical ABI. Conflict resolution: docs/dqn-wire-up-audit.md — both branches prepended entries; merged by keeping all three (Phase 2A.1 from phase2a, Phase 1.6, Phase 1.7 from phase1). Phase 2A.1 entry placed above Phase 1.6 / 1.7 to keep this region's audit ordering consistent (newer-first locally). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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b791bc8f7f |
refactor(sp15-p1.1.b): split sharpe out of fused backtest_metrics kernel; wire dedicated launch_sp15_sharpe_per_bar
Phase 1.1 landed sharpe_per_bar_kernel.cu + launch_sp15_sharpe_per_bar
as orphan scaffolding because the val-side sharpe was inline in
backtest_metrics_kernel's 8-metric fusion (lines 208-211, 277), not
a host-side loop the spec sketch had assumed.
This refactor splits sharpe out:
- backtest_metrics_kernel computes 7 metrics now (sortino, win_rate,
max_dd, calmar, omega, VaR, CVaR; remaining counters unchanged).
Output stride drops 14 -> 13; shmem 6 -> 5 reduction arrays.
- gpu_backtest_evaluator calls launch_sp15_sharpe_per_bar against
the same GPU-resident per-bar returns buffer, once per window
(kernel is single-block by design; n_windows is small).
- Annualization moves host-side: WindowMetrics.sharpe =
raw_sharpe * annualization_factor.
Atomic per feedback_no_partial_refactor: kernel split + offset
rebase (every metric below sharpe shifted down by 1) + the lone
WindowMetrics.sharpe consumer (consume_metrics_after_event)
migrated in one commit. No parallel paths.
Output value of WindowMetrics.sharpe is preserved (verified to
1e-5 relative error against f64 closed-form via new oracle test
unified_sharpe_kernel_equivalence_under_annualization). All
existing Phase 1.1 oracle tests still pass; ml lib test suite
holds at the 945/13 baseline (no new regressions).
Eliminates the Phase 1.1 orphan launcher per feedback_wire_everything_up.
Sets up Phase 1.2.b cost-net sharpe to also use launch_sp15_cost_net_sharpe
on the cost-net returns buffer (separate task, separate commit).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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69b8fdb61a |
feat(sp15-p3.5.5): recovery curriculum — per-step DD_TRAJECTORY_DECREASING proxy
Per spec §9.2 (3.5.5) post-amendment-2: replaces non-existent episode-level metadata with per-bar signal that fires when dd_pct(t) < dd_pct(t-1) AND dd_pct(t-1) > DD_TRAJECTORY_FLOOR — i.e. transition is part of a recovery from non-trivial DD. PER sampler (Phase 3.5.5.b follow-up) will read this and weight: sampling_weight = base × (1 + RECOVERY_OVERSAMPLE_WEIGHT × signal) so recovery transitions get amplified gradient signal, completing the downward-spiral break-out chain (3.5.2 reward asymmetry → 3.5.3 cooldown gate → 3.5.4 plasticity → 3.5.5 PER recovery curriculum). 3 ISV slots: 439 DD_TRAJECTORY_DECREASING, 440 RECOVERY_OVERSAMPLE_ WEIGHT (2.0 sentinel; ISV-driven from current dd_pct in follow-up), 441 DD_TRAJECTORY_FLOOR (0.02 sentinel; ISV-driven 25th percentile of running dd_pct distribution in Phase 3.5.5.c follow-up per feedback_isv_for_adaptive_bounds). New sp15_dd_trajectory_prev_dd MappedF32Buffer (size 1) tracks prev_dd across kernel calls — mirrors Task 3.5.3 sp15_cooldown_ consecutive_losses non-ISV mapped-pinned scratch pattern. 4 fold-reset registry entries + dispatch arms (3 ISV + 1 scratch). Per established Phase precedent: kernel + launcher land first; PER sampler integration and 25th-percentile floor producer are purely additive follow-ups per feedback_no_partial_refactor. Anchor test 2.10 recovery_after_streak (Phase 2C / Phase 3.5 paired) — fully green via 3.5.2 + 3.5.4 + 3.5.5 combined. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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e0e0abfb28 |
feat(sp15-p3.5.4): plasticity injection trigger + warm-up tracker (weight-reset deferred)
Per spec §9.2 (3.5.4) post-amendment-2 fix. TWO-STEP recovery:
1. Fire when DD_PERSISTENCE > PLASTICITY_PERSISTENCE_THRESHOLD AND
PLASTICITY_FIRED_THIS_FOLD == 0 → set fired flag, set warm-bars
counter to M_warm (default 200). [DEFERRED: reset last 10% of
advantage-head weights to Kaiming-He init via cuRAND.]
2. Per-bar warm-bars decrement; action-selection layer (consumer wiring
follow-up) reads max(COOLDOWN_BARS_REMAINING, PLASTICITY_WARM_BARS_
REMAINING) and forces Hold while > 0.
Weight-reset DEFERRED to Phase 3.5.4.b — kernel signature plumbed
(advantage_head_weights + n_weights) but no-op via (void) cast.
Documented in audit doc.
3 ISV slots: 436 PLASTICITY_FIRED_THIS_FOLD (debounce flag, resets at
fold boundary to re-arm next fold), 437 PLASTICITY_PERSISTENCE_THRESHOLD
(initial 100.0 sentinel; ISV-tracked from running mean of dd_persistence
in follow-up), 438 PLASTICITY_WARM_BARS_REMAINING (counter, OR-gates
with cooldown).
3 fold-reset registry entries + dispatch arms.
Three GPU oracle tests pass: fires-when-persistence-exceeds-threshold
(warm_bars [198, 200] post-fire-and-decrement), debounced-within-fold
(no re-fire when fired=1; warm decrements 50→49), no-fire-below-threshold.
Anchor test 2.22 plasticity_cooldown_interlock (Phase 2C / Phase 3.5
paired) — green via 3.5.4.b follow-up + action-selection consumer wiring.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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649128e739 |
feat(sp15-p3.5.3): cooldown gate — K=5 force Hold for M=20 bars (initial sentinels)
Per spec §9.2 (3.5.3). After K consecutive losing trades, force Hold for M bars. Counter at COOLDOWN_BARS_REMAINING (slot 435) part of state — model can reason about it. Initial K=5, M=20 hardcoded sentinels. ISV-driven K via MEDIAN_STREAK_ LENGTH (slot 442) producer using two-heap median tracking is documented Phase 3.5.3 follow-up. ISV-driven M from vol_normalizer time-to-mean- reversion is also follow-up. 4 ISV slots: 433 K_THRESHOLD, 434 M_BARS, 435 BARS_REMAINING, 442 MEDIAN_STREAK_LENGTH. New sp15_cooldown_consecutive_losses MappedF32Buffer tracks streak counter persistent across kernel calls. 5 fold-reset registry entries + dispatch arms (4 ISV slots + scratch buffer reset). Per spec post-amendment-2 fix: streak counter only updates on trade-close events; per-bar non-close calls just decrement the cooldown counter. The trigger gate fires only when a trade-close lands during an inactive cooldown — re-arming mid-cooldown would extend the gate every closed trade during the freeze, which is not the spec. Per established Phase precedent: kernel + launcher land first; action- selection wiring (force Hold while cooldown_remaining > 0) deferred to follow-up commit per feedback_no_partial_refactor. Anchor test 2.12 cooldown_engagement (Phase 2C / Phase 3.5 paired) — green via this commit. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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aa91ce4d82 |
feat(sp15-p3.5.2): asymmetric reward under DD — gain × (1 + λ × dd_pct), pre-SP12-cap
Per spec §9.2 (3.5.2). For gains: r_adjusted = r × (1 + λ × dd_pct). For losses: unchanged. Multiplier applies BEFORE SP12 NEG/POS cap clamp; saturating the cap for big recovery trades is behaviorally correct per spec (encourages frequent small recoveries). 3 ISV slots: 430 DD_ASYMMETRY_LAMBDA (initial 0.5; ISV-tracked from running DD variance via DD_DIST_VAR is follow-up), 431 R_GAIN_DD_BOOST (diagnostic — most recent boost), 432 DD_DIST_VAR (running variance, producer follow-up). 3 fold-reset registry entries + dispatch arms. Per established Phase precedent: kernel + launcher land first; reward composer site (apply multiplier BEFORE SP12 cap) deferred to follow-up commit per feedback_no_partial_refactor. Anchor test 2.10 recovery_after_streak (Phase 2C / Phase 3.5 paired) — green via 3.5.2 + 3.5.3 + 3.5.4 + 3.5.5 combined. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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5d36f3238c |
feat(sp15-p3.5): confidence-aware Hold floor — bounded sigmoid
Per spec §8.2 (3.5) post-amendment-2 fix. hold_floor = α × σ(k × (entropy − ε₀)) added to Q_hold pre-argmax/Thompson selection. Hold becomes uncertainty expression, not distributional default. α (HOLD_FLOOR_ALPHA slot 426) initial 0.5 sentinel — producer kernel updating from rolling 95th percentile of |Q_dir| (NOT running max — outlier-ratchet vulnerable per spec second-review #6) is documented Phase 3.5 follow-up. k (HOLD_FLOOR_K slot 427) initial 10.0 — producer from running variance of entropy is follow-up. ε₀ (HOLD_FLOOR_EPS0 slot 428) initial 1.0 — producer from 75th percentile of entropy distribution (ENTROPY_DIST_REF slot 429) is follow-up. 4 fold-reset registry entries + dispatch arms. Per established Phase precedent: kernel + launcher land first; action- selection wiring (add hold_floor to Q_hold pre-argmax/Thompson) deferred to follow-up commit per feedback_no_partial_refactor. Anchor tests: 2.1 flat_market_holds + 2.6 regime_silences (Phase 2B contracts) — green via this teaching's action-selection wiring. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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8bfc480d92 |
feat(sp15-p3.4): regret signal = r_discipline content + first-obs bootstrap EMA
Per spec §8.2 (3.4). When policy holds AND a trade would have been profitable past cost+trail, regret_bar = ideal_pnl_missed - cost_t. EMA tracked at REGRET_EMA (slot 423) with first-observation bootstrap (per pearl_first_observation_bootstrap) + simple exponential decay (α=0.05; Wiener-α adaptive swap is a documented follow-up). r_discipline_per_bar = -LAMBDA_REGRET × REGRET_EMA composed at the reward-split site in the follow-up consumer commit per feedback_no_partial_refactor. 3 ISV slots: 423 REGRET_EMA, 424 LAMBDA_REGRET (initial 1.0), 425 REGRET_GRAD_NORM. 3 fold-reset registry entries + dispatch arms. Anchor test 2.6 regime_silences (Phase 2B contract) — green via 3.4 + 3.5 combined. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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7753cbef1b |
feat(sp15-p3.3): quadratic DD penalty + ISV-driven λ + threshold
Per spec §8.2 (3.3). penalty = λ_dd × max(0, dd_current − dd_threshold)² Asymmetric: zero below threshold, quadratic growth above. Encodes loss aversion per pearl_audit_unboundedness_for_implicit_asymmetry. 3 ISV slots: 420 LAMBDA_DD (initial 1.0; ISV-tracked from grad-balance in follow-up), 421 DD_THRESHOLD (initial 0.05 = 5% drawdown trigger), 422 DD_PENALTY_GRAD_NORM (initial 0.0). 3 fold-reset registry entries + dispatch arms. Per established Phase precedent: kernel + launcher land first; reward composition site (subtract penalty from r_total) deferred to follow-up commit per feedback_no_partial_refactor. Anchor test 2.5 drawdown_de_risks (Phase 2C / Phase 3.5 paired) — green via Phase 3.5 mechanisms; this commit lands the penalty primitive. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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1eac41d644 |
feat(sp15-p3.2): explicit cost in r_quality on trade-close events
Per spec §8.2 (3.2). Extends the Phase 3.1 composer kernel
`r_quality_discipline_split_kernel` with two new args (`float cost_t`,
`unsigned int trade_close_indicator`) and subtracts
`cost_t * (float)trade_close_indicator` from `r_quality` BEFORE the α
blend. Same `cost_t` scalar shape as the Phase 1.2 cost_net_sharpe
accumulator (commission + per-side spread + OFI-impact); the gate
`trade_close_indicator=1` on round-trip-close bars (rt_ind=1) and 0
otherwise so non-close bars receive a structural no-op identical to
the pre-Phase-3.2 behaviour. Model SEES the bill in the gradient
signal during training, not just in eval-time metrics.
Approach: kernel-signature-extension (NOT wrapper-kernel). The only
existing call site in the tree is the Phase 3.1 oracle test
(`training_loop.rs` has dispatch-arm reset wiring but does NOT yet
invoke the launcher per the Phase 3.1 commit's deferred-consumer
note), so the cascade is bounded to that single test — extending the
existing kernel is cleaner than a parallel wrapper that would have to
be retired the moment the Phase 3.1 deferred consumer migration
lands.
Anchor test 2.4 cost_sensitivity (Phase 2B contract) — green via this
commit + Phase 3.1 split structure (already landed in
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jgrusewski
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2d226e6e76 |
feat(sp15-p3.1): r_quality + r_discipline split with ISV-driven α + sentinel cold-start
Per spec §8.2 (3.1) post-amendment-2 fix: ALPHA_SPLIT slot initialized
DIRECTLY to 0.5 in trainer constructor. Formula α = grad_norm_q /
(grad_norm_q + grad_norm_d + ε) takes over only after BOTH grad-norm
EMAs accumulate ≥ N_WARM=100 non-zero observations.
Two kernels in r_quality_discipline_split_kernel.cu (single cubin per
established 1:1-source-to-cubin pattern with multiple kernels):
- r_quality_discipline_split_kernel: per-step composition + warm count
- alpha_split_producer_kernel: per-step ALPHA_SPLIT update from grad ratio
(gated on warm count to prevent premature formula activation)
3 ISV slots (417 ALPHA_SPLIT, 418 GRAD_NORM_QUALITY, 419 GRAD_NORM_DISCIPLINE)
+ sp15_alpha_warm_count [1] mapped-pinned scratch buffer on the trainer
struct. 4 fold-reset registry entries + dispatch arms (one for the
non-ISV warm-count buffer mirrors the sp11_novelty_hash host_slice_mut
pattern).
Per established Phase precedent: kernels + launchers land first; consumer
migration (per-step launches in training_loop.rs reward composition site)
deferred to a follow-up commit per feedback_no_partial_refactor.
Anchor tests: 2.4 cost_sensitivity + 2.6 regime_silences (Phase 2B
contracts) — green via Phase 3.4 regret + 3.2 cost; this commit lands
the split structure they depend on.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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7e63f83bf0 |
test(sp15-p2b): 17 behavioral tests (Group 1 + Group 2) as #[ignore] contracts
Per spec §7.3 + plan v2 Phase 2B differential table. Each test documents its behavioral contract and its enabling phase. Tests are #[ignore]'d so the pre-commit-hook-gated suite does not fail; per-test #[ignore] is removed by the commit that lands its enabling phase. Group 1 trading behavior (7 tests): 2.1 flat_holds, 2.2 trend_directional, 2.3 mean_revert_reverses, 2.4 cost_sensitivity, 2.6 regime_silences, 2.7 stop_discipline, 2.18 action_latency. Group 2 state/arch grounding (10 tests): 2.8 hold_vs_flat_semantics, 2.9 eval_fold_isolation, 2.13 eval_train_consistency, 2.14 magnitude_uses_ all_buckets, 2.15 fold_transition_stability, 2.16 q_value_bounded, 2.17 gradient_flow_to_all_heads, 2.19 kelly_calibration, 2.20 state_input_ grounding, 2.21 egf_gate_opens (re-export hook for sp14_oracle_tests.rs). Group 3 (Phase 2C — 5 tests) lands paired with Phase 3.5 commits. Harness invocations use trainer = () placeholder; Phase 2B.b extends BehavioralResult/harness with per-bar actions, position-state inspection, forced-action stepping, and per-head grad-norm snapshots. Each test's ignore reason references which Phase X enabling work + harness extension makes it green. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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ef373c34d7 |
feat(sp15-p1.7): consume the abandoned walk-forward test slice (stash + observer; eval invocation deferred)
Per spec §6.7. The walk-forward generator emits `test_start..test_end` per fold but the trainer at `mod.rs:1294` only consumed train+val — the 12.5% test slice was silently dropped, the model was never measured on held-out data the train/val pipeline didn't see. This commit lands the foundation: `set_test_data_from_slices` stashes the per-fold range immediately after `set_val_data_from_slices`, gated on `fold.test_end > fold.test_start` for defensively-empty slices. A `set_test_data_observer` hook lets unit tests verify the wiring without spinning up a full GPU eval pipeline. The actual `evaluate_dqn_graphed` invocation against the stashed slice plus the per-fold `HEALTH_DIAG test_slice fold=K test_sharpe_net=...` emit is deferred to a follow-up commit per `feedback_no_partial_refactor`. Wiring it through requires either standing up a second `GpuBacktestEvaluator` instance (parallel to the val one at `metrics.rs:550`) or refactoring the existing val evaluator to swap window data between val and test eval — the val evaluator's lazy-init path is fundamentally tied to the window passed at construction. Plus TLOB weight sync, ISV signal wiring, and a `training_mode` toggle (no such field exists yet on `DQNTrainer`). This deferral matches the Phase 1.5 (kernel + launcher first, trunk consumer follow-up) and Phase 1.6 (stash dev/holdout slices, eval consumer follow-up) precedents on this branch. The stash + observer surface is the analogous foundation; the L40S smoke once Task 1.7.b lands will surface the per-fold `test_sharpe_net` HEALTH_DIAG line as the canonical end-to-end verifier. New oracle test `set_test_data_from_slices_fires_observer_and_stashes` in `sp15_phase1_oracle_tests.rs` constructs a real trainer (sync init, no GPU forward), registers an observer, exercises the API with a synthetic [5000..6000) range, asserts the observer fires once with the right bounds. Passes locally on RTX 3050 Ti. `docs/dqn-wire-up-audit.md` extended with a Phase 1.7 entry documenting what landed, what's deferred, the wire-up locations, and the rationale. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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ce019c72d2 |
feat(sp15-p1.6): --holdout-quarters + --dev-quarters CLI flags + sealed Q1-Q7/Q8/Q9 split
Per spec §6.6 / Q6 train/dev/test split (defaults Q1-Q7 train, Q8 dev, Q9 sealed final test): - DQNHyperparameters: holdout_quarters + dev_quarters (default 1+1) - crates/ml/examples/train_baseline_rl.rs: --holdout-quarters / --dev-quarters CLI flags forwarded to hyperparams (this is the actual training binary; bin/fxt/src/commands/train.rs is a gRPC client and services/ml_training_service/src/main.rs accepts training params via proto not CLI — see audit doc note). - DQNTrainer::train_walk_forward slices training_data BEFORE fold generation; folds run on Q1..Q(9 - holdout - dev) only. - DQNTrainer struct: dev_features/dev_targets/holdout_features/ holdout_targets fields stash trailing slices for end-of-training dev eval and the Phase 4.3 separate eval-only workflow. - debug_assert sealed-slice guard catches future refactors that re-introduce holdout into the training path. Per established Phase 1 precedent (1.1-1.5: kernel/state lands first, consumer wiring deferred to follow-up commit per feedback_no_partial_refactor): CLI plumbing + slicing + dev/holdout storage land in this commit. The post-final-fold dev evaluation call (consumer of dev_features) is deferred to a follow-up commit and will mirror Task 1.7's evaluate_dqn_graphed integration pattern. Phase 4.3 argo-eval-final.sh is the sole legitimate consumer of holdout_features (separate eval-only workflow that does NOT call train_walk_forward). cargo check -p ml --features cuda --example train_baseline_rl: clean cargo check -p fxt: clean (no fxt changes needed; gRPC client only) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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5309d4bee5 |
feat(sp15-p1.5): dd_pct foundational state input concat kernel — LAYOUT FINGERPRINT BREAK
LAYOUT FINGERPRINT BREAK: pre-SP15 checkpoints WILL NOT LOAD after this commit. Greenfield OK per spec Q1. Per spec §6.5: dd_pct (slot 406, written by Task 1.3 dd_state_kernel) gets concatenated to the trunk forward input as the last dim. Eval-time policy SEES drawdown context on every forward pass; Phase 3 teachings can condition on dd_pct directly via state, not just reward modulation. New kernel `dd_pct_concat_kernel.cu` produces a [B, state_dim_padded + 1] buffer whose leading state_dim_padded columns equal the input states_buf and whose +1 last column equals isv[DD_PCT_INDEX=406] broadcast across batch. Pure scatter-copy (no atomicAdd per feedback_no_atomicadd). layout_fingerprint_seed extended with 'TRUNK_INPUT_DD_PCT=sp15_phase_1_5' marker — FNV1a hash changes; old checkpoints fail to load with the existing layout-mismatch error path (same fail-fast that fired on the SP4 / SP14 layout breaks). Phase 1.5 lands kernel + launcher + layout fingerprint marker + GPU oracle test only. Trunk consumer migration (re-pointing forward_online to consume the concat buffer + bumping s1_input_dim from 48 → 49 + propagating through GRN encoder, VSN gate input, bottleneck path, and backward dx scratch) is deferred to a follow-up atomic commit per feedback_no_partial_refactor — matches the established Phase 1.1-1.4 precedent (kernels + launchers verify in isolation first; consumer migration is a load-bearing change touching the GRN encoder, VSN partition boundaries, fxcache schema, and backward gradient flow). GPU oracle test `dd_pct_concat_kernel_writes_last_column` validates B=4, raw state_dim=48, state_dim_padded=128: leading 128 columns of each output row match the input states (including pad zeros), and the 129th column equals isv[DD_PCT_INDEX]=0.42 broadcast across all 4 rows. Test passes on local RTX 3050 Ti (sm_86) in 1.62s. cargo test -p ml --lib --features cuda: 945 passed / 14 failed — same 14 failures pre-existing on the parent commit `c6fd4b4b2` (Task 1.4 partial baseline); zero introduced by this commit. Per spec §6.5 step 7 (trunk-grounding behavioral test): Phase 4 L40S smoke verifies dd_pct propagation at production scale via the existing layout-fingerprint-mismatch fail-fast on cold-start of any pre-SP15 checkpoint. The follow-up Phase 1.5.b commit that lands the consumer migration adds the explicit trunk-grounding KL test alongside the forward_online wiring. Touched: - crates/ml/src/cuda_pipeline/dd_pct_concat_kernel.cu (new) - crates/ml/build.rs (+1 cubin manifest entry) - crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs (+SP15_DD_PCT_CONCAT_CUBIN + launch_sp15_dd_pct_concat + TRUNK_INPUT_DD_PCT layout fingerprint marker) - crates/ml/tests/sp15_phase1_oracle_tests.rs (+1 GPU oracle test) - docs/dqn-wire-up-audit.md (+1 Phase 1.5 entry) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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c6fd4b4b2a |
feat(sp15-p1.4-partial): 4 constant-policy baselines (buyhold, hold_only, momentum, reversion)
Per spec §6.4. Pure-CUDA kernels in baseline_kernels.cu — single cubin, 4 extern "C" __global__ functions sharing a templated compute_baseline_sharpe helper. Trunk-shared baselines (random_dir_kelly slot 411, aux_only slot 413, mag_quarter_fixed slot 414, trail_only slot 415) deferred to Task 1.4.b follow-up — they need partial-policy-forward access from the main eval pass. ISV slots written: 409 (buyhold), 410 (hold_only), 412 (naive_momentum), 416 (naive_reversion). Slots 411/413/414/415 stay at sentinel 0.0 until follow-up commit. Per established Phase 1 precedent: kernels + launchers land first; per-eval-pass launches + HEALTH_DIAG baseline_deltas emit deferred to follow-up commit per feedback_no_partial_refactor. Anchor tests: buyhold positive on +drift, hold_only emits 0, momentum + reversion sum near zero on mean-reverting series. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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9e84602486 |
feat(sp15-p1.3): drawdown state kernel — DD_CURRENT/MAX/RECOVERY/PERSISTENCE/CALMAR/PCT
Per spec §6.3. Per-step kernel reads PS_PEAK_EQUITY (slot 7) and
PS_PREV_EQUITY (slot 9) from existing position state buffer (no new
equity slot needed). Writes 6 ISV slots (401-406). Calmar uses
max(dd_max, 1e-4) floor — eliminates the saturation-at-100 artifact
seen in train-dd4xl HEALTH_DIAG.
6 fold-reset registry entries + dispatch arms. 5 sentinel-0 stateful
outputs; calmar uses sentinel 1e-4 (same value as the kernel's floor)
so cold-start division uses the floor rather than ±inf.
Atomic split per feedback_no_partial_refactor.md (mirrors Task 1.1 +
1.2 precedent): kernel + launcher + registry land here; per-step
production wire-up + HEALTH_DIAG composer deferred to a follow-up
commit. Test 1.3 oracle on 6-step synthetic equity curve passes
locally on RTX 3050 Ti (sm_86) in 1.61s. cargo test -p ml --lib
--features cuda: 946 passed / 13 failed — same 13 pre-existing
failures as Task 1.2 baseline (
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jgrusewski
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a92ff28a98 |
feat(sp15-p1.2): cost-net sharpe kernel — commission + spread + OFI-impact
Per spec §6.2 per-side semantics:
cost_t = commission_per_rt × rt_ind[t]
+ half_spread[t] × |pos[t]| × side_ind[t]
+ ofi_lambda × |pos[t]| × |ofi[t]| × side_ind[t]
Commission charged at close; half-spread × |pos| at entry AND exit
(sums to one full spread per RT); OFI impact same per-side. Initial
λ=2.0e-4 in ISV[OFI_IMPACT_LAMBDA_INDEX=407] as Invariant-1 anchor
(constructor-write + FoldReset rewrite per feedback_isv_for_adaptive_bounds);
per-fold ISV refit may overwrite in later phases. Mean cost-per-bar
emitted to ISV[COST_PER_BAR_AVG_INDEX=408] (stateful kernel output;
FoldReset sentinel 0 + Pearl A first-observation bootstrap).
Same kernel reads LobBar fields from synthetic markets (Phase 2A) and
real fxcache LOB (prod) — dev/prod parity per Q3.
Phase 1.2 lands kernel + launcher + anchor seed + 2 registry entries
+ 2 dispatch arms only; consumer migration deferred to a follow-up
commit per feedback_no_partial_refactor (mirrors Phase 1.1 atomic
pattern). Oracle test cost_net_sharpe_round_trip_charges_full_spread
validates single round-trip cost = 2.00 / 10 bars = 0.20/bar with
mean_pnl_net = 0.80 on 1.69s RTX 3050 Ti (sm_86). Zero regressions
introduced (946 passed / 13 pre-existing failures, same as Task 1.1).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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3667cd1b04 |
feat(sp15-p1.1): unified sharpe kernel — single formula for train and val
Replaces sharpe_ema (per-batch EMA, train) vs sharpe_annualised (val × sqrt(525600)) split. Single GPU kernel computes mean/std/sharpe via 2-pass block-tree-reduce; annualisation at the call site. Per feedback_no_partial_refactor: consumer migration in metrics.rs / training_loop.rs deferred to a follow-up commit; kernel + launcher land in isolation first. Verified via 2 GPU oracle tests (unified_sharpe_kernel_zero_mean, unified_sharpe_kernel_positive_drift) passing on local RTX 3050 Ti (sm_86) in 1.78s. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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dff6e666ee |
feat(sp15-p2a.2): oracle policies + evaluator harness + pre-commit hook
Phase 2A scaffolding complete (per spec §7.2): - oracle.rs: OracleAction enum + 3 oracle policies (flat, drift, OU) - harness.rs: BehavioralResult + evaluate_policy_on_market stub. Trainer-side methods (eval_actions_on_features, read_isv_for_test) are documented gap #7; Phase 2B tests add them per-test as needed. - pre-commit hook: cargo test -p ml --test behavioral_suite gates argo-train.sh per spec §4.5 discipline rule. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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7d0a29dced |
feat(sp15-p2a.1): LobBar canonical ABI + 4 synthetic market generators
Phase 2A scaffolding lands FIRST per spec §4.4 ABI contract. Phase 1.2 cost kernel reads LobBar; both dev synthetic and prod fxcache produce LobBar — dev/prod parity per Q3. Generators: flat_market, drift_market, ou_market, regime_switch_market (seeded RNG for reproducible tests). Regime-switch test uses sticky 0.99/0.01 transitions (true regime persistence; spec's 50/50 was a random walk, not a regime switch — corrected with code comment). behavioral_suite test target wired into Cargo.toml; will run all 22 Phase 2 tests once they land in Phase 2B/2C. Audit doc: SP15 Phase 2A.1 entry appended to docs/dqn-wire-up-audit.md per Invariant 7 (component changes require audit-doc update). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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04ea5a0243 |
test(sp15-p1.0): scaffold sp15_phase1_oracle_tests.rs for Phase 1
Empty mod gpu placeholder; Phase 1 tasks 1.1-1.7 will append per-task oracle tests. No tests yet — file just must compile. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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c146c4fffd |
feat(sp15): scaffold sp15_isv_slots.rs with 46 slots [397..443) — ISV_TOTAL_DIM 396→443
Per spec §4.3 allocation map. Pre-allocates disjoint slot ranges to enable Approach B parallel sub-worktrees without index collisions: - Phase 0.B EGF retune: [397..401) - Phase 1.3 drawdown: [401..407) - Phase 1.2 cost: [407..409) - Phase 1.4 baselines: [409..417) - Phase 3.X-3.5.X teachings + recovery: [417..441) - Phase 3.5 deferred anchors: [441..443) Layout fingerprint extended with all 46 slot names. Pre-SP15 checkpoints will be incompatible (greenfield OK per Q1). Two regression tests verify: (1) every slot < ISV_TOTAL_DIM, (2) layout fingerprint locked at named indices. docs/isv-slots.md gets the SP15 section documenting the allocation map + greenfield sub-worktree plan. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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35935ae441 |
plan(sp15): fix 3 critical compile-breakers from third review
Targeted fixes per user direction (option 3 of "fix critical only, accept rest as execution-time gaps"): 1. build.rs cubin manifest is 1:1 source-to-cubin (verified: list of .cu filenames, NOT (source, name) tuples). Fixed Phase 3.1 Step 5 to use single manifest entry; both kernels load from SAME module via get_function() with their symbolic names. 2. egf_anchor_p1 helper in sp4_histogram_p99.cuh: replaced the `return 0.0f` stub with the full ~80-line body. Pass 1 + Pass 2 byte-identical to sp4_histogram_p99 (mirrored verbatim from the existing sibling). Pass 3 walks cumulative-from-bottom for p1 instead of cumulative-from-top for p99. Returns lower-edge of the first bin reaching 1% threshold. 3. Added Task 4.2.5: `fxt evaluate` subcommand (PREREQUISITE for 4.3). Verified that bin/fxt/src/main.rs Commands enum has no Evaluate variant. Without this task, eval-final-template.yaml fails at runtime. Full subcommand shown: bin/fxt/src/evaluate.rs with 5 flags (--checkpoint-dir, --quarter, --seeds, --output-dir, --report-card-md), report card markdown emitter per spec §10.5. 5 IMPORTANT and 2 NIT issues from review remain documented as execution-time friction; subagent-driven-development's spec-compliance reviewer between tasks is expected to catch them per-task. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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eb5e19d670 |
plan(sp15): rewrite v2 — fix all 16 reviewer-flagged issues
Rewrite of 2026-05-06-sp15-trader-discipline-and-recovery.md from v1 (commit |
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jgrusewski
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0178a53ab0 |
plan(sp15): trader discipline and recovery implementation plan
Implementation plan for SP15 spec at docs/superpowers/specs/2026-05-06-trader-
discipline-and-recovery-design.md (commit
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jgrusewski
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5417e27567 |
docs(sp15): amend spec v2 — 10 fixes from second critical review
Second critical review pass found 10 more issues, 3 critical. All addressed: CRITICAL: - §8.2 (3.1): ALPHA_SPLIT cold-start was unspecified — formula produces 0/0=0, not the claimed 0.5 sentinel. Now: ISV slot initialized DIRECTLY to 0.5 in trainer constructor; formula takes over only after both grad-norm EMAs accumulate N_warm non-zero observations - §9.2 (3.5.4): plasticity now performs TWO-STEP recovery: (1) Flat all positions at fire bar (close current losing trade), (2) engage warmup cooldown forcing Hold for M_warm bars. Without step 1, forced Hold preserved the losing position that drove drawdown for the entire 200-bar warmup - §12.2: stale "5-10%" baseline cost estimate updated to "15-25%" matching §6.4 (was contradicting earlier amendment) IMPORTANT: - §9.2 (3.5.5): DD_TRAJECTORY_DECREASING threshold 0.02 hardcoded → ISV-driven via new slot DD_TRAJECTORY_FLOOR (slot 441, 25th percentile of running dd_pct distribution) - §8.2 (3.5): HOLD_FLOOR_ALPHA tracked from rolling 95th percentile of |Q_dir| (NOT running max — was outlier-ratchet vulnerable) - §9.2 (3.5.3): MEDIAN_STREAK_LENGTH formerly undefined in cooldown K formula → ISV-driven via new slot 442, running median of observed loss-streak lengths via two-heap algorithm - §9.2 (3.5.2): asymmetric reward × α split compound interaction explicitly stated as intentional with POS_CAP as binding ceiling NIT: - §7.4: "2C: Group 3 (4 tests)" → "(5 tests)" (was off-by-one after 2.22 added) - §9.2 (3.5.4): Xavier → Kaiming-He init for advantage head reset (architecturally appropriate for ReLU-gated activation chain) ISV_TOTAL_DIM: 441 → 443 post-SP15 (added DD_TRAJECTORY_FLOOR and MEDIAN_STREAK_LENGTH at slots [441..443)). 46 SP15 slots total. File: 799 → 811 lines. Spec is now consistent end-to-end with no contradictions between sections, no hardcoded values violating feedback_isv_for_adaptive_ bounds, and no underspecified load-bearing parameters. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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f3cb0c78c2 |
docs(sp15): amend spec — 14 fixes from critical review
Critical review (combined fresh-eyes subagent + self-critique) flagged 14 issues. All addressed in this amendment. CRITICAL (blocks implementation): - §4.3 NEW: ISV slot allocation map [397..441) per phase, prevents parallel-dispatch ISV-table conflict (was: undefined, would break Approach B) - §4.4 NEW: Phase 2A ↔ Phase 1.2 ABI contract (LobBar struct as canonical contract, Phase 2A defines first; Phase 1.2 conforms). Restores parallelism dependency - §9.2 (3.5.4): plasticity injection now MANDATES cooldown engagement via PLASTICITY_WARM_BARS_REMAINING slot 438. NEW anchor test 2.22 plasticity_cooldown_interlock prevents random-tail-output retrigger loop - §9.2 (3.5.5): recovery curriculum replaced episode-level metadata (didn't exist in transition-level PER) with per-step DD_TRAJECTORY_ DECREASING signal — same goal, no PER restructure IMPORTANT (rework prevention): - §9.2 (3.5.3): cooldown K threshold from running mean of per-trade PnL (NOT variance — variance is LOW during streaks, would delay cooldown when needed) - §8.2 (3.5): Hold floor function form specified as bounded sigmoid with α/k/ε₀ ISV-driven; was "monotonic_inv_func" (undefined family) - §6.2: cost kernel per-side semantics explicit. Half-spread × side_ indicator at entry AND exit; commission_per_rt on close. Resolves round-trip vs per-side ambiguity - §6.2: OFI impact λ initial value 2e-4 + ISV refit methodology; was "empirical fit from MES historical" (hand-wavy) - §6.4: 8 baselines now mandate shared trunk forward; honest 15-25% overhead estimate (was 5-10%, optimistic) - §12.3: Q9 burn policy explicitly honor-system, not enforcement. Mitigations described as deterrents not enforcement - §10.6: Phase 4.5 thresholds CLI-config-driven with rationale, anchored empirically post-Phase-1 (was hardcoded > 1.0) NIT: - §9.2 (3.5.2): multiplier vs SP12 cap interaction explicit (applied BEFORE cap) - §8.2 (3.1): α=0.7 hardcoded → ISV-driven from grad ratio (was feedback_isv_for_adaptive_bounds violation) - §13: pearls reframed as candidates pending validation per discipline rule; pre-naming pressure removed Test count: 21 → 22 (added 2.22). Phase 2 LOC: 2000 → 2100. ISV_TOTAL_DIM: 396 → 441 post-SP15. All 14 issues addressed in spec text. Ready for user review. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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fb5f2394d0 |
docs(sp15): trader discipline and recovery design spec
Design spec for SP15 — addresses the train-dd4xl downward spiral post-mortem (8 epochs, trades 131k→64k, sharpe 79→44 with monotone descent across active_frac, dir_entropy) and the walk-forward audit finding (test_start..test_end slice generated but never consumed, val IS the selection set, no sealed test). Six phases over ~13-21 days: - Phase 0: SP14 EGF ISV-driven retune (gate1=closed forever fix) - Phase 1: honest numbers — unified sharpe kernel, cost-net (commission + spread + OFI-impact, dev/prod parity), drawdown reporting, 8 counterfactual baselines, dd_pct as foundational state input, --holdout-quarters/--dev-quarters CLI, consume abandoned test slice - Phase 2: 21 behavioral tests on dev RTX 3050 Ti, pre-commit hook gates argo-train.sh - Phase 3: 5 trader teachings (r_quality/r_discipline split, explicit cost, quadratic DD, regret, confidence-aware Hold floor) - Phase 3.5: 4 recovery mechanisms (asymmetric reward under DD, cooldown gate, plasticity injection, recovery curriculum in PER) - Phase 4: L40S walk-forward Q1-Q7, Q8 final dev, sealed Q9 OOS Cross-cutting discipline rule: no new pearl/controller/kernel/ISV slot/reward term ships without a Phase 2 behavioral test that proves the intended trader behavior. Hard rule, no exceptions. Decisions captured from 7 clarifying questions answered 2026-05-06. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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0275a25d9f |
Merge SP11/12/13/14 implementation chain into main
SP11 reward-as-controlled-subsystem: B1b z-score normalization for
magnitude-asymmetric weight ratios; popart-component magnitude slot.
SP12 v3: per-trade event-driven reward (asymmetric pos/neg cap +
min-hold target + zero per-bar dense shaping).
SP13 Layer B: K=1→2 softmax CE aux head + i32 replay buffer ring +
GpuBatchPtrs plumbing + scale-free MSE bridge for ISV[117].
SP14 Layer A+B: 3 stability fixes (C51 inv_a_std floor lift, set_aux_weight
clamp, stagnation warmup gate) + Earned Gradient Flow pearl wired through
alpha_grad_compute / q_disagreement_update / gradient_hack_detect /
dir_concat_qaux / scale_wire_col kernels + ISV_TOTAL_DIM bus fix
(383→396) + warmup_gate delete (variance-driven k_aux/k_q handles
warmup intrinsically).
Smoke A2-B PASSED. 8-epoch train-dd4xl L40S validation revealed:
- Walk-forward test_start..test_end slice generated but never consumed
(val IS the selection set; no sealed test).
- Downward-spiral pathology: trades 131k→64k, active_frac 0.48→0.17,
sharpe_ann 79→44 across 8 epochs.
SP15 (trader-discipline-and-recovery) addresses both: honest cost-aware
metrics on Q1-Q7/Q8/Q9 split, behavioral test suite on dev RTX 3050 Ti,
DD-state foundational input, recovery dynamics inc. plasticity injection.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
# Conflicts:
# docs/superpowers/specs/2026-05-04-sp11-reward-as-controlled-subsystem.md
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jgrusewski
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c0fc28e455 |
fix(sp14): delete warmup_gate — let variance-driven k_aux/k_q handle warmup (ISV-driven)
Per `feedback_isv_for_adaptive_bounds`, the hardcoded `warmup_gate = (fold_step_counter / WARMUP_STEPS_FALLBACK).min(1.0)` ramp violated the rule: adaptive bounds in ISV, never hardcoded constants. The variance-driven k_aux/k_q sigmoid steepness already provides warmup behavior intrinsically: - High variance (cold-start, EMAs still moving) → k → K_MIN → flat sigmoid → gate ≈ 0.5 regardless of input. That IS the warmup. - Low variance (settled) → k → K_BASE → sharp sigmoid → gates respond correctly to driver signals. Adding a separate hardcoded step-counter multiplier on top was double-counting + tuning-driven (the 1000-step threshold had no principled basis). Removed entirely. Removed (per `feedback_no_partial_refactor`, all atomically): - `WARMUP_STEPS_FALLBACK` constant in `sp14_isv_slots.rs` - `warmup_gate: f32` parameter in `alpha_grad_compute_kernel.cu` - `gate1 * gate2 * warmup_gate` → `gate1 * gate2` in kernel - `warmup_gate` arg from `launch_sp14_alpha_grad_compute` - `fold_step_counter: usize` field on the trainer struct - `fold_step_counter = 0` reset in `reset_for_fold` - `fold_step_counter` init in trainer constructor - `let warmup_gate: f32 = 1.0;` and `.arg(&warmup_gate)` from B.4 oracle tests (4 launches: 2 in alpha_grad_schmitt_hysteresis, 20 in alpha_grad_adaptive_beta loop) Build: clean, 18 warnings (pre-existing baseline). Tests: cargo test --no-run on sp14_oracle_tests succeeds. Net result: EGF gate's warmup behavior now lives entirely in the variance-driven k_aux/k_q sigmoid steepness controller (ISV slots 388/var_aux, 389/var_q). No hardcoded step counter. Honors `feedback_isv_for_adaptive_bounds` and `pearl_controller_anchors_isv_driven`. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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60ad42676e |
fix(sp14): bump ISV_TOTAL_DIM 383 → 396 to cover SP14 EGF slots
ROOT CAUSE of L1+L2 from Smoke A2-B: the ISV bus was sized for top of SP13 (ISV_TOTAL_DIM=383) but B.1 allocated SP14 slots at 383-395. Every SP14 read/write was OUT-OF-BOUNDS memory access. That's why: - gate1 (slot 391) read as 0 always (OOB zero-init memory) - post_open_min (slot 394) accumulated garbage values 9.5 → 28 → 46 - α_smoothed/α_raw values appeared to work but were undefined behavior SP4/SP5 had a regression test (`all_sp4/5_slots_fit_within_isv_total_dim`) that catches this exact failure mode at unit-test time. SP14 was missing it — that gap let the bug ship across all 16 commits without being caught. Changes: - ISV_TOTAL_DIM: 383 → 396 (covers SP14 slots 383-395) - layout_fingerprint_seed: extended with SP14 slot names + new ISV_TOTAL_DIM=396 marker (forces fingerprint hash bump per Invariant 8 — old checkpoints invalidated correctly) - sp14_isv_slots.rs: 2 regression tests (mirror SP4/SP5 patterns) Both tests pass. After this fix, SP14 EGF kernels will read/write the correct slots; gate1 should actually flip open when aux_dir_acc crosses target+0.03; gradient_hack_detect post_open_min stays bounded in [0, 1] as designed. NOT yet addressed (separate follow-up): - warmup_gate hardcoded WARMUP_STEPS_FALLBACK=1000 violates feedback_isv_for_adaptive_bounds. Should be ISV-signal-driven OR removed entirely (k_aux/k_q already provide variance-driven warmup). Redesign post-re-smoke once bus-size fix is verified. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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976ab4bf1a |
docs(sp14): Smoke A2-B PASSED — Layer A+B chain validated, 2 EGF bugs flagged
Workflow smoke-test-z2kt7 on commit
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jgrusewski
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26343cd573 |
docs(sp14): Layer A+B close-out — full chain summary pre-Smoke-A2-B
Adds a Layer A+B close-out section to dqn-wire-up-audit.md summarizing
all 15 commits in the SP14 chain (3 Layer A stability fixes + 12 Layer B
EGF pearl tasks).
Includes:
- Commit-by-commit table with SHA + task ID + summary
- Architectural summary post-Layer B (forward + backward + α_grad pipeline)
- 8 explicit kill criteria for Smoke A2-B (per spec B.7)
- B.13 skip rationale (per-kernel oracle tests cover unit behavior;
B.14 smoke is the real integration test)
Layer B effective end:
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jgrusewski
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e41dbb7d8a |
diag(sp14 B.12): per-epoch pearl_egf_diag HEALTH_DIAG emit
Adds a new HEALTH_DIAG[{epoch}]: pearl_egf_diag line immediately after
the aux_moe block in the per-epoch metrics section of training_loop.rs.
Reads all 13 SP14 ISV slots [383..396) — α_smoothed, α_raw, β, k_aux,
k_q, var_aux, var_q, var_α, q_dis_short, q_dis_long, gate1 state,
post_open_min, lockout — via the established read_isv_signal_at pattern,
giving forensic visibility into EGF pearl state each epoch.
gate1/gate2 sigmoid outputs are intentionally omitted: recomputing them
host-side would violate feedback_no_cpu_compute_strict; the sigmoid
inputs are sufficient for a reader to infer the output values.
docs/isv-slots.md updated (Invariant 7): records B.12 HEALTH_DIAG wire-up.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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jgrusewski
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857722e774 |
feat(sp14): B.11 — orchestrator wire-up for 3 EGF producer kernels + var_aux gap closure
Per-step launches (in graph capture order): 1. Forward (existing) 2. Action select (existing) → q_dir_logits available 3. launch_sp14_q_disagreement_update → ISV[383, 384, 389] 4. launch_sp14_alpha_grad_compute → ISV[385..395] (consumes q_disagreement) 5. Backward (existing) — wire-col scale at B.10 reads ISV[393] Per-epoch launch (end of epoch): 6. launch_sp14_gradient_hack_detect → circuit breaker α_short=0.3, α_long=0.05, α_var=0.05 per spec; warmup_gate derived from steps_in_fold / WARMUP_STEPS_FALLBACK. Var_aux producer gap closed (option C from B.4): alpha_grad_compute_kernel now also writes ISV[VAR_AUX_INDEX=388] via Welford EMA against (aux_dir_acc_short - aux_dir_acc_long). Adaptive k_aux is now functional (was degenerate at K_BASE_AUX=20.0 constant pre-B.11). Closes the "adaptive_k_aux currently degenerate" concern flagged in B.4 commit. After this commit, the EGF pearl is FULLY ACTIVE end-to-end: - Forward: aux signal feeds direction Q-head input (B.8/B.9) - Backward: wire-col gradient gated by α_grad_smoothed (B.10) - Producers: α_grad computed every step from real driver signals (B.11) - Pre-B.11 force-closed gate (sentinel 0.0) → post-B.11 responsive gate Build clean: 18 warnings pre-existing baseline, 0 new. Tests: 4/4 P0b aux_w tests pass (no regression). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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dc3f948ee9 |
feat(sp14): B.10 — backward wire gradient gating by ALPHA_GRAD_SMOOTHED
Critical safety mechanism that completes the EGF pearl: scales the wire
column of `dL/dx_concat [B, SH2 + 1]` (the gradient flowing FROM the
direction Q-head's first FC SGEMM TO `aux_softmax_diff`) by
`ISV[ALPHA_GRAD_SMOOTHED_INDEX = 393]`, computed by B.4's
`alpha_grad_compute_kernel` and orchestrated per-step in B.11.
`dL/dW[wire_col]` (Q-head's own weight gradient for the appended column)
is NOT scaled — the dW SGEMM `dY^T × x_concat` and the dX SGEMM
`dY × W^T` are independent, so scaling `dx[:, SH2]` AFTER both have
completed leaves dW unaffected. Q-head learns to USE the wire freely;
only the gradient PROPAGATING BACK to aux is gated.
Pre-B.11 (no producer wired) `ISV[393]` holds sentinel `0.0` →
wire force-closed (gradient zeroed) — the conservative safety state.
Post-B.11, B.4 writes the live gate output ∈ [0, 1] each step.
Closes the latent K-mismatch B.8/B.9 left in backward
============================================================
B.8 grew `w_b0fc` to `[adv_h, SH2 + 1]` end-to-end (Adam m/v +
spectral-norm vector + smoke fixtures); B.9 closed the forward dispatch
K-mismatch. The backward dW/dX SGEMMs for `d == 0` still used `K = SH2`
against the new `LDA = SH2 + 1` weight tensor — silently dropping the
last column of dW and zeroing the wire-col gradient. B.10 closes that
gap atomically with the wire-col scale per `feedback_no_partial_refactor`:
* `backward_branch_dw` for `d == 0` now uses `(dir_qaux_concat_ptr, SH2 + 1)`
instead of `(save_h_s2, SH2)` — matching the forward consumer
pattern from B.9.
* `backward_branch_dx` for `d == 0` now writes to
`d_dir_qaux_concat [B, SH2 + 1]` with `K = SH2 + 1` instead of
`scratch_d_h_s2 [B, SH2]` with `K = SH2`. Mirrors the magnitude
branch's wider-buffer pattern.
New artifacts
=============
* `sp14_scale_wire_col_kernel.cu`: one thread per batch row, scales
`dx_concat[b, SH2]` by `isv[393]` IN-PLACE. NaN-safe per the
`dqn_scale_f32_kernel` precedent (explicit `α==0 ⇒ 0` branch).
Pure per-thread map, no atomicAdd, no shared memory.
* `sp14_d_dir_qaux_concat: CudaSlice<f32>` `[B, SH2 + 1]` trainer-
struct field. Dx SGEMM destination; the wire-col scale acts on
this buffer; the strided accumulator copies the first SH2 columns
into `bw_d_h_s2` after the scale.
* `launch_sp14_scale_wire_col` launcher reads `self.isv_signals_dev_ptr`
and the new buffer's raw_ptr.
* `backward_full` signature grows two trailing `u64` args
(`dir_qaux_concat_ptr`, `d_dir_qaux_concat_ptr`); both
`backward_full` call sites (CQL aux + main online) wired
atomically per `feedback_no_partial_refactor`.
Post-call orchestration at trainer level
========================================
1. `launch_sp14_dir_concat_qaux(save_h_s2)` rebuilds the ONLINE
concat in `sp14_dir_qaux_concat_scratch` (the forward pass had
overwritten it with the TARGET concat at line ~25817). Same
one-step-lag semantic preserved — `aux_nb_softmax_buf` is
unchanged between forward and backward.
2. `cuMemsetD32Async` zero of `d_h_s2` — pre-B.10 the direction
branch (d==0) wrote it with beta=0; post-B.10 the dir-Q dX
lives in `d_dir_qaux_concat` and is gated + accumulated AFTER
`backward_full` returns, so the value-FC dx accumulator inside
`backward_full` (beta=1) needs an explicit zero baseline.
3. `backward_full` runs: dir branch → `d_dir_qaux_concat`,
mag/ord/urg branches → their concat dX buffers, value-FC →
`d_h_s2` (beta=1, on top of zeroed buffer).
4. `launch_sp14_scale_wire_col` gates col SH2 of `d_dir_qaux_concat`.
5. `accumulate_d_h_s2_from_concat` (beta=1) copies first SH2 cols
of `d_dir_qaux_concat` into `d_h_s2`. Wire col stays in
`d_dir_qaux_concat[:, SH2]`, untouched by this accumulator (its
destination range is [0, SH2)). Pre-B.11 the wire is already
zeroed by the sentinel-α gate; the orchestrator that propagates
the gated wire-col gradient back to the aux head's softmax CE
backward chain lives in B.11.
6. mag/ord/urg accumulators continue with beta=1 (comments updated).
Wire status
===========
* Forward dispatch: unchanged (B.9-complete).
* Backward dispatch: GATED on both call sites (CQL aux + main online).
* dW unchanged: the `dW = dY^T × x_concat` SGEMM writes
`grad_buf[goff_w_b0fc..]` BEFORE the scale-wire-col launches;
the scale operates ONLY on `d_dir_qaux_concat` (the dx buffer)
AFTER both dW and dX SGEMMs complete.
* Target net unaffected: Polyak EMA-only, no backward.
* CudaSlice wrapper path: passes `0u64` for both new args, falls
back to the legacy K=SH2 path. Consistent with the forward
wrapper's diagnostic-only residual.
Verified
========
* `SQLX_OFFLINE=true cargo check -p ml` clean, 18 warnings (baseline)
* `cargo test -p ml --test sp14_oracle_tests` 2 passed, 6 ignored (GPU)
* Audit doc `docs/dqn-wire-up-audit.md` updated per Invariant 7.
After this commit, the EGF pearl is architecturally complete; the
orchestration of when/how the alpha_grad gates fire happens in B.11
(producer chain orchestrator).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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ecf4757c0d |
feat(sp14): B.9 — wire forward concat into direction Q-head SGEMM
Closes the latent SGEMM K-mismatch left by B.8 (
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jgrusewski
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6715ab4ea1 |
feat(sp14): B.8 — direction Q-head input dim SH2 → SH2+1 + fingerprint
Forward wire (weight-side only — dispatch consumer lands in B.9): direction Q-head's first FC weight tensor `w_b0fc` (param-table index 17) input dim grows by 1 to accept aux_softmax_diff. The (rows, cols) shape table at the trainer-init Xavier site is updated in lock-step with `compute_param_sizes()`. Output dim (adv_h) and the bias `b_b0fc` are unchanged — bias is per-output, not per-input. `layout_fingerprint_seed()` entry renamed `PARAM_W_B0FC` → `PARAM_W_B0FC_AUX1`, forcing the FNV-1a hash to bump per Invariant 8 (old checkpoints fail-fast at load via `check_layout_fingerprint` instead of silently aliasing onto the new architecture). Per `feedback_no_legacy_aliases`, no `_DEPRECATED` shim — straight in-place rename. New weight column zero-initialised in trainer construction (mirrors the OFI column zeroing for w_b2fc/w_b3fc): the model starts ignoring the new input and learns to use it through gradient descent. Xavier- init on this column would inject day-0 noise the trunk would have to denoise — let the EGF gate decide when the aux signal is trustworthy. Atomic-migration consumers (`feedback_no_partial_refactor`) updated: - `gpu_dqn_trainer.rs` — Xavier (rows, cols) table at index 17 grows to (adv_h, SH2+1); spectral-norm descriptor entry [4] for W_a1 grows in_dim from sh2 to sh2+1; spec_v_a1 power-iteration vector grows from sh2 to sh2+1 floats. - `dqn/smoke_tests/gradient_budget.rs` — both `alloc_dueling` fixtures' slot 8 grow `cfg.adv_h * cfg.shared_h2` → `cfg.adv_h * (cfg.shared_h2 + 1)`. - `docs/dqn-wire-up-audit.md` — new SP14 Layer B B.8 entry per Invariant 7. Note: forward GEMM dispatch still uses `K = shared_h2` until B.9 lands the concat-then-SGEMM consumer (per plan §2358). Until then the new column reads as ignored padding; this is safe because (a) it's zero- initialised, (b) GPU-only smoke tests are skipped on this CPU CI, (c) the fingerprint bump invalidates any pre-SP14 checkpoint that would attempt to load. Test: `layout_fingerprint_bumps_after_sp14_wire` (CPU-only, in `sp14_oracle_tests.rs`) hashes the pre-B.8 seed verbatim with the single difference `PARAM_W_B0FC` (vs post-B.8 `PARAM_W_B0FC_AUX1`) and asserts `LAYOUT_FINGERPRINT_CURRENT` differs — any silent revert of the rename trips this test. Mirrors the `fingerprint_bumped_from_ pre_b1_1a` pattern from `sp13_layer_b_oracle_tests.rs`. Verified: - `SQLX_OFFLINE=true cargo check -p ml` clean, 18 warnings (baseline) - `cargo test -p ml --test sp14_oracle_tests` 2 passed, 6 ignored (GPU) - `cargo test -p ml --test sp13_layer_b_oracle_tests fingerprint_bumped_from_pre_b1_1a` still passes (sister test) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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9843de5e3d |
feat(sp14): B.7 — trainer struct fields for EGF kernels + concat scratch
Adds 4 CudaFunction handles + 1 scratch buffer to GpuDqnTrainer: - sp14_q_disagreement_update_kernel - sp14_alpha_grad_compute_kernel - sp14_gradient_hack_detect_kernel - sp14_dir_concat_qaux_kernel - sp14_dir_qaux_concat_scratch: CudaSlice<f32> [B * (SH2 + 1)] All loaded from precompiled cubins in trainer construction, mirroring the SP13 aux_pred_to_isv_tanh / aux_sign_label kernel-loading pattern. Per feedback_no_partial_refactor: handles + scratch are held but not yet wired in. Subsequent tasks (B.9+) launch them. Build: cargo check --workspace clean. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
|
4527d8c852 |
feat(sp14): B.6 — dir_concat_qaux_kernel (pre-SGEMM forward-wire concat)
Mirrors mag_concat_qdir precedent (experience_kernels.cu:4560). Concats [h_s2 ; aux_softmax_diff] into scratch buffer [B, SH2+1] for the direction Q-head's first FC SGEMM. aux_softmax_diff = softmax[b, 1] - softmax[b, 0] in [-1, +1] computed inline; structurally bounded by softmax components per pearl_bounded_modifier_outputs_require_structural_activation. Pure per-thread map; no reduction; no atomicAdd. Does not read or write ISV slots — purely data-movement. Launch order constraint: aux head forward MUST complete before this concat reads aux_nb_softmax_buf (enforced by orchestrator in B.10/B.11). Test: dir_concat_qaux_correct verifies row-wise contiguous concat + correct softmax diff values for both 'down' (-0.8) and 'up' (+0.8) synthetic aux predictions. B.3+B.4+B.5 regression: 5 GPU tests unchanged (6 total pass). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> |