feat(scripts): cross-asset trend/lead-lag harness (6E/ES/NQ/ZN OHLCV)

Per-instrument time-series momentum + diversified trend portfolio + lead-lag,
honest IS(2024)/OOS(2025) Sharpe on non-overlapping daily P&L.

Verdict on 2y/4-instrument data: diversified trend portfolio IS Sharpe +1.98
(L10) -> OOS -0.50; per-instrument TSMOM sign-flips IS<->OOS; lead-lag ICs <0.11.
No robust edge. Conclusion: 4 instruments x 2y is underpowered by 1-2 orders of
magnitude for systematic edge discovery -- the bottleneck is data/universe, not
model. Real progress needs a broad futures universe + decades, or a less-efficient
order-book market (crypto).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

.gitignore

@@ -7,6 +7,9 @@ test_data/feature-cache/
 /data/feature-cache/
 *.fxcache
 
+# Tier 1.5 mid-smoke local data (symlinks to test_data/futures-baseline-mbp10/)
+test_data/futures-baseline-mid/
+
 # IDE files
 .vscode/
 .idea/

CLAUDE.md

@@ -66,6 +66,24 @@ cargo bench --bench database_performance
 - `SQLX_OFFLINE=true` — compiled SQL queries (no live DB needed for build)
 - `SCCACHE_BUCKET=foxhunt-sccache` — shared compile cache
 
+### Tiered local validation (fast dev cycle)
+
+Three-tier funnel before cluster submit (per `docs/superpowers/specs/2026-06-02-fast-dev-cycle.md`):
+
+| Tier | Setup | Time | What it validates |
+|---|---|---|---|
+| 1 (correctness) | RTX 3050, b=16, 200 steps, 1 file | ~6 sec | Kernel correctness, ISV slots, NaN |
+| 1.5 (behavior) | RTX 3050, b=128, 2000+500 steps, 2 files | ~10 min | entropy, hold growth, controller stability, early Pearson |
+| 2 (eval verdict) | L40S, b=1024, 20k+5k, 9 files | ~70 min | eval pnl, eval wr, regime stratification |
+
+**Tier 1.5 data path**: `test_data/futures-baseline-mid/` (symlinks to existing MBP-10 files for fold-1 train/eval split).
+
+```bash
+./scripts/local-mid-smoke.sh           # Run Tier 1.5 mid-smoke (~10 min)
+./scripts/determinism-check.sh         # Reproducibility self-test (runs mid-smoke twice, diffs final 5 rows)
+python3 scripts/tier1_5_verdict.py /tmp/foxhunt-mid-smoke   # Behavioral kill verdict
+```
+
 ## Deployment (Argo Workflows)
 
 ```bash

Cargo.lock

@@ -6090,7 +6090,6 @@ dependencies = [
  "approx",
  "arrow 56.2.0",
  "bincode",
- "bytemuck",
  "clap",
  "cudarc",
  "data",

bin/fxt/tests/cli_integration_test.rs

@@ -215,10 +215,11 @@ fn test_tune_status_invalid_uuid() {
 #[ignore = "Ignored because it tries to launch terminal UI"]
 fn test_dashboard_command() {
     let mut cmd = Command::cargo_bin("fxt").unwrap();
-    cmd.arg("dashboard")
+    let _ = cmd.arg("dashboard")
         .timeout(std::time::Duration::from_secs(2))
         .assert();
-    // Will timeout or fail trying to connect, but that's expected
+    // Will timeout or fail trying to connect, but that's expected — assert result
+    // intentionally discarded; this test verifies arg parsing reaches launch.
 }
 
 /// Test version flag

crates/data/src/providers/databento/dbn_parser.rs

@@ -699,38 +699,19 @@ impl DbnParser {
                     if let RecordRefEnum::Mbp10(mbp10) = record_enum {
                         update_count += 1;
 
-                        // Phase E.1 fix (2026-05-15): MBP-10 messages carry
-                        // the FULL post-update top-10 book in
-                        // `mbp10.levels: [BidAskPair; 10]` — not just the
-                        // single update event. We copy the full top-10
-                        // here so downstream consumers (OFI, microprice,
-                        // FillModel L2/L3) see real data. Mirror of the
-                        // parse_mbp10_streaming fix in the same file.
-                        let is_bid = mbp10.side == b'B' as i8;
+                        // MBP-10 messages carry the FULL post-update top-10 book
+                        // in `mbp10.levels`; `apply_mbp10_record` overlays all 10
+                        // levels (incl. L0, the inside quote) and bumps
+                        // trade_count on Trade actions. See its doc comment.
                         let action = OrderBookAction::from(mbp10.action as u8);
-
-                        current_snapshot.update_level(
-                            0, // Level index
+                        apply_mbp10_record(
+                            &mut current_snapshot,
+                            &mbp10.levels,
                             action,
-                            mbp10.price,
-                            mbp10.size,
-                            1, // Order count (not available in MBP-10 single update)
-                            is_bid,
+                            mbp10.hd.ts_event,
+                            mbp10.sequence,
                         );
 
-                        let max_lvl = mbp10.levels.len().min(current_snapshot.levels.len());
-                        for lvl in 1..max_lvl {
-                            current_snapshot.levels[lvl].bid_px = mbp10.levels[lvl].bid_px;
-                            current_snapshot.levels[lvl].bid_sz = mbp10.levels[lvl].bid_sz;
-                            current_snapshot.levels[lvl].bid_ct = mbp10.levels[lvl].bid_ct;
-                            current_snapshot.levels[lvl].ask_px = mbp10.levels[lvl].ask_px;
-                            current_snapshot.levels[lvl].ask_sz = mbp10.levels[lvl].ask_sz;
-                            current_snapshot.levels[lvl].ask_ct = mbp10.levels[lvl].ask_ct;
-                        }
-
-                        current_snapshot.timestamp = mbp10.hd.ts_event;
-                        current_snapshot.sequence = mbp10.sequence;
-
                         // Create snapshot periodically to reduce memory
                         if update_count % SNAPSHOT_INTERVAL == 0 {
                             snapshots.push(current_snapshot.clone());
@@ -870,48 +851,23 @@ impl DbnParser {
                         kept += 1;
                         update_count += 1;
 
-                        let is_bid = mbp10.side == b'B' as i8;
+                        // The dbn `Mbp10Msg` carries the full 10-level
+                        // post-update book in `levels: [BidAskPair; 10]`
+                        // (index 0 = inside quote). `apply_mbp10_record` overlays
+                        // ALL levels — including L0 — using the existing 1e9
+                        // fixed-point scale convention, and bumps trade_count on
+                        // Trade actions. Writing the single update event into L0
+                        // (the previous behavior) corrupted the inside quote:
+                        // ~6.4% crossed books, ~10% wide-L0 spikes.
                         let action = OrderBookAction::from(mbp10.action as u8);
-
-                        current_snapshot.update_level(
-                            0,
+                        apply_mbp10_record(
+                            &mut current_snapshot,
+                            &mbp10.levels,
                             action,
-                            mbp10.price,
-                            mbp10.size,
-                            1,
-                            is_bid,
+                            mbp10.hd.ts_event,
+                            mbp10.sequence,
                         );
 
-                        // Phase E.1 fix (2026-05-15): copy the full top-10
-                        // post-update book snapshot from `mbp10.levels[1..]`
-                        // into `current_snapshot.levels[1..]`. Without this,
-                        // levels[1..10] stayed at default-empty, so downstream
-                        // consumers (OFI calculator's L2-L5 reads, microprice
-                        // at `snapshot.levels[1]`, FillModel L2/L3 distributions)
-                        // received zeros for everything below L1. The dbn
-                        // crate's `Mbp10Msg` carries the full 10-level
-                        // post-update book in `levels: [BidAskPair; 10]`;
-                        // previously only the single update event's
-                        // (price, size) was captured (into level 0 via
-                        // `update_level`).
-                        //
-                        // Field-by-field copy preserves the existing scale
-                        // convention (raw 1e9 fixed-point i64; readers apply
-                        // 1e-9 via `BidAskPair::price_to_f64` or local
-                        // `raw_price_to_f32` workarounds).
-                        let max_lvl = mbp10.levels.len().min(current_snapshot.levels.len());
-                        for lvl in 1..max_lvl {
-                            current_snapshot.levels[lvl].bid_px = mbp10.levels[lvl].bid_px;
-                            current_snapshot.levels[lvl].bid_sz = mbp10.levels[lvl].bid_sz;
-                            current_snapshot.levels[lvl].bid_ct = mbp10.levels[lvl].bid_ct;
-                            current_snapshot.levels[lvl].ask_px = mbp10.levels[lvl].ask_px;
-                            current_snapshot.levels[lvl].ask_sz = mbp10.levels[lvl].ask_sz;
-                            current_snapshot.levels[lvl].ask_ct = mbp10.levels[lvl].ask_ct;
-                        }
-
-                        current_snapshot.timestamp = mbp10.hd.ts_event;
-                        current_snapshot.sequence = mbp10.sequence;
-
                         if update_count % snapshot_interval == 0 {
                             callback(&current_snapshot);
                             snapshot_count += 1;
@@ -1289,6 +1245,43 @@ impl DbnParserMetrics {
     }
 }
 
+/// Overlay an MBP-10 record's authoritative post-update book onto `snapshot`.
+///
+/// MBP-10 messages carry the full top-10 book in `levels` (index 0 = inside
+/// quote). We copy **all** levels including L0. A prior version wrote only the
+/// single update event's price into L0 via `update_level(0, …)` and then copied
+/// `levels[1..]`, which left L0 holding the lone event price (typically one side
+/// only) instead of the real inside quote → crossed books and wide-L0 spikes.
+///
+/// `trade_count` is bumped on Trade-action records, preserving the downstream
+/// signal (encoder feature `[17] = log1p(trade_count)` and the inter-snapshot
+/// trade delta in the ml-alpha / ml-features loaders). A trade does not alter
+/// the book structure itself, so only the counter moves.
+fn apply_mbp10_record(
+    snapshot: &mut Mbp10Snapshot,
+    levels: &[dbn::BidAskPair],
+    action: OrderBookAction,
+    ts_event: u64,
+    sequence: u32,
+) {
+    let max_lvl = levels.len().min(snapshot.levels.len());
+    for lvl in 0..max_lvl {
+        snapshot.levels[lvl].bid_px = levels[lvl].bid_px;
+        snapshot.levels[lvl].bid_sz = levels[lvl].bid_sz;
+        snapshot.levels[lvl].bid_ct = levels[lvl].bid_ct;
+        snapshot.levels[lvl].ask_px = levels[lvl].ask_px;
+        snapshot.levels[lvl].ask_sz = levels[lvl].ask_sz;
+        snapshot.levels[lvl].ask_ct = levels[lvl].ask_ct;
+    }
+
+    if action == OrderBookAction::Trade {
+        snapshot.trade_count += 1;
+    }
+
+    snapshot.timestamp = ts_event;
+    snapshot.sequence = sequence;
+}
+
 /// Snapshot of DBN parser metrics
 #[derive(Debug, Clone, Serialize, Deserialize)]
 pub struct DbnParserMetricsSnapshot {
@@ -1348,6 +1341,92 @@ mod tests {
         assert_eq!(parser.get_symbol(999), "UNKNOWN_999");
     }
 
+    /// Regression: the MBP-10 decoder must populate L0 from the authoritative
+    /// `mbp10.levels[0]` (the inside quote), NOT from the lone update event.
+    /// Writing the event into L0 produced crossed/half-empty inside quotes
+    /// (root cause of ~6.4% crossed books + ~10% wide-L0 spikes).
+    #[test]
+    fn apply_mbp10_record_fills_inside_quote_without_crossing() {
+        use dbn::BidAskPair as DbnBidAskPair;
+
+        // Authoritative post-update book: L0 = normal uncrossed inside quote.
+        let mut levels: [DbnBidAskPair; 10] = std::array::from_fn(|_| DbnBidAskPair {
+            bid_px: 0,
+            ask_px: 0,
+            bid_sz: 0,
+            ask_sz: 0,
+            bid_ct: 0,
+            ask_ct: 0,
+        });
+        levels[0] = DbnBidAskPair {
+            bid_px: 5_000_000_000_000, // 5000.00 (×1e9)
+            ask_px: 5_000_250_000_000, // 5000.25 (×1e9)
+            bid_sz: 10,
+            ask_sz: 12,
+            bid_ct: 1,
+            ask_ct: 1,
+        };
+        levels[1] = DbnBidAskPair {
+            bid_px: 4_999_750_000_000,
+            ask_px: 5_000_500_000_000,
+            bid_sz: 7,
+            ask_sz: 9,
+            bid_ct: 1,
+            ask_ct: 1,
+        };
+
+        let mut snap = Mbp10Snapshot::empty("ES.FUT".to_string());
+
+        // A bid-side ADD event priced ABOVE the real ask — the classic
+        // corruptor. Pre-fix code wrote this into L0 and copied only levels[1..].
+        apply_mbp10_record(
+            &mut snap,
+            &levels,
+            OrderBookAction::Add,
+            1_700_000_000_000_000_000,
+            42,
+        );
+
+        assert_eq!(
+            snap.levels[0].bid_px, 5_000_000_000_000,
+            "L0 bid must be the real inside bid, not the event price"
+        );
+        assert_eq!(
+            snap.levels[0].ask_px, 5_000_250_000_000,
+            "L0 ask must be the real inside ask (event never set the ask side)"
+        );
+        assert!(
+            snap.levels[0].bid_px < snap.levels[0].ask_px,
+            "inside quote must not be crossed"
+        );
+        assert_eq!(snap.levels[1].ask_px, 5_000_500_000_000, "L1 still copied");
+        assert_eq!(snap.timestamp, 1_700_000_000_000_000_000);
+        assert_eq!(snap.sequence, 42);
+    }
+
+    /// `trade_count` is a live model feature; only Trade-action records bump it.
+    #[test]
+    fn apply_mbp10_record_counts_only_trade_actions() {
+        use dbn::BidAskPair as DbnBidAskPair;
+
+        let levels: [DbnBidAskPair; 10] = std::array::from_fn(|_| DbnBidAskPair {
+            bid_px: 5_000_000_000_000,
+            ask_px: 5_000_250_000_000,
+            bid_sz: 1,
+            ask_sz: 1,
+            bid_ct: 1,
+            ask_ct: 1,
+        });
+        let mut snap = Mbp10Snapshot::empty("ES.FUT".to_string());
+
+        apply_mbp10_record(&mut snap, &levels, OrderBookAction::Add, 1, 1);
+        assert_eq!(snap.trade_count, 0, "non-trade action must not bump count");
+
+        apply_mbp10_record(&mut snap, &levels, OrderBookAction::Trade, 2, 2);
+        apply_mbp10_record(&mut snap, &levels, OrderBookAction::Trade, 3, 3);
+        assert_eq!(snap.trade_count, 2, "Trade actions must increment trade_count");
+    }
+
     #[test]
     fn test_price_scaling() {
         let parser = DbnParser::new().unwrap();

crates/ml-alpha/Cargo.toml

@@ -33,7 +33,6 @@ tracing-subscriber.workspace = true
 serde = { workspace = true, features = ["derive"] }
 serde_json.workspace = true
 bincode.workspace = true
-bytemuck = { workspace = true }
 thiserror.workspace = true
 clap = { workspace = true, features = ["derive"] }
 

crates/ml-alpha/build.rs

@@ -35,11 +35,15 @@ const KERNELS: &[&str] = &[
     "rl_gamma_controller",           // RL Phase C: ISV controller emitting γ to ISV[RL_GAMMA_INDEX=400]
     "rl_target_tau_controller",      // RL Phase C: ISV controller emitting τ to ISV[RL_TARGET_TAU_INDEX=401]
     "ppo_clipped_surrogate",         // RL Phase D: PPO clipped-surrogate + entropy bonus + value MSE fwd/bwd
+    "ppo_loss_reduce_b",             // F4.1 (2026-05-31): [B] → [1] block tree-reduce mean of per-batch PPO loss + entropy loss (replaces atomicAdd; eliminates l_pi step-count staleness bug — see ppo_clipped_surrogate.cu header)
     "rl_ppo_clip_controller",        // RL Phase D: ISV controller emitting ε to ISV[RL_PPO_CLIP_INDEX=402]
     "rl_entropy_coef_controller",    // RL Phase D: ISV controller emitting entropy bonus weight to ISV[RL_ENTROPY_COEF_INDEX=403]
     "v_head_fwd_bwd",                // RL Phase E.2: scalar V(s) head fwd + MSE bwd (linear layer; per-batch scratch + reduce_axis0)
     "grad_h_accumulate",             // RL Phase E.2: element-wise grad_h_encoder += λ × grad_h_head accumulator (one head at a time, serialised by stream)
     "bellman_target_projection",     // RL Phase E.2-DEFER: C51 categorical projection of Bellman target Z(s_{t+1}, a*) onto the discrete support, reads γ from ISV[400]; replaces host-side build_synthetic_bellman_target stand-in
+    "rl_bellman_target_saturation_reduce", // B-9 (2026-06-01): cross-batch tree-reduce of per-batch saturation tallies from bellman_target_projection / _fused; emits ISV slots 726-729 (top/bot rate + max/min pre-proj)
+    "rl_q_distribution_stats",       // B-10 (2026-06-01) G1: Q-distribution informativeness; two entry points `rl_q_distribution_per_batch` (per-block per-action softmax + entropy + E_Q over online Q logits) + `rl_q_distribution_reduce` (cross-batch tree-reduce → ISV slots 730/731/732)
+    "rl_ppo_diagnostic_stats_reduce",// B-10 (2026-06-01) G3+G4: cross-batch tree-reduce of per-batch advantage + ratio + surrogate scratches written by ppo_clipped_surrogate.cu; reads var_pre_norm slot 612 for σ_used; emits ISV slots 735-742
     "rl_lr_controller",              // RL Phase E.2-DEFER: per-head learning-rate ISV emitter — bootstraps ISV[412..417] with 1e-3 (BCE/Q/π/V/aux); replaces hardcoded PHASE_E2_DEFAULT_LR
     "rl_rollout_steps_controller",   // RL Phase E.3b: rollout-buffer-length ISV emitter — emits ISV[RL_N_ROLLOUT_STEPS_INDEX=404] from var(advantage)/|mean A| EMA; bootstraps 2048
     "rl_per_alpha_controller",       // RL Phase E.3b: PER priority-exponent ISV emitter — emits ISV[RL_PER_ALPHA_INDEX=405] from TD-error kurtosis EMA; bootstraps 0.6
@@ -47,6 +51,8 @@ const KERNELS: &[&str] = &[
     "ema_update_on_done",            // RL Phase R3: generic done-gated EMA producer (slot-parameterised) for closed-trade-magnitude EMAs (mean_abs_pnl, q_divergence, td_kurtosis)
     "ema_update_per_step",           // RL Phase R3: generic per-step EMA producer (slot-parameterised) for continuous EMAs (kl_pi, entropy_observed, advantage_var_ratio, trade_duration)
     "compute_advantage_return",      // RL Phase R3: element-wise A_t = r + γ(1-done)·V(s_{t+1}) − V(s_t), R_t = r + γ(1-done)·V(s_{t+1}); reads γ from ISV[400]
+    "gae_backward_sweep",            // Phase 1B-A (2026-06-02): GAE backward sweep over [B × T] rollout trajectories — A_t = δ_t + γλ·A_{t+1}·non_terminal, returns_t = A_t + V_t; deterministic single-thread-per-batch sequential sweep; replaces compute_advantage_return when wired in Phase 1B-B+
+    "rollout_pack",                  // Phase 1B-B (2026-06-02): per-step f32→u8 dones packer; writes `dones_f32 [B]` into rollout buffer's `dones_u8_bt [B × T]` at offset `b * T + t_cursor`; single-thread-per-batch, deterministic
     "rl_action_kernel",              // RL Phase R4: Thompson sampler over C51 atoms; one block per batch, N_ACTIONS threads; per-batch xorshift32 PRNG state; replaces host Thompson loop per feedback_cpu_is_read_only
     "argmax_expected_q",             // RL Phase R4: argmax over expected Q per action; Bellman-target argmax (Double-DQN); pairs with rl_action_kernel per pearl_thompson_for_distributional_action_selection
     "log_pi_at_action",              // RL Phase R4: per-batch log π(action_b) via log-softmax + lookup; PPO importance-ratio path
@@ -72,8 +78,8 @@ const KERNELS: &[&str] = &[
     "rl_atom_support_update",        // audit 2026-05-24 followup: refreshes atom_supports_d from ISV V_MIN/V_MAX so C51 atom span adapts with reward clamp (Q learning was capped at V_MAX=1.0)
     "rl_kl_reference_grad",
     "rl_q_pi_distill_grad",          // audit 2026-05-24 vj5f6 followup: KL(softmax(E_Q/τ) || π_new) gradient ADDED to pi_grad_logits — couples Q's improved C51 calibration to action selection (was decoupled per Option B)
+    "rl_pi_grad_blend",              // Phase 3D-C (2026-06-03): PPO surrogate × Q-distill blend operator (replaces zero-fill before Q-distill +=); restores direct PG signal to π
     "action_entropy_per_step",       // POST-gate action entropy EMA for SAC α/τ co-tuning
-    "rl_drawdown_stop",              // per-step drawdown penalty + hard stop-loss
     "rl_q_distill_lambda_controller",// audit 2026-05-24 rljzl followup: adaptive λ_distill via Schulman bounded step on KL_EMA vs target
     "rl_unit_state_update",          // SP20 P1+P5 audit fix: per-unit trade state machine — detects open/close/reverse transitions, sets up unit slot 0 entry+trail
     "rl_trail_mutate",               // SP20 P1+P5 audit fix (a7/a8 dead): TrailTighten/TrailLoosen mutate unit_trail_distance bounded MIN/MAX, symmetric reciprocal adjust
@@ -97,6 +103,25 @@ const KERNELS: &[&str] = &[
     "rl_iqn_forward",                // IQN distributional Q-head: quantile embedding + action-value projection; complementary to C51
     "rl_iqn_loss",                   // IQN quantile Huber loss: ρ_τ(δ) = |τ - 1(δ<0)| × Huber(δ, κ=1.0); forward + backward
     "rl_iqn_backward",               // IQN backward through forward pass: grad_output → grad_w_out/b_out/w_embed/b_embed per-batch scratch
+    "rl_dueling_q_forward",                // Phase 4 (2026-05-30): Independent dueling Q head forward — V[B] + A[B,N] + composed_Q[B,N] = V + A − mean_a A; parallel to C51/IQN, zero shared state per spec 2026-05-30-phase4-independent-dueling-head-design.md
+    "rl_dueling_q_bellman_target",         // Phase 4: argmax over target composed_Q + Bellman target = r + γ^n × (1-done) × max_Q
+    "rl_dueling_q_loss_and_grad",          // Phase 4: Huber loss on (target − online_composed_Q[taken]) + grad_composed
+    "rl_dueling_q_decompose_and_bwd",      // Phase 4: decompose grad_composed → grad_V + grad_A via mean-subtraction Jacobian + per-batch weight gradients
+    "rl_v_blend",                          // Phase 4.4 (2026-05-30): elementwise V_used = α V_scalar + (1−α) V_dq, α from ISV
+    "rl_v_blend_alpha_controller",         // Phase 4.4: ISV-adaptive Schulman-bounded controller on α from observed |V_dq − V_scalar| / |V_scalar| tracking ratio
+    "rl_advantage_normalize",              // Phase 4.5 (2026-05-30): per-batch advantage normalization (A − mean)/std with ε² variance floor — standard PPO practice, self-adaptive (no tuned params)
+    "rl_signal_variance_update",           // Adaptive controller floors (2026-05-30): Welford online variance for controller input EMAs; replaces hardcoded NOISE_FLOOR_FRAC constants in 8 controllers — sample_var = M² / (count-1); see spec 2026-05-30-adaptive-controller-floor-design
+    "rl_win_rate_ema_update",              // Adaptive risk management (2026-05-30): Layer 4 (Kelly) input — observed win_rate EMA from per-batch trade outcomes
+    "rl_avg_win_loss_ema_update",          // Adaptive risk management (2026-05-30): Layer 4 (Kelly) input — avg_win/avg_loss USD EMAs from per-batch closed-trade pnl
+    "rl_inventory_variance_update",        // Adaptive risk management (2026-05-30): Layer 3 (inventory β) input — |net_position| variance EMA across batches
+    "rl_cmdp_constraints_check",           // Adaptive risk management (2026-05-30): Layer 1 hard gates — session DD + cooldown + consecutive-loss tracking; writes override flags to ISV
+    "rl_iqn_action_tau_controller",        // Adaptive risk management (2026-05-30): Layer 2 — adapts IQN action-selection quantile τ from session drawdown signal
+    "rl_inventory_beta_controller",        // Adaptive risk management (2026-05-30): Layer 3 — adapts inventory penalty β from observed inventory variance vs reward magnitude
+    "rl_kelly_fraction_controller",        // Adaptive risk management (2026-05-30): Layer 4 — half-Kelly position-size multiplier from observed win_rate × R-multiple; warmup-gated
+    "rl_surfer_scaffold_controller",       // Reward-policy realignment v5 (2026-06-01): adaptive Phase 5 shaping weight ∈ [0,1] — fades surfer-bias scaffold as agent crosses break-even, re-engages on edge-decay PH alerts
+    "rl_eval_warmup_decay",                // v9 (2026-05-31): defensive eval-boundary calibration — overrides Kelly/τ_min/entropy_min/ε_min during warmup, linearly decays back to normal; runs every step
+    "rl_regime_flat_count",                // F1.2 (2026-05-31): block-reduce per-account lots[b] → flat_count single int; prereq for regime_observer (F1.3)
+    "rl_regime_observer",                  // F1.3 (2026-05-31): unified regime state-machine — dead-zone, Welford PnL variance, tail-event, recovery_factor/eps_live
     "rl_ensemble_action_value",      // C51+IQN ensemble: E_ensemble = α×E_C51 + (1-α)×E_IQN; α from ISV[544]
     "rl_noisy_linear_forward",       // NoisyNet: factored noisy linear forward — y = (mu_w + sigma_w ⊙ eps_w) × x + (mu_b + sigma_b ⊙ eps_b); state-dependent exploration for C51/IQN final projection
     "rl_noisy_linear_backward",      // NoisyNet: factored noisy linear backward — grad_mu_w/sigma_w/mu_b/sigma_b per-batch scratch for reduce_axis0
@@ -112,7 +137,6 @@ const KERNELS: &[&str] = &[
     "rl_hindsight_track",            // HER Phase 1: per-step mid-price ring + peak tracking for backward hindsight
     "rl_hindsight_inject",           // HER Phase 2: backward inject — synthetic replay push on done if peak >> actual
     "rl_hindsight_forward",          // HER Phase 3: forward continuation — evaluates closed trades after lookahead
-    "rl_lr_from_mapped_pinned",      // Mega-graph: LR controller reads loss from mapped-pinned dev_ptrs (eliminates host loss readback between reward + training graphs)
     "rl_increment_step",             // device-resident step counter bump (ISV[548] += 1.0); graph-safe prereq — removes scalar current_step from all downstream kernel args
     "rl_fused_controllers",          // fused kernel: 10 RL ISV controllers in one launch (gamma, tau, ppo_clip, entropy_coef, rollout_steps, per_alpha, reward_scale, ppo_ratio_clamp, gate_threshold, q_distill_lambda) — saves 9 kernel launch overheads (~40-80μs/step)
     "rl_popart_normalize",           // PopArt: Welford-EMA reward normalization (replaces apply_reward_scale)
@@ -131,6 +155,20 @@ const KERNELS: &[&str] = &[
     "rl_outcome_bwd",                // Outcome aux: single linear layer backward — dW (per-batch), db (per-batch), dh_t (per-batch); 1 block per batch, 128 threads
     "snapshot_aos_to_soa",           // AoS→SoA scatter: one thread per snapshot reads contiguous Mbp10RawInput, writes into 10 SoA device buffers; replaces host nested loops + 10 DtoD copies
     "gpu_sample_and_gather",         // GPU-resident batch sampler: random file+anchor sampling + AoS→SoA gather from pre-uploaded dataset; eliminates ALL per-step CPU data loading
+    "rl_deterministic_checksum",     // Determinism foundation Phase 1 (2026-06-02): provably deterministic sum-of-squares (single-block / single-thread / f64 accumulation) for per-step component checksums in diag; localizes non-determinism source. Spec: docs/superpowers/specs/2026-06-02-determinism-foundation.md §1.1
+    "multi_head_policy_forward",     // Phase 2A-A (2026-06-03): K-head policy logit + softmax + mixture combination; per-batch deterministic sequential mixture sum. Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md §R.6
+    "multi_head_policy_gate_forward",// Phase 2A-A (2026-06-03): gating head from raw regime features [B × 6] (parallel channel bypassing VSN/Mamba2). Spec ADDENDUM 2026-06-03 §R.3 Option B
+    "multi_head_policy_backward",    // Phase 2A-B (2026-06-03): backward through mixture + per-head softmax + gating softmax. Two kernels: `_backward_pi` and `_backward_gate`. Per-batch grad scratch; caller reduces via reduce_axis0. Spec ADDENDUM 2026-06-03 §R.6
+    "multi_head_policy_aux_prior",   // Phase 2A-B (2026-06-03): per-head auxiliary KL prior gradient — additive into grad_pi_logits_k. β read from ISV slot 764. Spec ADDENDUM 2026-06-03 §R.4
+    "multi_head_policy_aggregate_diag", // Phase 2A-D (2026-06-03): device-aggregated gate-and-head diagnostics. Reduces forward outputs (gate_probs, pi_probs_k) over B → 25 ISV slots (gate_probs_mean[K] / gate_argmax_mass[K] / gate_entropy_mean / per_head_entropy_mean[K]) for the multi-head specialization verdict signal. Tree-reduce, no atomicAdd.
+    "rl_gate_lr_multiplier_controller", // Phase 2A-D fix B1.3 (2026-06-03): adaptive gate-LR multiplier controller. Reads gate_entropy_mean (slot 781) via EMA → escalates +0.3 %/step when entropy_ema > 0.85·log(K) (under-learning), decays −5 %/step when < 0.20·log(K) (collapse risk), leaves alone in healthy band. Single-thread launch (1,1,1)/(1,1,1).
+    "rl_band_head_forward",         // Phase 4-A (2026-06-03): No-transaction-band head forward — two-stage launch: (1) `rl_band_head_linear_fwd` produces [B × 2] pre-activation band logits via tree-reduce over HIDDEN_DIM; (2) `rl_band_apply_activation` applies asymmetric ±|tanh| × N_max_eff to enforce b_l ≤ 0 ≤ b_u per Davis-Norman optimality. Spec: docs/superpowers/specs/2026-06-03-no-transaction-band-architecture.md §1.1.
+    "rl_band_mask",                 // Phase 4-A: override actions[b]→Hold when position_lots[b] ∈ [b_l, b_u]. Master-gated at slot 799 (RL_BAND_ENABLED_INDEX). Grid=(B), Block=(1) — mirrors rl_confidence_gate launch shape; runs OUTSIDE graph capture per spec §9.5.
+    "rl_state_action_mask",         // Phase 7b F5 (2026-06-05): state-conditional action availability mask. Sets pi_logits[b][a]=-INF for state-illegal actions BEFORE rl_pi_action_kernel samples. Master-gated at slot 823 (RL_F5_STATE_MASK_ENABLED_INDEX, bootstrap 0.0 = OFF). Grid=(B), Block=(1). Spec docs/superpowers/specs/2026-06-04-bellman-target-foundation-reshape.md §3.5.
+    "rl_band_turnover_loss",        // Phase 4-A: turnover regularizer (Option b) with sigmoid surrogate for differentiable boundary gradient. Emits per-batch loss + per-batch grad on (b_l, b_u). Phase 4-A wires for OBSERVABILITY only; full encoder backward chain lands in Phase 4-B.
+    "rl_band_frac_aggregate",       // Phase 4-B (2026-06-04): per-step `frac_not_masked` reducer (single-block tree-reduce over batch) → writes to RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX (slot 812). Consumed by `rl_band_turnover_controller`.
+    "rl_band_turnover_controller",  // Phase 4-B: adaptive turnover-target controller. Single-thread launch (1×1×1); first-observation bootstrap for EMA at slot 809 + Schulman-bounded asymmetric adapter for slot 811 from slot 812 input. Spec §3.1 Option (c).
+    "rl_band_head_backward",        // Phase 4-B: backward through ±|tanh|×N_max activation + linear projection → per-batch grad_w/grad_b scratch + grad_h_t (OVERWRITE). Caller reduces via reduce_axis0 + folds grad_h_t into encoder via grad_h_accumulate_scaled. Spec §3.3.
 ];
 
 // Cache bust v31 — five new reduce / derive kernels populate the input

crates/ml-alpha/cuda/actions_to_market_targets.cu

@@ -40,6 +40,30 @@
 #define RL_ANTIMARTINGALE_MIN_INDEX     510
 #define RL_ANTIMARTINGALE_MAX_INDEX     511
 
+// ── Layer 1 (CMDP hard constraints — spec 2026-05-30-adaptive-risk-management) ──
+// Session-level DD-triggered + cooldown are PER-BATCH (one buffer slot per
+// independent backtest session). The two ISV slots below carry only
+// canonical-summary aggregates (worst per-batch DD, max per-batch
+// cooldown) for diag visibility — gating reads the per-batch arrays.
+#define RL_MAX_OPEN_UNITS_INDEX             665
+#define RL_NET_INVENTORY_LIMIT_USD_INDEX    670
+
+// ── Layer 4 (Kelly fraction sizing — spec 2026-05-30-adaptive-risk-management) ──
+#define RL_KELLY_FRACTION_INDEX             676
+
+// Action indices — must match crate::rl::common::Action.
+#define ACTION_SHORT_LARGE     0
+#define ACTION_SHORT_SMALL     1
+#define ACTION_HOLD            2
+#define ACTION_FLAT_FROM_LONG  3
+#define ACTION_FLAT_FROM_SHORT 4
+#define ACTION_LONG_SMALL      5
+#define ACTION_LONG_LARGE      6
+#define ACTION_TRAIL_TIGHTEN   7
+#define ACTION_TRAIL_LOOSEN    8
+#define ACTION_HALF_FLAT_LONG  9
+#define ACTION_HALF_FLAT_SHORT 10
+
 __device__ __forceinline__ int antimartingale_size(
     int base_size, float outcome_ema_b, const float* isv
 ) {
@@ -51,6 +75,24 @@ __device__ __forceinline__ int antimartingale_size(
     return (sized > 0) ? sized : 1;
 }
 
+// Returns true if `action` would open or grow a one-sided position
+// (excludes closes, half-flats, holds, and trail mutations).
+__device__ __forceinline__ bool is_opening_action(int action) {
+    return (action == ACTION_SHORT_LARGE) || (action == ACTION_SHORT_SMALL)
+        || (action == ACTION_LONG_SMALL)  || (action == ACTION_LONG_LARGE);
+}
+
+// Returns true if executing `action` from the current `net_pos_lots`
+// would INCREASE one-sided exposure (i.e. opens/grows the dominant side).
+// Closes/reverses/holds never trigger this — only same-side adds.
+__device__ __forceinline__ bool would_increase_exposure(int action, int net_pos_lots) {
+    const bool longs  = (action == ACTION_LONG_SMALL)  || (action == ACTION_LONG_LARGE);
+    const bool shorts = (action == ACTION_SHORT_SMALL) || (action == ACTION_SHORT_LARGE);
+    if (longs  && net_pos_lots >= 0) return true;   // open or pyramid same side
+    if (shorts && net_pos_lots <= 0) return true;
+    return false;
+}
+
 extern "C" __global__ void actions_to_market_targets(
     const int*           __restrict__ actions,             // [b_size]
     const unsigned char* __restrict__ pos_state,           // [b_size * pos_bytes]
@@ -64,19 +106,86 @@ extern "C" __global__ void actions_to_market_targets(
     const int*           __restrict__ pyramid_units_count, // [b_size]
     const int*           __restrict__ close_unit_index,    // [b_size] (-1 = auto oldest)
     const float*         __restrict__ outcome_ema,         // [b_size] per-batch
+    // CMDP per-batch state (Layer 1, spec 2026-05-30-adaptive-risk-management).
+    // Each batch element is an independent session; one account hitting
+    // its DD limit or cooldown does not gate the other 1023 sessions.
+    const float*         __restrict__ session_dd_triggered_per_batch, // [b_size]
+    const float*         __restrict__ cooldown_remaining_per_batch,   // [b_size]
     int                                b_size,
     int                                pos_bytes
 ) {
     const int b = blockIdx.x * blockDim.x + threadIdx.x;
     if (b >= b_size) return;
 
-    const int action = actions[b];
+    int action = actions[b];
     const int position_lots = *(const int*)(pos_state + b * pos_bytes);
     const float outcome_ema_b = outcome_ema[b];
 
     int side = 2; // default no-op
     int size = 0;
 
+    // ────────────────────────────────────────────────────────────────────
+    // Layer 1 (CMDP hard constraints — spec 2026-05-30-adaptive-risk-management).
+    // Session-level overrides force the account FLAT regardless of agent's
+    // choice. Per-batch (one independent backtest session per b); a tripped
+    // DD or active cooldown on session `b` does NOT lock out the others.
+    //
+    // Fix E (2026-05-30): emit a *closing* market order when the account
+    // is non-flat — otherwise an existing losing position bleeds m2m for
+    // the entire 500-step cooldown with no exit (trail stops are also
+    // suppressed by this branch). Cluster alpha-rl-rjsjq step 371 showed
+    // worst session_pnl growing monotonically -$3.7k → -$9.3k from
+    // exactly this mechanism.
+    //
+    // Once the position is flat, subsequent cooldown steps emit a true
+    // no-op (side=2, size=0) and the account waits for its recovery clock.
+    // ────────────────────────────────────────────────────────────────────
+    const bool dd_triggered = session_dd_triggered_per_batch[b] >= 0.5f;
+    const bool in_cooldown  = cooldown_remaining_per_batch[b]   > 0.0f;
+    if (dd_triggered || in_cooldown) {
+        if (position_lots > 0) {
+            // long → close via sell
+            market_targets[b * 2 + 0] = 1;
+            market_targets[b * 2 + 1] = position_lots;
+        } else if (position_lots < 0) {
+            // short → close via buy
+            market_targets[b * 2 + 0] = 0;
+            market_targets[b * 2 + 1] = -position_lots;
+        } else {
+            // already flat → true no-op
+            market_targets[b * 2 + 0] = 2;
+            market_targets[b * 2 + 1] = 0;
+        }
+        return;
+    }
+
+    // Max-open-units check (per-batch dynamic count): refuse opens once
+    // pyramid is at MAX. Closes still allowed (handled by remaining logic).
+    {
+        int active_units = 0;
+        const int base_u = b * MAX_UNITS;
+        for (int u = 0; u < MAX_UNITS; ++u) {
+            if (unit_active[base_u + u]) active_units += 1;
+        }
+        const int max_open = (int)isv[RL_MAX_OPEN_UNITS_INDEX];
+        if (active_units >= max_open && is_opening_action(action)) {
+            action = ACTION_HOLD;
+        }
+    }
+
+    // Net-inventory cap (USD): block actions that grow one-sided exposure
+    // beyond the limit. Uses bid/ask mid as the USD multiplier.
+    {
+        const float inv_limit = isv[RL_NET_INVENTORY_LIMIT_USD_INDEX];
+        if (inv_limit > 0.0f) {
+            const float mid = 0.5f * (bid_px[0] + ask_px[0]);
+            const float net_pos_usd = (float)position_lots * mid;
+            if (fabsf(net_pos_usd) > inv_limit && would_increase_exposure(action, position_lots)) {
+                action = ACTION_HOLD;
+            }
+        }
+    }
+
     if (action == 0) {
         // ShortLarge — when already short, apply pyramid logic.
         if (position_lots < 0) {
@@ -240,6 +349,27 @@ extern "C" __global__ void actions_to_market_targets(
     // actions 7, 8 (TrailTighten/Loosen): no fill — handled by
     // rl_trail_mutate kernel. The side=2 no-op default is correct here.
 
+    // ────────────────────────────────────────────────────────────────────
+    // Layer 4 (Kelly-fraction sizing — spec 2026-05-30-adaptive-risk-management).
+    // Scales the opening/sizing size by the observed-edge Kelly fraction.
+    // Closes (FlatFrom* + HalfFlat*) and Hold are NOT scaled — risk
+    // management for exiting positions is handled by Layer 1 + trail stops.
+    // ────────────────────────────────────────────────────────────────────
+    if (size > 0 && is_opening_action(action)) {
+        const float kelly = isv[RL_KELLY_FRACTION_INDEX];
+        // Bootstrap = 1.0 (full size); negative or zero → no commitment.
+        const float scaled = (float)size * kelly;
+        if (scaled <= 0.0f) {
+            size = 0;
+            side = 2;
+        } else {
+            // Ceil to preserve at least 1-lot when kelly is small-but-positive.
+            int new_size = (int)ceilf(scaled);
+            if (new_size < 1) new_size = 1;
+            size = new_size;
+        }
+    }
+
     market_targets[b * 2 + 0] = side;
     market_targets[b * 2 + 1] = size;
 }

crates/ml-alpha/cuda/adamw_step.cu

@@ -44,41 +44,3 @@ extern "C" __global__ void adamw_step(
 
     theta[i] -= lr * (m_hat / (sqrtf(v_hat) + eps) + wd * theta[i]);
 }
-
-// Mega-graph variant: reads LR from an ISV device pointer at a given
-// slot index instead of taking a scalar argument. This allows the LR
-// to vary across graph replays (the ISV slot is modified in-place by
-// the rl_lr_from_mapped_pinned controller kernel which is captured
-// earlier in the same graph). All other args are identical to adamw_step.
-extern "C" __global__ void adamw_step_isv_lr(
-    float*       __restrict__ theta,
-    const float* __restrict__ grad,
-    float*       __restrict__ m,
-    float*       __restrict__ v,
-    int n_params,
-    const float* __restrict__ isv,
-    int lr_slot,
-    float beta1,
-    float beta2,
-    float eps,
-    float wd,
-    int step
-) {
-    int i = blockIdx.x * blockDim.x + threadIdx.x;
-    if (i >= n_params) return;
-
-    const float lr = isv[lr_slot];
-
-    const float g = grad[i];
-    const float m_n = beta1 * m[i] + (1.0f - beta1) * g;
-    const float v_n = beta2 * v[i] + (1.0f - beta2) * g * g;
-    m[i] = m_n;
-    v[i] = v_n;
-
-    const float bc1 = 1.0f - powf(beta1, (float) step);
-    const float bc2 = 1.0f - powf(beta2, (float) step);
-    const float m_hat = m_n / fmaxf(bc1, 1e-12f);
-    const float v_hat = v_n / fmaxf(bc2, 1e-12f);
-
-    theta[i] -= lr * (m_hat / (sqrtf(v_hat) + eps) + wd * theta[i]);
-}

crates/ml-alpha/cuda/apply_reward_scale.cu

@@ -57,7 +57,11 @@
 // by `rl_isv_write`; tunable at runtime by re-seeding. Also adaptive
 // per-step via `rl_reward_clamp_controller` reading the per-step
 // positive-scaled max published below.
-#define RL_REWARD_CLAMP_WIN_INDEX  452
+#define RL_REWARD_CLAMP_WIN_INDEX     452
+// B-7 (2026-06-01): ISV toggle to disable the post-scale clamp entirely.
+// Default 0 → clamp disabled, popart's standardization + F4 envelope
+// handle tail magnitudes. Legacy 1 → clamp applied as before.
+#define RL_REWARD_CLAMP_ENABLED_INDEX 724
 #define RL_REWARD_CLAMP_LOSS_INDEX 453
 
 // audit 2026-05-24: per-step max(positive scaled reward, 0) published
@@ -99,8 +103,9 @@ extern "C" __global__ void apply_reward_scale(
     // ISV-driven clamp bounds (was hardcoded 1.0 / 3.0). Reading per
     // kernel launch is one extra coalesced load; broadcast across the
     // block by all threads.
-    const float clamp_win  = isv[RL_REWARD_CLAMP_WIN_INDEX];
-    const float clamp_loss = isv[RL_REWARD_CLAMP_LOSS_INDEX];
+    const float clamp_win     = isv[RL_REWARD_CLAMP_WIN_INDEX];
+    const float clamp_loss    = isv[RL_REWARD_CLAMP_LOSS_INDEX];
+    const float clamp_enabled = isv[RL_REWARD_CLAMP_ENABLED_INDEX];
 
     // Pass 1 — scale, clamp, accumulate per-thread max |scaled|, max
     // max(positive scaled, 0), AND max(-scaled, 0). Three independent
@@ -131,11 +136,15 @@ extern "C" __global__ void apply_reward_scale(
         const float n = fmaxf(-scaled, 0.0f);
         if (n > local_neg) local_neg = n;
 
-        // Asymmetric clamp: [-clamp_loss, +clamp_win] from ISV.
-        // Defaults preserve loss aversion (loss > win) while bounding
-        // V regression target.
-        const float clamped = fmaxf(-clamp_loss,
-                                    fminf(scaled, clamp_win));
+        // B-7 (2026-06-01): ISV-gated clamp. Default OFF — popart's
+        // standardization + F4 envelope handle tail magnitudes per
+        // van Hasselt 2016. Clamp truncates tail losses BEFORE popart
+        // sees them, creating a reward-hacking gap (training reward
+        // signal positive while realized eval pnl strongly negative).
+        // Set RL_REWARD_CLAMP_ENABLED_INDEX = 1 to restore legacy.
+        const float clamped = (clamp_enabled > 0.5f)
+            ? fmaxf(-clamp_loss, fminf(scaled, clamp_win))
+            : scaled;
         rewards[b] = clamped;
     }
     s_abs[tid] = local_abs;

crates/ml-alpha/cuda/bellman_target_projection.cu

@@ -44,13 +44,29 @@
 #define N_ACTIONS          11
 // V_MIN/V_MAX/DELTA_Z are now ISV-driven per audit 2026-05-24 followup
 // so adaptive reward clamps also lift Q's distributional support.
-// Slots RL_C51_V_MIN_INDEX/RL_C51_V_MAX_INDEX are ratchet (monotone-
-// grow), so the C51 atom mapping never coarsens — only expands as
-// wider trades are observed.
+// Slots RL_C51_V_MIN_INDEX/RL_C51_V_MAX_INDEX track the active reward
+// range via a symmetric slow EWMA (α=0.001, half-life ~700 steps) on
+// the WIN/LOSS clamp bounds — see `rl_reward_clamp_controller.cu`
+// Step 5 (lines 72-81 for design rationale, 333-350 for the update).
+// Floored at [-1, +1] per pearl_c51_v_max_freeze_required_for_surfer
+// (V_MAX in 100-200 → trend-follower; past 1000 → degraded). The
+// earlier "ratchet (monotone-grow)" comment here was stale — superseded
+// by the wwcsz followup 2026-05-24 which replaced the ratchet to focus
+// atom resolution on the active range. B-9's saturation observability
+// (slots 726-729) surfaces if the EWMA decay over-shrinks the span.
 #define RL_C51_V_MAX_INDEX  484
 #define RL_C51_V_MIN_INDEX  485
 #define RL_GAMMA_INDEX   400
 
+// B-9 (2026-06-01): per-batch scratch outputs for the C51 Bellman-target
+// saturation diagnostic. Each `[B]` array receives one value per block;
+// the cross-batch reduce kernel `rl_bellman_target_saturation_reduce`
+// folds them into ISV slots 726-729. Per `feedback_no_atomicadd.md`:
+// scratch + tree-reduce; no atomicAdd anywhere. The sequential thread-0
+// reduction below matches the existing softmax max/sum pattern (lines
+// 157 / 171 / 234 / 248) — avoids the odd-`Q_N_ATOMS=21` tree-reduce
+// partner-skip bug.
+
 
 // ─────────────────────────────────────────────────────────────────────
 // dqn_select_action_atoms — extract per-batch atom row at the requested
@@ -120,14 +136,21 @@ extern "C" __global__ void dqn_select_action_atoms(
 //   block = (Q_N_ATOMS, 1, 1)
 // ─────────────────────────────────────────────────────────────────────
 extern "C" __global__ void bellman_fused_select_project(
-    const float* __restrict__ full_logits,    // [B × N_ACTIONS × Q_N_ATOMS]
-    const int*   __restrict__ actions,        // [B]
-    const float* __restrict__ rewards,        // [B]
-    const float* __restrict__ dones,          // [B]
-    const float* __restrict__ n_step_gammas,  // [B]
-    const float* __restrict__ isv,            // ≥ 486
+    const float* __restrict__ full_logits,         // [B × N_ACTIONS × Q_N_ATOMS]
+    const int*   __restrict__ actions,             // [B]
+    const float* __restrict__ rewards,             // [B]
+    const float* __restrict__ dones,               // [B]
+    const float* __restrict__ n_step_gammas,       // [B]
+    const float* __restrict__ isv,                 // ≥ 486
     int          B,
-    float*       __restrict__ target_dist     // [B × Q_N_ATOMS]
+    float*       __restrict__ target_dist,         // [B × Q_N_ATOMS]
+    // B-9 (2026-06-01): per-batch saturation tally scratch. Each block
+    // (one per batch element) writes one value to each. Consumed by
+    // `rl_bellman_target_saturation_reduce` after this kernel returns.
+    float*       __restrict__ sat_top_per_batch,   // [B]
+    float*       __restrict__ sat_bot_per_batch,   // [B]
+    float*       __restrict__ max_pre_per_batch,   // [B]
+    float*       __restrict__ min_pre_per_batch    // [B]
 ) {
     const int batch = blockIdx.x;
     const int atom  = threadIdx.x;
@@ -193,6 +216,31 @@ extern "C" __global__ void bellman_fused_select_project(
     const int   u          = max(0, min(Q_N_ATOMS - 1, (int)ceilf(b_frac)));
     const float frac       = b_frac - (float)l;
 
+    // B-9 (2026-06-01): per-(b, atom_z) saturation tally over pre-clamp
+    // t_z. Sequential thread-0 reduction over Q_N_ATOMS=21 (matches the
+    // softmax pattern at lines 157 / 171). Odd count rules out a
+    // symmetric tree-reduce.
+    __shared__ float s_t_z[Q_N_ATOMS];
+    s_t_z[atom] = t_z;
+    __syncthreads();
+    if (atom == 0) {
+        float sum_top = 0.0f, sum_bot = 0.0f;
+        float max_tz  = s_t_z[0], min_tz = s_t_z[0];
+        #pragma unroll
+        for (int z = 0; z < Q_N_ATOMS; ++z) {
+            const float tz_z = s_t_z[z];
+            sum_top += (tz_z > V_MAX_eff) ? 1.0f : 0.0f;
+            sum_bot += (tz_z < V_MIN_eff) ? 1.0f : 0.0f;
+            max_tz   = fmaxf(max_tz, tz_z);
+            min_tz   = fminf(min_tz, tz_z);
+        }
+        sat_top_per_batch[batch] = sum_top;
+        sat_bot_per_batch[batch] = sum_bot;
+        max_pre_per_batch[batch] = max_tz;
+        min_pre_per_batch[batch] = min_tz;
+    }
+    __syncthreads();
+
     // Distribute mass — serialised walk per `feedback_no_atomicadd.md`
     for (int src = 0; src < Q_N_ATOMS; ++src) {
         __syncthreads();
@@ -211,13 +259,21 @@ extern "C" __global__ void bellman_fused_select_project(
 
 
 extern "C" __global__ void bellman_target_projection(
-    const float* __restrict__ target_logits,  // [B × Q_N_ATOMS]
-    const float* __restrict__ rewards,        // [B] (n-step discounted R_n)
-    const float* __restrict__ dones,          // [B]
-    const float* __restrict__ n_step_gammas,  // [B] (γⁿ per transition, 0 if done)
-    const float* __restrict__ isv,            // ≥ 401
+    const float* __restrict__ target_logits,       // [B × Q_N_ATOMS]
+    const float* __restrict__ rewards,             // [B] (n-step discounted R_n)
+    const float* __restrict__ dones,               // [B]
+    const float* __restrict__ n_step_gammas,       // [B] (γⁿ per transition, 0 if done)
+    const float* __restrict__ isv,                 // ≥ 401
     int          B,
-    float*       __restrict__ target_dist     // [B × Q_N_ATOMS]
+    float*       __restrict__ target_dist,         // [B × Q_N_ATOMS]
+    // B-9 (2026-06-01): per-batch saturation tally scratch. Mirrors the
+    // fused variant above (`bellman_fused_select_project`); per
+    // `feedback_no_partial_refactor.md` both entry points must be
+    // instrumented atomically.
+    float*       __restrict__ sat_top_per_batch,   // [B]
+    float*       __restrict__ sat_bot_per_batch,   // [B]
+    float*       __restrict__ max_pre_per_batch,   // [B]
+    float*       __restrict__ min_pre_per_batch    // [B]
 ) {
     const int batch = blockIdx.x;
     const int atom  = threadIdx.x;
@@ -278,6 +334,30 @@ extern "C" __global__ void bellman_target_projection(
     const int   u          = max(0, min(Q_N_ATOMS - 1, (int)ceilf(b_frac)));
     const float frac       = b_frac - (float)l;
 
+    // B-9 (2026-06-01): per-(b, atom_z) saturation tally over pre-clamp
+    // t_z. Identical reduction as `bellman_fused_select_project` above
+    // — per `feedback_no_partial_refactor.md`.
+    __shared__ float s_t_z[Q_N_ATOMS];
+    s_t_z[atom] = t_z;
+    __syncthreads();
+    if (atom == 0) {
+        float sum_top = 0.0f, sum_bot = 0.0f;
+        float max_tz  = s_t_z[0], min_tz = s_t_z[0];
+        #pragma unroll
+        for (int z = 0; z < Q_N_ATOMS; ++z) {
+            const float tz_z = s_t_z[z];
+            sum_top += (tz_z > V_MAX_eff) ? 1.0f : 0.0f;
+            sum_bot += (tz_z < V_MIN_eff) ? 1.0f : 0.0f;
+            max_tz   = fmaxf(max_tz, tz_z);
+            min_tz   = fminf(min_tz, tz_z);
+        }
+        sat_top_per_batch[batch] = sum_top;
+        sat_bot_per_batch[batch] = sum_bot;
+        max_pre_per_batch[batch] = max_tz;
+        min_pre_per_batch[batch] = min_tz;
+    }
+    __syncthreads();
+
     // ── Distribute mass into the two nearest support atoms ───────────
     //
     // Each thread holds (l, u, frac, p) for its OWN source atom. We

crates/ml-alpha/cuda/bucket_transition_kernels.cu

@@ -392,10 +392,14 @@ extern "C" __global__ void heads_lr_multiplier_scale_kernel(
 // `channels_in_bucket[bucket][i]` populated at transition by
 // `channels_in_bucket_kernel`.
 //
-// Launch: grid = (N_HORIZONS, 1, 1), block = (32, 1, 1). Each block
+// Launch: grid = (N_HORIZONS, 1, 1), block = (128, 1, 1). Each block
 // reduces one bucket. Per `feedback_no_atomicadd`, reduction is
 // block-tree on shared memory (no atomicAdd).
 //
+// Block size = 128 covers MAX_BUCKET_DIM=96 (smallest pow2 ≥ 96).
+// Previous block_dim=32 silently dropped channels 32..bdim when bdim>32
+// — caught by `tests/bucket_transition_kernels.rs` (block_dim=43 case).
+//
 // Input `h_state` is `[B × HIDDEN_DIM]` (ORIGINAL channel layout). Each
 // block reads its bucket's `bucket_dim_k[bucket]` channels (via
 // `channels_in_bucket[bucket][0..bdim]`) per sample (across all B
@@ -412,20 +416,20 @@ extern "C" __global__ void h_mag_per_bucket_kernel(
     if (bucket >= N_HORIZONS) return;
     int bdim = (int)bucket_dim_k[bucket];
 
-    // sdata sized for a single-warp reduction (32 lanes).
-    __shared__ float sdata[32];
+    // sdata sized for the 128-lane block reduction.
+    __shared__ float sdata[128];
     int tid = threadIdx.x;
 
     // Each thread sums |h| over its bucket-local index (tid), looking up
     // the ORIGINAL channel via channels_in_bucket. Threads with tid >= bdim
-    // idle — uniform predicate, no warp divergence inside [0, 32).
+    // contribute 0. With bdim ∈ [1, MAX_BUCKET_DIM=96] and block_dim=128,
+    // tail lanes [bdim, 128) are always inactive — uniform predicate.
     float local_sum = 0.0f;
     if (tid < bdim) {
         unsigned int c = channels_in_bucket[bucket * MAX_BUCKET_DIM + tid];
-        // Defensive: sentinel slot OR out-of-range channel index should
-        // not contribute. Predicate is uniform across the warp because all
-        // active threads (tid < bdim) hold valid entries by construction
-        // of channels_in_bucket_kernel.
+        // Defensive: out-of-range channel index should not contribute.
+        // Predicate is uniform across active lanes (tid < bdim) — all hold
+        // valid entries by construction of channels_in_bucket_kernel.
         if (c < (unsigned int)HIDDEN_DIM) {
             for (int b = 0; b < B; ++b) {
                 float v = h_state[b * HIDDEN_DIM + c];
@@ -433,11 +437,12 @@ extern "C" __global__ void h_mag_per_bucket_kernel(
             }
         }
     }
-    sdata[tid] = (tid < 32) ? local_sum : 0.0f;
+    sdata[tid] = local_sum;
     __syncthreads();
 
-    // Block-tree reduction over 32 lanes (single warp). No atomicAdd.
-    for (int s = 16; s > 0; s >>= 1) {
+    // Block-tree reduction over 128 lanes (multi-warp). No atomicAdd.
+    // Stages: 64→32→16→8→4→2→1. Each stage halves the active lane count.
+    for (int s = 64; s > 0; s >>= 1) {
         if (tid < s) sdata[tid] += sdata[tid + s];
         __syncthreads();
     }

crates/ml-alpha/cuda/compute_advantage_return.cu

@@ -19,13 +19,26 @@ extern "C" __global__ void compute_advantage_return(
     const int b = blockIdx.x * blockDim.x + threadIdx.x;
     if (b >= b_size) return;
 
-    const float gamma = isv[RL_GAMMA_INDEX];
-    const float r     = rewards[b];
-    const float done  = dones[b];
-    const float vt    = v_t[b];
-    const float vtp1  = v_tp1[b];
+    const float gamma  = isv[RL_GAMMA_INDEX];
+    const float r      = rewards[b];
+    const float is_done = (dones[b] > 0.5f);
+    const float vt     = v_t[b];
+    const float vtp1   = v_tp1[b];
 
-    const float ret = r + gamma * (1.0f - done) * vtp1;
-    returns[b]    = ret;
-    advantages[b] = done * (ret - vt);
+    // 2026-05-29: branch-gate (not multiplication-gate) the V_tp1 term
+    // and the (ret - vt) advantage. Multiplication-gating fails on IEEE
+    // `0 * Inf = NaN`: if any batch's encoder produces a non-finite V
+    // prediction early in training (random init outliers), the prior
+    // `done * (ret - vt)` multiplication propagated NaN to ALL non-done
+    // batches' advantages, which then broke compute_advantage_rms (sum
+    // of A² → NaN) and PPO (A/RMS → NaN, ratio×A → NaN, l_pi → NaN).
+    // Branch-gating ensures non-finite vtp1/vt are NEVER mixed into a
+    // non-done batch's advantage. Validated by the smoke bisect at
+    // 10d4614fb (deterministic NaN at step 4 with l_v=6.329 stable —
+    // proving V REGRESSION is fine while V FORWARD has at least one
+    // non-finite output that the 0*Inf trick was promoting to NaN
+    // everywhere). Per `pearl_atomicadd_masks_v_instability`.
+    const float ret = is_done ? r : (r + gamma * vtp1);
+    returns[b]      = ret;
+    advantages[b]   = is_done ? (ret - vt) : 0.0f;
 }

crates/ml-alpha/cuda/dqn_distributional_q.cu

@@ -33,24 +33,22 @@
 //             One thread per (action, atom) pair (231 live threads,
 //             25 padding). Softmax uses shared-memory reduce (21
 //             atoms for the taken action). Loss uses a 256-wide
-//             block-level tree-reduce in shared memory. Cross-batch
-//             loss accumulation uses atomicAdd ONLY into the scalar
-//             loss_out — see ATOMIC NOTE below.
+//             block-level tree-reduce in shared memory. Per-batch CE
+//             is written to `loss_per_batch[batch]` (single writer per
+//             slot); the trainer's scalar diagnostic is produced by a
+//             separate `mean_reduce_b_f32` kernel call. No atomicAdd.
 //
-// ATOMIC NOTE (deliberate, deferred fix): the cross-batch loss
-// accumulator uses `atomicAdd(loss_out, ce_b)`. This nominally violates
-// `feedback_no_atomicadd.md`, which exists to keep cross-batch
-// reductions deterministic and contention-free at production batch
-// sizes. We accept it HERE in Phase C because:
-//   (a) the toy-bandit smoke runs with B ≤ 32, so atomic contention is
-//       negligible (32 writers on a single L2 line);
-//   (b) the loss_out scalar is purely diagnostic — gradient flow goes
-//       through `grad_logits`, which is NEVER atomicAdded;
-//   (c) Phase E replaces this with a two-stage warp-shuffle → shared
-//       reduce → single-writer store, matching the `aux_loss.cu` pattern,
-//       when the trainer batches reach production sizes (B = 256+).
-// Documented loudly here so the audit trail is visible at the kernel
-// header without diving into the loss kernel body.
+// REDUCTION DISCIPLINE (per `feedback_no_atomicadd.md`):
+//   F4.1 (2026-05-31) removed the prior `atomicAdd(loss_out, ce/B)`
+//   call. The kernel still tree-reduces atoms-per-batch in shared
+//   memory; cross-batch reduction is now external (single block,
+//   `mean_reduce_b_f32` in ppo_loss_reduce_b cubin) so every device
+//   write in the loss path has exactly one writer. The atomicAdd was
+//   structurally fine here because the trainer DID memset `loss_out`
+//   between launches in `dqn_replay_step`, but the same pattern in
+//   `ppo_clipped_surrogate_fwd` lacked that memset and silently
+//   accumulated across steps — see commit log for the
+//   step-count-fingerprint diagnosis. Both fixed identically.
 
 #define HIDDEN_DIM       128
 #define N_ACTIONS        11
@@ -159,8 +157,8 @@ extern "C" __global__ void dqn_distributional_q_bwd(
     const float* __restrict__ target_dist,    // [B * Q_N_ATOMS]
     const int*   __restrict__ actions_taken,  // [B]
     int          B,
-    float*       __restrict__ loss_out,       // [1]
-    float*       __restrict__ loss_per_batch, // [B] — R7d: per-sample CE for PER priority update
+    float*       __restrict__ loss_per_batch, // [B] — per-sample CE (PER priority update + diagnostic
+                                              //       mean reduction via `mean_reduce_b_f32`).
     float*       __restrict__ grad_logits     // [B * N_ACTIONS * Q_N_ATOMS]
 ) {
     const int batch = blockIdx.x;
@@ -275,14 +273,17 @@ extern "C" __global__ void dqn_distributional_q_bwd(
         __syncthreads();
     }
 
-    // Thread 0 writes the per-batch CE and accumulates into loss_out.
-    // The cross-batch atomicAdd on loss_out is the Phase C deferred
-    // fix (see ATOMIC NOTE in the file header). grad_logits is never
-    // atomicAdded.
+    // F4.1 (2026-05-31): single writer per batch slot — no atomicAdd.
+    // The trainer-side scalar `loss_out` is produced by a separate
+    // `mean_reduce_b_f32` block tree-reduce kernel (ppo_loss_reduce_b
+    // cubin), called immediately after this kernel. Replaces the Phase
+    // C "loud-flagged" atomicAdd that — like the analogous bug in
+    // `ppo_clipped_surrogate_fwd` — accumulated across steps whenever
+    // the caller forgot to memset between launches, producing
+    // step-count-fingerprinted loss inflation. Per
+    // `feedback_no_atomicadd`.
     if (tid == 0) {
-        const float ce = s_ce[0];
-        loss_per_batch[batch] = ce;
-        atomicAdd(loss_out, ce / (float)B);
+        loss_per_batch[batch] = s_ce[0];
     }
 }
 

crates/ml-alpha/cuda/gae_backward_sweep.cu

@@ -0,0 +1,58 @@
+// gae_backward_sweep.cu — Generalized Advantage Estimation backward sweep.
+//
+// Spec: docs/superpowers/specs/2026-06-02-trainer-rollout-buffer-gae.md §1.3
+// Plan: docs/superpowers/plans/2026-06-02-trainer-rollout-buffer-gae-implementation.md
+//
+// Per batch b, sequentially compute (backward over T):
+//   A_T   = 0
+//   for t in (T-1)..=0:
+//     non_terminal = 1.0f - (float)dones[b][t]
+//     v_tp1 = (t == T-1) ? v_T_bootstrap[b] : v_t[b][t+1]
+//     δ_t = r[b][t] + γ * v_tp1 * non_terminal - v_t[b][t]
+//     A_t = δ_t + γ * λ * A_next * non_terminal
+//     A_next = A_t * non_terminal   // reset GAE accumulator on terminal
+//   returns[b][t] = A_t + v_t[b][t]
+//
+// Single-thread-per-batch kernel. Sequential backward sweep guarantees
+// determinism (no parallel reductions, no inter-thread/block races).
+// Memory access is strided over T for each thread — coalescing is
+// suboptimal but functional; the rollout T (≤1024) and B (≤1024) keep
+// this off the hot path. If profiling later shows it dominating, the
+// follow-up is a warp-cooperative tiled implementation that preserves
+// determinism via a single-warp reduction.
+//
+// Per `feedback_no_atomicadd`: no atomic ops anywhere.
+// Per `feedback_cpu_is_read_only`: pure device-side, no host roundtrips.
+// Per `feedback_no_nvrtc`: pre-compiled cubin (build.rs registers it).
+
+#include <stdint.h>
+
+extern "C" __global__ void gae_backward_sweep(
+    const float* __restrict__ rewards,        // [B × T]
+    const uint8_t* __restrict__ dones,        // [B × T]
+    const float* __restrict__ v_t,            // [B × T]
+    const float* __restrict__ v_T_bootstrap,  // [B]   — V(s_T) for trajectory end
+    float* __restrict__ advantages,           // [B × T] (output)
+    float* __restrict__ returns,              // [B × T] (output)
+    const int B,
+    const int T,
+    const float gamma,
+    const float lambda
+) {
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
+    if (b >= B) return;
+
+    float a_next = 0.0f;
+    for (int t = T - 1; t >= 0; t--) {
+        const int idx = b * T + t;
+        const float r_t = rewards[idx];
+        const float v_curr = v_t[idx];
+        const float non_terminal = 1.0f - (float)dones[idx];
+        const float v_tp1 = (t == T - 1) ? v_T_bootstrap[b] : v_t[idx + 1];
+        const float delta = r_t + gamma * v_tp1 * non_terminal - v_curr;
+        const float a_t = delta + gamma * lambda * a_next * non_terminal;
+        advantages[idx] = a_t;
+        returns[idx] = a_t + v_curr;
+        a_next = a_t * non_terminal;  // reset on done
+    }
+}

crates/ml-alpha/cuda/gpu_sample_and_gather.cu

@@ -24,8 +24,6 @@
 
 #define BOOK_LEVELS 10
 #define REGIME_DIM  6
-#define N_HORIZONS  3
-#define N_LABEL_SOURCES 5
 
 // Must match #[repr(C)] Mbp10RawInput in snap_features.rs (216 bytes).
 struct __align__(8) Mbp10Raw {
@@ -82,26 +80,11 @@ extern "C" __global__ void gpu_sample_and_gather(
     long long*      __restrict__ ts_ns_soa,        // [B*K]
     long long*      __restrict__ prev_ts_ns_soa,   // [B*K]
     // Global-memory outputs for the sampled (file_offset, anchor, file_idx)
-    // per batch element. Read by gpu_gather_next and gpu_gather_frd_labels
-    // to reuse the same sampling decision.
+    // per batch element. Read by gpu_gather_next, gpu_gather_frd_labels,
+    // and gpu_gather_bce_labels to reuse the same sampling decision.
     int*            __restrict__ out_file_offset,   // [B]
     int*            __restrict__ out_anchor,         // [B]
     int*            __restrict__ out_file_idx,       // [B]
-    // Fused label gather — 5 label sources (BCE, prof_long, prof_short,
-    // size_long, size_short), each [N_HORIZONS × total_snaps]. Reads in
-    // the same pass as snapshot gather to avoid 5 separate random-access
-    // kernel launches that consumed 95.6% of GPU time.
-    int             total_snaps,
-    const float*    __restrict__ labels_src_0,      // [N_HORIZONS × total_snaps]
-    const float*    __restrict__ labels_src_1,
-    const float*    __restrict__ labels_src_2,
-    const float*    __restrict__ labels_src_3,
-    const float*    __restrict__ labels_src_4,
-    float*          __restrict__ labels_out_0,      // [K, B, N_HORIZONS]
-    float*          __restrict__ labels_out_1,
-    float*          __restrict__ labels_out_2,
-    float*          __restrict__ labels_out_3,
-    float*          __restrict__ labels_out_4,
     int B
 ) {
     int b = blockIdx.x;
@@ -165,26 +148,9 @@ extern "C" __global__ void gpu_sample_and_gather(
     tc_soa[n]        = (int)snap.trade_count;
     ts_ns_soa[n]     = (long long)snap.ts_ns;
     prev_ts_ns_soa[n] = (long long)snap.prev_ts_ns;
-
-    // Fused label gather — same global_idx, zero extra random access.
-    // Output layout: [K, B, N_HORIZONS] row-major.
-    int lbl_base = (k * B + b) * N_HORIZONS;
-    const float* srcs[N_LABEL_SOURCES] = {
-        labels_src_0, labels_src_1, labels_src_2, labels_src_3, labels_src_4
-    };
-    float* outs[N_LABEL_SOURCES] = {
-        labels_out_0, labels_out_1, labels_out_2, labels_out_3, labels_out_4
-    };
-    #pragma unroll
-    for (int s = 0; s < N_LABEL_SOURCES; s++) {
-        #pragma unroll
-        for (int h = 0; h < N_HORIZONS; h++) {
-            outs[s][lbl_base + h] = srcs[s][h * total_snaps + global_idx];
-        }
-    }
 }
 
-// ── Label gather kernel (STANDALONE — kept for backward compat) ─────
+// ── Label gather kernel ──────────────────────────────────────────────
 //
 // Runs AFTER gpu_sample_and_gather. Gathers per-horizon FRD labels at
 // the anchor position (rightmost K position = newest snapshot in the

crates/ml-alpha/cuda/grad_h_accumulate.cu

@@ -36,20 +36,3 @@ extern "C" __global__ void grad_h_accumulate_scaled(
     if (i >= n) return;
     grad_h_encoder[i] += lambda * grad_h_head[i];
 }
-
-// Mega-graph variant: reads lambda from ISV device pointer at given slot.
-// This allows the lambda to vary across graph replays (ISV is modified
-// in-place by controller kernels captured earlier in the same graph).
-extern "C" __global__ void grad_h_accumulate_scaled_isv(
-    const float* __restrict__ grad_h_head,
-    const float* __restrict__ isv,
-    int          lambda_slot,
-    float        batch_inv,                    // 1.0 / b_size
-    int          n,
-    float*       __restrict__ grad_h_encoder
-) {
-    const int i = blockIdx.x * blockDim.x + threadIdx.x;
-    if (i >= n) return;
-    const float lambda = isv[lambda_slot] * batch_inv;
-    grad_h_encoder[i] += lambda * grad_h_head[i];
-}

crates/ml-alpha/cuda/multi_head_policy_aggregate_diag.cu

@@ -0,0 +1,200 @@
+// multi_head_policy_aggregate_diag.cu — Phase 2A-D (2026-06-03)
+//
+// Device-aggregated gate-and-head diagnostics for the MultiHeadPolicy
+// path. Reads forward outputs (`gate_probs [B × K]`, `pi_probs_k
+// [B × K × N_ACTIONS]`) and writes 25 scalars into the ISV bus:
+//
+//   765..773  gate_probs_mean[K]       — mean over B of gate_probs[b,k]
+//   773..781  gate_argmax_mass[K]      — fraction of B where head k is argmax
+//   781       gate_entropy_mean        — mean over B of −Σ_k p·log p
+//   782..790  per_head_entropy_mean[K] — mean over B of −Σ_a π_k·log π_k
+//
+// Tail entries past runtime K (in the 8-stride arrays) are written 0.0
+// so the diag JSON schema is constant for K ∈ [1, 8] (matches the
+// MAX_K_HEADS=8 mirror in `rl/multi_head_policy.rs` and the kernel
+// `#define MAX_K_HEADS 8` in `multi_head_policy_forward.cu` /
+// `multi_head_policy_gate_forward.cu`).
+//
+// Constraints honoured:
+//   * `feedback_no_atomicadd` — no atomic ops. Each ISV destination cell
+//     has a single writer (thread 0 of the responsible block).
+//   * `feedback_cpu_is_read_only` — pure device kernel.
+//   * `feedback_nvidia_grade_perf_for_kernels` — no host branches in
+//     capture path; deterministic launch shape.
+//   * `pearl_fleet_fraction_not_aggregate` — these are explicit
+//     per-batch-fraction stats (mean over B / argmax-mass over B), not
+//     aggregate scalars hiding per-batch state.
+//
+// Determinism: every reduction uses a fixed-order sequential sum within
+// a single thread. Inputs (`gate_probs`, `pi_probs_k`) are forward
+// outputs already on the launching stream; aggregator runs on the same
+// stream so the producer→consumer ordering is single-stream.
+//
+// Launch config:
+//   grid  = (MAX_K_HEADS + 1, 1, 1)   = 9 blocks
+//   block = (BLOCK_THREADS, 1, 1)     = 128 threads
+//   smem  = 0 (small static shared arrays declared inside)
+//
+//   Block role assignment:
+//     blockIdx.x = 0..MAX_K_HEADS-1  → per-head stats for head k = blockIdx.x.
+//                                      Writes gate_probs_mean[k] +
+//                                      per_head_entropy_mean[k]. Tail
+//                                      heads (k >= runtime K) write 0.0.
+//     blockIdx.x = MAX_K_HEADS       → global stats. Computes
+//                                      gate_entropy_mean +
+//                                      gate_argmax_mass[k] for all K
+//                                      heads. Tail entries write 0.0.
+
+#include <stdint.h>
+
+#define MAX_K_HEADS    8
+#define N_ACTIONS      11
+#define BLOCK_THREADS  128
+
+extern "C" __global__ void multi_head_policy_aggregate_diag(
+    const float* __restrict__ gate_probs,           // [B × K]
+    const float* __restrict__ pi_probs_k,           // [B × K × N_ACTIONS]
+    float*       __restrict__ isv,                  // ISV bus
+    int                       b_size,
+    int                       k_runtime,            // ∈ [1, MAX_K_HEADS]
+    int                       gate_probs_mean_base, // 765
+    int                       gate_argmax_mass_base,// 773
+    int                       gate_entropy_mean_slot,// 781
+    int                       per_head_entropy_mean_base // 782
+) {
+    const int k_block = blockIdx.x;          // ∈ [0, MAX_K_HEADS]
+    const int tid     = threadIdx.x;          // ∈ [0, BLOCK_THREADS)
+    const float inv_b = (b_size > 0) ? (1.0f / (float)b_size) : 0.0f;
+
+    // ── Per-head blocks (k_block = 0 .. MAX_K_HEADS-1) ────────────────
+    if (k_block < MAX_K_HEADS) {
+        // Tail heads past runtime K — sole writer (thread 0) clears its
+        // two ISV destinations to 0.0 and exits.
+        if (k_block >= k_runtime) {
+            if (tid == 0) {
+                isv[gate_probs_mean_base       + k_block] = 0.0f;
+                isv[per_head_entropy_mean_base + k_block] = 0.0f;
+            }
+            return;
+        }
+
+        // ── Stat 1: gate_probs_mean[k_block] ─────────────────────────
+        // Each thread sums a strided subset of batches; tree-reduce in
+        // shared memory.
+        __shared__ float s_gpm[BLOCK_THREADS];
+        __shared__ float s_phe[BLOCK_THREADS];
+        float my_gpm = 0.0f;
+        float my_phe = 0.0f;
+
+        for (int b = tid; b < b_size; b += BLOCK_THREADS) {
+            // gate_probs is [B × K] row-major over (b, k).
+            const float p = gate_probs[b * k_runtime + k_block];
+            my_gpm += p;
+
+            // ── Stat 2: per-head entropy ─────────────────────────────
+            // pi_probs_k is [B × K × N_ACTIONS] row-major over
+            // (b, k, a). Per-head per-batch entropy:
+            //     H_k(b) = -Σ_a π_k[b,a] · log(π_k[b,a])
+            // Guard against log(0); the forward kernel writes a softmax
+            // output so π_k[b,a] > 0 (modulo fp32 underflow), but be
+            // defensive — entries < 1e-12 are clamped to a 0 contribution
+            // (matches the standard entropy convention 0·log(0) = 0).
+            const int row = (b * k_runtime + k_block) * N_ACTIONS;
+            float h = 0.0f;
+            for (int a = 0; a < N_ACTIONS; ++a) {
+                const float pa = pi_probs_k[row + a];
+                if (pa > 1e-12f) {
+                    h -= pa * logf(pa);
+                }
+            }
+            my_phe += h;
+        }
+        s_gpm[tid] = my_gpm;
+        s_phe[tid] = my_phe;
+        __syncthreads();
+
+        // Tree-reduce in shared memory. Fixed-order sequential pairwise
+        // sum — deterministic across launches (no warp shuffles, no
+        // atomic adds).
+        for (int stride = BLOCK_THREADS / 2; stride > 0; stride >>= 1) {
+            if (tid < stride) {
+                s_gpm[tid] += s_gpm[tid + stride];
+                s_phe[tid] += s_phe[tid + stride];
+            }
+            __syncthreads();
+        }
+
+        if (tid == 0) {
+            isv[gate_probs_mean_base       + k_block] = s_gpm[0] * inv_b;
+            isv[per_head_entropy_mean_base + k_block] = s_phe[0] * inv_b;
+        }
+        return;
+    }
+
+    // ── Global block (k_block == MAX_K_HEADS) ─────────────────────────
+    // Computes gate_entropy_mean (scalar) and gate_argmax_mass[K] (array).
+    //
+    // The argmax tally must avoid atomicAdd. Each thread maintains a
+    // private per-head counter in registers (small array indexed by
+    // 0..MAX_K_HEADS-1) while iterating its stride of batches. After
+    // the per-thread loop, tree-reduce each counter across threads via
+    // shared memory.
+
+    __shared__ float s_ge[BLOCK_THREADS];                  // gate entropy partial
+    __shared__ float s_am[MAX_K_HEADS][BLOCK_THREADS];      // argmax counts per (k, tid)
+
+    int   my_am[MAX_K_HEADS];
+    float my_ge = 0.0f;
+    #pragma unroll
+    for (int k = 0; k < MAX_K_HEADS; ++k) my_am[k] = 0;
+
+    for (int b = tid; b < b_size; b += BLOCK_THREADS) {
+        // Walk this batch row once: argmax + entropy in one pass.
+        int   argmax_k = 0;
+        float max_p    = gate_probs[b * k_runtime + 0];
+        float h        = 0.0f;
+        if (max_p > 1e-12f) h -= max_p * logf(max_p);
+        for (int k = 1; k < k_runtime; ++k) {
+            const float p = gate_probs[b * k_runtime + k];
+            // Ties broken by lowest index — `>` not `>=`. Deterministic.
+            if (p > max_p) {
+                max_p    = p;
+                argmax_k = k;
+            }
+            if (p > 1e-12f) h -= p * logf(p);
+        }
+        my_am[argmax_k] += 1;
+        my_ge           += h;
+    }
+
+    // Scatter per-thread counters into shared memory for tree reduction.
+    s_ge[tid] = my_ge;
+    #pragma unroll
+    for (int k = 0; k < MAX_K_HEADS; ++k) {
+        s_am[k][tid] = (float)my_am[k];
+    }
+    __syncthreads();
+
+    for (int stride = BLOCK_THREADS / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_ge[tid] += s_ge[tid + stride];
+            #pragma unroll
+            for (int k = 0; k < MAX_K_HEADS; ++k) {
+                s_am[k][tid] += s_am[k][tid + stride];
+            }
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        // gate_entropy_mean — scalar.
+        isv[gate_entropy_mean_slot] = s_ge[0] * inv_b;
+
+        // gate_argmax_mass[k] — fraction over B. Tail entries (k >= K)
+        // are 0 by construction (my_am[k>=K] is never incremented).
+        #pragma unroll
+        for (int k = 0; k < MAX_K_HEADS; ++k) {
+            isv[gate_argmax_mass_base + k] = s_am[k][0] * inv_b;
+        }
+    }
+}

crates/ml-alpha/cuda/multi_head_policy_aux_prior.cu

@@ -0,0 +1,91 @@
+// multi_head_policy_aux_prior.cu — Per-head auxiliary KL prior gradient.
+//
+// Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//       ADDENDUM 2026-06-03 §R.4 (per-head aux KL priors)
+// Plan: docs/superpowers/plans/2026-06-03-multi-head-policy-implementation.md (Phase 2A-B)
+//
+// For each head k, we add an auxiliary KL regularizer that anchors the
+// head distribution to a fixed prior:
+//
+//   L_aux_k = β · KL(π_k || prior_k)
+//           = β · Σ_a π_k(a) · log( π_k(a) / prior_k(a) )
+//
+// The grad of L_aux on the head's pre-softmax logits is the standard
+// softmax-Jacobian form (parameterization-invariant):
+//
+//   ∂L_aux_k / ∂pi_logits_k[a] = β · π_k(a) · ( log(π_k(a)/prior_k(a)) − KL_k )
+//
+// This kernel ADDS that contribution to `grad_pi_logits_k` (which the
+// backward pi kernel populated with the Q-distill chain rule).
+//
+// β is read from ISV slot `RL_POLICY_AUX_PRIOR_BETA_INDEX = 764`.
+//
+// ── Block layout ────────────────────────────────────────────────────────
+//   grid  = (B, K, 1)
+//   block = (N_ACTIONS = 11, 1, 1)
+//
+// One block per (batch, head). N_ACTIONS threads cooperate via shared
+// memory to compute KL_k[b] then write the additive grad per action.
+//
+// Per feedback_no_atomicadd: sole-writer per (b, k, a) cell within this
+// kernel; `grad_pi_logits_k` is read-modify-write but additive into a
+// slot that was just exclusively written by the preceding pi backward
+// kernel on the same stream — sequential stream ordering keeps the RMW
+// safe (no races).
+//
+// Per feedback_no_nvrtc: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+#define N_ACTIONS                         11
+#define RL_POLICY_AUX_PRIOR_BETA_INDEX    764
+#define KL_PROB_EPS                       1e-12f  // log domain stability
+
+extern "C" __global__ void multi_head_policy_aux_prior(
+    const float* __restrict__ pi_probs_k,     // [B × K × N_ACTIONS]
+    const float* __restrict__ priors,         // [K × N_ACTIONS]
+    const float* __restrict__ isv,            // ISV bus — slot 764 holds β
+    const int    B,
+    const int    K,
+    float*       __restrict__ grad_pi_logits_k  // [B × K × N_ACTIONS] RW (+=)
+) {
+    const int b = blockIdx.x;
+    const int k = blockIdx.y;
+    if (b >= B || k >= K) return;
+
+    const int a = threadIdx.x;
+    if (a >= N_ACTIONS) return;
+
+    const float beta = isv[RL_POLICY_AUX_PRIOR_BETA_INDEX];
+    // Zero-β short circuit — leaves grad_pi_logits_k untouched.
+    if (beta == 0.0f) return;
+
+    // ── Stage probs + per-action log(π/prior) ─────────────────────────
+    __shared__ float s_pi[N_ACTIONS];
+    __shared__ float s_log_ratio[N_ACTIONS];
+    __shared__ float s_kl;
+
+    const int pk_idx = (b * K + k) * N_ACTIONS + a;
+    const float pi_a = pi_probs_k[pk_idx];
+    const float prior_a = priors[k * N_ACTIONS + a];
+
+    s_pi[a] = pi_a;
+    // log(π_a / prior_a) with both args clamped against fp32 underflow.
+    s_log_ratio[a] = logf(fmaxf(pi_a, KL_PROB_EPS) / fmaxf(prior_a, KL_PROB_EPS));
+    __syncthreads();
+
+    // ── KL_k[b] = Σ_a π_a · log(π_a / prior_a) ────────────────────────
+    // Single-thread reduction over N_ACTIONS=11 for deterministic order.
+    if (a == 0) {
+        float kl = 0.0f;
+        for (int aa = 0; aa < N_ACTIONS; ++aa) {
+            kl += s_pi[aa] * s_log_ratio[aa];
+        }
+        s_kl = kl;
+    }
+    __syncthreads();
+
+    // ── grad += β · π_a · (log_ratio − KL) ────────────────────────────
+    const float g_aux = beta * s_pi[a] * (s_log_ratio[a] - s_kl);
+    grad_pi_logits_k[pk_idx] += g_aux;
+}

crates/ml-alpha/cuda/multi_head_policy_backward.cu

@@ -0,0 +1,300 @@
+// multi_head_policy_backward.cu — Backward pass for the K-head policy mixture.
+//
+// Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//       ADDENDUM 2026-06-03 §R.4 (per-head aux KL priors), §R.6 (gradient flow)
+// Plan: docs/superpowers/plans/2026-06-03-multi-head-policy-implementation.md (Phase 2A-B)
+//
+// ── Forward recap (multi_head_policy_forward.cu) ────────────────────────
+//   pi_logits_k[b,k,a] = W_heads[k,a,:] · h_t[b,:] + b_heads[k,a]
+//   pi_probs_k[b,k,a]  = softmax_a(pi_logits_k[b,k,:])
+//   pi_probs[b,a]      = Σ_k gate_probs[b,k] · pi_probs_k[b,k,a]
+//   pi_logits[b,a]     = log(pi_probs[b,a] + ε)
+//
+// ── Backward chain implemented by this file (two kernels) ───────────────
+//
+// (1) `multi_head_policy_backward_pi` — distributes incoming `grad_pi_logits`
+//     through the mixture and per-head softmax. Outputs:
+//       a. grad_pi_logits_k [B × K × N_ACTIONS]  (for aux prior + diag)
+//       b. grad_gate_probs  [B × K]              (consumed by kernel 2)
+//       c. grad_W_heads_pb  [B × K × N_ACTIONS × HIDDEN_DIM]
+//       d. grad_b_heads_pb  [B × K × N_ACTIONS]
+//       e. grad_h_t_scratch [B × HIDDEN_DIM]     (OVERWRITE; caller folds
+//                                                 via grad_h_accumulate_scaled)
+//
+// (2) `multi_head_policy_backward_gate` — distributes `grad_gate_probs`
+//     through the gating softmax. Outputs:
+//       a. grad_gate_logits  [B × K]                (diag)
+//       b. grad_W_gate_pb    [B × K × REGIME_DIM]
+//       c. grad_b_gate_pb    [B × K]
+//       d. grad_regime_h     [B × REGIME_DIM]       (computed; NOT used
+//                                                    upstream in Phase 2A-B)
+//
+// ── Math (kernel 1) ─────────────────────────────────────────────────────
+//   grad_pi_probs[b,a]    = grad_pi_logits[b,a] / (pi_probs[b,a] + ε)
+//   grad_pi_probs_k[b,k,a] = gate_probs[b,k] · grad_pi_probs[b,a]
+//   grad_gate_probs[b,k]   = Σ_a pi_probs_k[b,k,a] · grad_pi_probs[b,a]
+//
+//   (per-head softmax-Jacobian; standard form):
+//   grad_pi_logits_k[b,k,a] = pi_probs_k[b,k,a]
+//                             · ( grad_pi_probs_k[b,k,a]
+//                                 − Σ_{a'} pi_probs_k[b,k,a'] · grad_pi_probs_k[b,k,a'] )
+//
+// ── Math (kernel 2) ─────────────────────────────────────────────────────
+//   grad_gate_logits[b,k] = gate_probs[b,k]
+//                           · ( grad_gate_probs[b,k]
+//                               − Σ_{k'} gate_probs[b,k'] · grad_gate_probs[b,k'] )
+//
+//   grad_W_gate_pb[b,k,r]  = grad_gate_logits[b,k] · regime_h[b,r]
+//   grad_b_gate_pb[b,k]    = grad_gate_logits[b,k]
+//   grad_regime_h[b,r]     = Σ_k W_gate[k,r] · grad_gate_logits[b,k]
+//
+// ── Per-batch grad scratch convention ───────────────────────────────────
+//   Caller reduces `_pb` buffers via `reduce_axis0`:
+//     grad_W_heads_pb [B × K·N·H]   → grad_W_heads [K·N·H]
+//     grad_b_heads_pb [B × K·N]      → grad_b_heads [K·N]
+//     grad_W_gate_pb  [B × K·R]      → grad_W_gate  [K·R]
+//     grad_b_gate_pb  [B × K]        → grad_b_gate  [K]
+//
+// Per feedback_no_atomicadd: NO atomicAdd. Each output cell has exactly one
+// writer per launch. Per-batch scratch + reduce_axis0 is the standard
+// foxhunt pattern (see ppo_clipped_surrogate.cu::ppo_grad_w_b_h_t).
+//
+// Per feedback_no_nvrtc: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+#define HIDDEN_DIM    128
+#define N_ACTIONS     11
+#define REGIME_DIM    6
+#define MAX_K_HEADS   8       // Compile-time max; runtime K from ISV
+#define LOG_PROB_EPS  1e-12f  // mirrors forward kernel's `+1e-12` guard
+
+// ─────────────────────────────────────────────────────────────────────
+// Kernel 1: backward through the mixture + per-head softmax.
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (HIDDEN_DIM = 128, 1, 1)
+//   shared = MAX_K_HEADS*N_ACTIONS*3 + MAX_K_HEADS + N_ACTIONS ≈ 304 floats
+//
+// Thread c handles one hidden-dim index. Threads 0..N_ACTIONS-1 first
+// reconstruct pi_probs[b,:] and the softmax-Jacobian — only threads with
+// `c < N_ACTIONS` participate in the small reductions. All HIDDEN_DIM
+// threads participate in the per-batch weight-grad emit.
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void multi_head_policy_backward_pi(
+    const float* __restrict__ grad_pi_logits, // [B × N_ACTIONS] incoming grad on log-mixture
+    const float* __restrict__ h_t,            // [B × HIDDEN_DIM]
+    const float* __restrict__ W_heads,        // [K × N_ACTIONS × HIDDEN_DIM]
+    const float* __restrict__ gate_probs,     // [B × K]  forward output
+    const float* __restrict__ pi_probs_k,     // [B × K × N_ACTIONS]  forward output
+    const int    B,
+    const int    K,
+    float*       __restrict__ grad_pi_logits_k,   // [B × K × N_ACTIONS] OUT (for aux + diag)
+    float*       __restrict__ grad_gate_probs,    // [B × K]             OUT (→ kernel 2)
+    float*       __restrict__ grad_W_heads_pb,    // [B × K × N_ACTIONS × HIDDEN_DIM]
+    float*       __restrict__ grad_b_heads_pb,    // [B × K × N_ACTIONS]
+    float*       __restrict__ grad_h_t_scratch    // [B × HIDDEN_DIM] (OVERWRITE)
+) {
+    const int b = blockIdx.x;
+    if (b >= B) return;
+    const int c = threadIdx.x;  // hidden-dim index, 0..HIDDEN_DIM-1
+
+    // ── Shared state (per-batch) ──────────────────────────────────────
+    __shared__ float s_pi_probs[N_ACTIONS];                       // mixture probs
+    __shared__ float s_grad_pi_probs[N_ACTIONS];                  // dL/dp[a]
+    __shared__ float s_gate_probs[MAX_K_HEADS];                   // forward gate
+    __shared__ float s_pi_probs_k[MAX_K_HEADS * N_ACTIONS];       // forward per-head probs
+    __shared__ float s_grad_pi_probs_k[MAX_K_HEADS * N_ACTIONS];  // step 2 intermediate
+    __shared__ float s_grad_pi_logits_k[MAX_K_HEADS * N_ACTIONS]; // final per-head logit grad
+    __shared__ float s_dot_k[MAX_K_HEADS];                        // softmax-Jacobian scalar per head
+
+    // ── Stage forward outputs (small, per-batch) into shared mem ───────
+    if (c < K) {
+        s_gate_probs[c] = gate_probs[b * K + c];
+    }
+    if (c < N_ACTIONS) {
+        const int gpi_idx = b * N_ACTIONS + c;
+        s_grad_pi_probs[c] = 0.0f;  // accumulator, populated below
+        // Stage pi_probs_k[b, :, c] across all heads.
+        for (int k = 0; k < K; ++k) {
+            s_pi_probs_k[k * N_ACTIONS + c] =
+                pi_probs_k[(b * K + k) * N_ACTIONS + c];
+        }
+        // Reconstruct pi_probs[b, c] = Σ_k gate · pi_probs_k.
+        // Sequential summation order matches the forward kernel for
+        // determinism.
+        float p = 0.0f;
+        #pragma unroll
+        for (int k = 0; k < K; ++k) {
+            p += gate_probs[b * K + k] * pi_probs_k[(b * K + k) * N_ACTIONS + c];
+        }
+        s_pi_probs[c] = p;
+        // dL/dp[a] = dL/dlog(p+ε) × 1/(p+ε)
+        const float gl = grad_pi_logits[gpi_idx];
+        s_grad_pi_probs[c] = gl / (s_pi_probs[c] + LOG_PROB_EPS);
+    }
+    __syncthreads();
+
+    // ── Step 2: grad_pi_probs_k + grad_gate_probs ─────────────────────
+    // grad_pi_probs_k[b,k,a] = gate_probs[b,k] · grad_pi_probs[b,a]
+    // grad_gate_probs[b,k]   = Σ_a pi_probs_k[b,k,a] · grad_pi_probs[b,a]
+    if (c < N_ACTIONS) {
+        for (int k = 0; k < K; ++k) {
+            s_grad_pi_probs_k[k * N_ACTIONS + c] =
+                s_gate_probs[k] * s_grad_pi_probs[c];
+        }
+    }
+    __syncthreads();
+
+    // Thread k computes Σ_a pi_probs_k[k,a] · grad_pi_probs[a] for its head.
+    if (c < K) {
+        float gp = 0.0f;
+        #pragma unroll
+        for (int a = 0; a < N_ACTIONS; ++a) {
+            gp += s_pi_probs_k[c * N_ACTIONS + a] * s_grad_pi_probs[a];
+        }
+        grad_gate_probs[b * K + c] = gp;
+    }
+    __syncthreads();
+
+    // ── Step 3: per-head softmax-Jacobian → grad_pi_logits_k ──────────
+    // dot_k[b,k] = Σ_{a'} pi_probs_k[k,a'] · grad_pi_probs_k[k,a']
+    if (c < K) {
+        float dot = 0.0f;
+        #pragma unroll
+        for (int a = 0; a < N_ACTIONS; ++a) {
+            dot += s_pi_probs_k[c * N_ACTIONS + a]
+                 * s_grad_pi_probs_k[c * N_ACTIONS + a];
+        }
+        s_dot_k[c] = dot;
+    }
+    __syncthreads();
+
+    if (c < N_ACTIONS) {
+        for (int k = 0; k < K; ++k) {
+            const int kak = k * N_ACTIONS + c;
+            const float gl = s_pi_probs_k[kak]
+                           * ( s_grad_pi_probs_k[kak] - s_dot_k[k] );
+            s_grad_pi_logits_k[kak] = gl;
+            // Persist to global memory for aux prior kernel + diagnostics.
+            grad_pi_logits_k[(b * K + k) * N_ACTIONS + c] = gl;
+        }
+    }
+    __syncthreads();
+
+    // ── Step 4: per-batch weight grads + grad_h_t ─────────────────────
+    // Each thread c is the sole writer of:
+    //   grad_W_heads_pb[b, k, a, c]   for all (k, a)
+    //   grad_h_t_scratch[b, c]
+    // Threads c<K * N_ACTIONS additionally write grad_b_heads_pb[b, k, a].
+    if (c < HIDDEN_DIM) {
+        const float h_bc = h_t[b * HIDDEN_DIM + c];
+        float gh_acc = 0.0f;
+        for (int k = 0; k < K; ++k) {
+            for (int a = 0; a < N_ACTIONS; ++a) {
+                const int kak = k * N_ACTIONS + a;
+                const float g = s_grad_pi_logits_k[kak];
+                // grad_W_heads_pb[b, k, a, c] = g * h[b, c]
+                grad_W_heads_pb[(long long)((b * K + k) * N_ACTIONS + a) * HIDDEN_DIM + c]
+                    = g * h_bc;
+                // Accumulate grad_h_t[b, c] = Σ_{k,a} g · W_heads[k, a, c]
+                gh_acc += g * W_heads[(long long)((k * N_ACTIONS) + a) * HIDDEN_DIM + c];
+            }
+        }
+        // OVERWRITE — caller folds via grad_h_accumulate_scaled.
+        grad_h_t_scratch[b * HIDDEN_DIM + c] = gh_acc;
+    }
+
+    // Bias grads — sole-writer per (b, k, a). Use the first K*N_ACTIONS
+    // threads to cover the per-(k, a) slots in one pass.
+    if (c < K * N_ACTIONS) {
+        const int k = c / N_ACTIONS;
+        const int a = c % N_ACTIONS;
+        grad_b_heads_pb[(b * K + k) * N_ACTIONS + a] =
+            s_grad_pi_logits_k[k * N_ACTIONS + a];
+    }
+}
+
+// ─────────────────────────────────────────────────────────────────────
+// Kernel 2: backward through the gating softmax.
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (max(K, REGIME_DIM) = 8, 1, 1)
+//
+// Tiny block — K≤8 and REGIME_DIM=6. Thread layout is per-head for the
+// softmax-Jacobian reduction, per-regime-dim for the regime-grad output.
+// We use the same threads for both phases since both dimensions are ≤8.
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void multi_head_policy_backward_gate(
+    const float* __restrict__ grad_gate_probs, // [B × K] from kernel 1
+    const float* __restrict__ gate_probs,      // [B × K] forward output
+    const float* __restrict__ regime_h,        // [B × REGIME_DIM]
+    const float* __restrict__ W_gate,          // [K × REGIME_DIM]
+    const int    B,
+    const int    K,
+    float*       __restrict__ grad_gate_logits,// [B × K]            OUT (for diag)
+    float*       __restrict__ grad_W_gate_pb,  // [B × K × REGIME_DIM]
+    float*       __restrict__ grad_b_gate_pb,  // [B × K]
+    float*       __restrict__ grad_regime_h    // [B × REGIME_DIM] (computed; unused upstream)
+) {
+    const int b = blockIdx.x;
+    if (b >= B) return;
+    const int tid = threadIdx.x;
+
+    __shared__ float s_gate_probs[MAX_K_HEADS];
+    __shared__ float s_grad_gate_probs[MAX_K_HEADS];
+    __shared__ float s_grad_gate_logits[MAX_K_HEADS];
+    __shared__ float s_dot;  // Σ_{k'} gate · grad_gate_probs
+
+    // ── Stage forward + incoming grad ─────────────────────────────────
+    if (tid < K) {
+        s_gate_probs[tid] = gate_probs[b * K + tid];
+        s_grad_gate_probs[tid] = grad_gate_probs[b * K + tid];
+    }
+    __syncthreads();
+
+    // ── Softmax-Jacobian reduction (single thread for determinism) ────
+    if (tid == 0) {
+        float dot = 0.0f;
+        for (int k = 0; k < K; ++k) {
+            dot += s_gate_probs[k] * s_grad_gate_probs[k];
+        }
+        s_dot = dot;
+    }
+    __syncthreads();
+
+    // ── grad_gate_logits[b, k] = p · (dp − dot) ───────────────────────
+    if (tid < K) {
+        const float gl = s_gate_probs[tid] * (s_grad_gate_probs[tid] - s_dot);
+        s_grad_gate_logits[tid] = gl;
+        grad_gate_logits[b * K + tid] = gl;
+        grad_b_gate_pb[b * K + tid] = gl;
+    }
+    __syncthreads();
+
+    // ── grad_W_gate_pb[b, k, r] = grad_gate_logits[k] · regime_h[r] ───
+    // Cover all (k, r) slots — K*REGIME_DIM ≤ 48 — using a single loop
+    // per active thread. Thread `tid` handles its column across all k.
+    if (tid < REGIME_DIM) {
+        const float r_b = regime_h[b * REGIME_DIM + tid];
+        for (int k = 0; k < K; ++k) {
+            grad_W_gate_pb[((b * K + k) * REGIME_DIM) + tid] =
+                s_grad_gate_logits[k] * r_b;
+        }
+    }
+
+    // ── grad_regime_h[b, r] = Σ_k W_gate[k, r] · grad_gate_logits[k] ──
+    // Computed but NOT propagated upstream in Phase 2A-B (regime_h is
+    // loader-precomputed in foxhunt). Allocate + write the buffer so a
+    // future phase can route it if needed.
+    if (tid < REGIME_DIM) {
+        float gr = 0.0f;
+        #pragma unroll
+        for (int k = 0; k < K; ++k) {
+            gr += W_gate[k * REGIME_DIM + tid] * s_grad_gate_logits[k];
+        }
+        grad_regime_h[b * REGIME_DIM + tid] = gr;
+    }
+}

crates/ml-alpha/cuda/multi_head_policy_forward.cu

@@ -0,0 +1,136 @@
+// multi_head_policy_forward.cu — K-head policy logit + mixture combination.
+//
+// Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//       ADDENDUM 2026-06-03 §R.6
+// Plan: docs/superpowers/plans/2026-06-03-multi-head-policy-implementation.md (Phase 2A-A)
+//
+// Per-(batch, head) computes pi_logits_k = W_k @ h_t + b_k (HIDDEN_DIM=128 → N_ACTIONS=11).
+// Then per-batch computes the mixture:
+//   pi_probs_k[b, k, a] = softmax_a(pi_logits_k[b, k, :])
+//   pi_probs[b, a]      = Σ_k gate_probs[b, k] · pi_probs_k[b, k, a]
+//   pi_logits[b, a]     = log(pi_probs[b, a] + 1e-12)
+//
+// Deterministic by construction: per-batch sequential mixture sum (no parallel
+// reductions across batches; the only reduction is over K=3 heads with fixed
+// summation order). Sole-writer per output cell.
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (N_ACTIONS = 11, 1, 1)
+//   One block per batch. N_ACTIONS threads. Each thread owns one action across
+//   all K heads; loops K times for per-head matmul + softmax + mixture combine.
+//
+// Per feedback_no_atomicadd: no atomic ops.
+// Per feedback_no_nvrtc: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+#define HIDDEN_DIM    128
+#define N_ACTIONS     11
+#define MAX_K_HEADS   8       // Compile-time max; runtime K from ISV
+
+extern "C" __global__ void multi_head_policy_forward(
+    const float* __restrict__ h_t,            // [B × HIDDEN_DIM]
+    const float* __restrict__ W_heads,        // [K × N_ACTIONS × HIDDEN_DIM]
+    const float* __restrict__ b_heads,        // [K × N_ACTIONS]
+    const float* __restrict__ gate_probs,     // [B × K]  — already softmax'd
+    float*       __restrict__ pi_logits_k,    // [B × K × N_ACTIONS]   (output, for backward)
+    float*       __restrict__ pi_probs_k,     // [B × K × N_ACTIONS]   (output, for backward)
+    float*       __restrict__ pi_logits,      // [B × N_ACTIONS]       (output, mixture)
+    const int B,
+    const int K
+) {
+    const int b = blockIdx.x;
+    if (b >= B) return;
+
+    const int tid = threadIdx.x;  // 0..N_ACTIONS-1
+
+    __shared__ float s_pi_logits_k[MAX_K_HEADS * N_ACTIONS];
+    __shared__ float s_pi_probs_k[MAX_K_HEADS * N_ACTIONS];
+    __shared__ float s_pi_probs[N_ACTIONS];
+    __shared__ float s_max_k[MAX_K_HEADS];     // for softmax stability
+    __shared__ float s_sum_k[MAX_K_HEADS];
+
+    // ── Step 1: per-head linear projection ───────────────────────────────
+    // pi_logits_k[b, k, a] = Σ_j W_heads[k, a, j] × h_t[b, j] + b_heads[k, a]
+    // One thread per action; loops over k inside thread.
+    if (tid < N_ACTIONS) {
+        for (int k = 0; k < K; ++k) {
+            float gl = b_heads[k * N_ACTIONS + tid];
+            #pragma unroll
+            for (int j = 0; j < HIDDEN_DIM; ++j) {
+                gl += W_heads[(k * N_ACTIONS + tid) * HIDDEN_DIM + j]
+                      * h_t[b * HIDDEN_DIM + j];
+            }
+            s_pi_logits_k[k * N_ACTIONS + tid] = gl;
+        }
+    }
+    __syncthreads();
+
+    // ── Step 2: per-head softmax (max-subtract for stability) ────────────
+    // Threads 0..K-1 compute per-head max over the N_ACTIONS logits.
+    if (tid < K) {
+        float mx = s_pi_logits_k[tid * N_ACTIONS];
+        #pragma unroll
+        for (int a = 1; a < N_ACTIONS; ++a) {
+            float v = s_pi_logits_k[tid * N_ACTIONS + a];
+            mx = fmaxf(mx, v);
+        }
+        s_max_k[tid] = mx;
+    }
+    __syncthreads();
+
+    // Each action-thread exponentiates its slot for every head.
+    if (tid < N_ACTIONS) {
+        for (int k = 0; k < K; ++k) {
+            float v = expf(s_pi_logits_k[k * N_ACTIONS + tid] - s_max_k[k]);
+            s_pi_probs_k[k * N_ACTIONS + tid] = v;
+        }
+    }
+    __syncthreads();
+
+    // Threads 0..K-1 reduce per-head sum (denominator).
+    if (tid < K) {
+        float sm = 0.0f;
+        #pragma unroll
+        for (int a = 0; a < N_ACTIONS; ++a) {
+            sm += s_pi_probs_k[tid * N_ACTIONS + a];
+        }
+        s_sum_k[tid] = sm;
+    }
+    __syncthreads();
+
+    // Normalize.
+    if (tid < N_ACTIONS) {
+        for (int k = 0; k < K; ++k) {
+            s_pi_probs_k[k * N_ACTIONS + tid] /= s_sum_k[k];
+        }
+    }
+    __syncthreads();
+
+    // ── Step 3: mixture ──────────────────────────────────────────────────
+    // pi_probs[b, a] = Σ_k gate_probs[b, k] · pi_probs_k[k, a]
+    // Sequential summation order over K (deterministic).
+    if (tid < N_ACTIONS) {
+        float p = 0.0f;
+        #pragma unroll
+        for (int k = 0; k < K; ++k) {
+            p += gate_probs[b * K + k] * s_pi_probs_k[k * N_ACTIONS + tid];
+        }
+        s_pi_probs[tid] = p;
+    }
+    __syncthreads();
+
+    // ── Step 4: write outputs ────────────────────────────────────────────
+    // pi_logits[b, a] = log(pi_probs[b, a] + 1e-12) for downstream softmax callers.
+    // Also stash per-head logits + probs for the Phase 2A-B backward kernel.
+    if (tid < N_ACTIONS) {
+        pi_logits[b * N_ACTIONS + tid] = logf(s_pi_probs[tid] + 1e-12f);
+        for (int k = 0; k < K; ++k) {
+            pi_logits_k[(b * K + k) * N_ACTIONS + tid] =
+                s_pi_logits_k[k * N_ACTIONS + tid];
+            pi_probs_k[(b * K + k) * N_ACTIONS + tid] =
+                s_pi_probs_k[k * N_ACTIONS + tid];
+        }
+    }
+}

crates/ml-alpha/cuda/multi_head_policy_gate_forward.cu

@@ -0,0 +1,90 @@
+// multi_head_policy_gate_forward.cu — gating head from raw regime features.
+//
+// Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//       ADDENDUM 2026-06-03 §R.3 Option B (regime-direct gating, bypass VSN)
+// Plan: docs/superpowers/plans/2026-06-03-multi-head-policy-implementation.md (Phase 2A-A)
+//
+// gate_logits[b, k] = Σ_j W_gate[k, j] × regime_h[b, j] + b_gate[k]
+// gate_probs[b, k]  = softmax_k(gate_logits[b])
+//
+// Reads regime_h DIRECTLY (parallel channel — does NOT go through VSN/Mamba2).
+// This is the load-bearing architectural choice motivated by the empirical
+// regime-attenuation finding (pearl_local_smoke_noise_floor_and_regime_concentration):
+// VSN's softmax-over-40 gating structurally limits any single encoder-input
+// feature to ~1/40 of attention budget, suppressing vol-axis routing. The gate
+// reads regime[0..6] without that bottleneck.
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (K, 1, 1)    — typically K=3, ≤ MAX_K_HEADS=8
+//   One block per batch. K threads cooperate via shared-mem reductions.
+//
+// Per feedback_no_atomicadd: no atomic ops.
+// Per feedback_no_nvrtc: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+#define REGIME_DIM      6
+#define MAX_K_HEADS     8
+
+extern "C" __global__ void multi_head_policy_gate_forward(
+    const float* __restrict__ regime_h,       // [B × REGIME_DIM=6]
+    const float* __restrict__ W_gate,         // [K × REGIME_DIM]
+    const float* __restrict__ b_gate,         // [K]
+    float*       __restrict__ gate_logits,    // [B × K] (output, for backward)
+    float*       __restrict__ gate_probs,     // [B × K] (output, post-softmax)
+    const int B,
+    const int K
+) {
+    const int b = blockIdx.x;
+    if (b >= B) return;
+
+    const int tid = threadIdx.x;
+    __shared__ float s_logits[MAX_K_HEADS];     // pre-softmax logits
+    __shared__ float s_exp[MAX_K_HEADS];        // exp(logit - max) for softmax
+    __shared__ float s_max;
+    __shared__ float s_sum;
+
+    // ── Step 1: linear projection ────────────────────────────────────────
+    // gate_logits[b, k] = Σ_j W_gate[k, j] × regime_h[b, j] + b_gate[k]
+    // One thread per head k.
+    if (tid < K) {
+        float gl = b_gate[tid];
+        #pragma unroll
+        for (int j = 0; j < REGIME_DIM; ++j) {
+            gl += W_gate[tid * REGIME_DIM + j] * regime_h[b * REGIME_DIM + j];
+        }
+        s_logits[tid] = gl;
+        // Persist pre-softmax logits to gmem for the Phase 2A-B backward kernel.
+        gate_logits[b * K + tid] = gl;
+    }
+    __syncthreads();
+
+    // ── Step 2: softmax (max-subtract for stability) ─────────────────────
+    if (tid == 0) {
+        float mx = s_logits[0];
+        for (int k = 1; k < K; ++k) {
+            mx = fmaxf(mx, s_logits[k]);
+        }
+        s_max = mx;
+    }
+    __syncthreads();
+
+    if (tid < K) {
+        s_exp[tid] = expf(s_logits[tid] - s_max);
+    }
+    __syncthreads();
+
+    if (tid == 0) {
+        float sm = 0.0f;
+        for (int k = 0; k < K; ++k) {
+            sm += s_exp[k];
+        }
+        s_sum = sm;
+    }
+    __syncthreads();
+
+    if (tid < K) {
+        gate_probs[b * K + tid] = s_exp[tid] / s_sum;
+    }
+}

crates/ml-alpha/cuda/ppo_clipped_surrogate.cu

@@ -29,33 +29,26 @@
 //                  combined with the clip mask (gradient of the surrogate
 //                  is zero in the clipped region).
 //
-// PHASE D scope: kernel signature + per-element body. The atomicAdd in
-// the loss accumulator is the same loud-flagged deferral as Phase C's
-// dqn_distributional_q_bwd — see ATOMIC NOTE below. Phase E refactors
-// to warp-shuffle reduce across batches.
-//
-// ATOMIC NOTE (deliberate, deferred fix): the cross-batch loss
-// accumulators (loss_pi / loss_entropy) use `atomicAdd`. This nominally
-// violates `feedback_no_atomicadd.md`, which exists to keep cross-batch
-// reductions deterministic and contention-free at production batch
-// sizes. We accept it HERE in Phase D because:
-//   (a) the toy-bandit smoke runs with B ≤ 32, so atomic contention is
-//       negligible (32 writers on a single L2 line);
-//   (b) the loss scalars are purely diagnostic — gradient flow goes
-//       through `grad_logits`, which is NEVER atomicAdded;
-//   (c) Phase E replaces this with a two-stage warp-shuffle → shared
-//       reduce → single-writer store, matching the `aux_loss.cu` pattern,
-//       when the trainer batches reach production sizes (B = 256+).
-// Documented loudly here so the audit trail is visible at the kernel
-// header without diving into the loss kernel body.
+// REDUCTION DISCIPLINE (per `feedback_no_atomicadd.md`):
+//   Each block (= one batch element) is the SOLE writer of its own slot
+//   in two per-batch buffers — `loss_pi_per_b[batch]` and
+//   `loss_entropy_per_b[batch]`. No atomicAdd. The scalar diagnostics
+//   the trainer reads (mean over batch) are produced by a separate
+//   `ppo_loss_reduce_b` block tree-reduce kernel that the trainer calls
+//   immediately after this kernel. This eliminates the staleness bug
+//   that inflated `last_pi_loss` by N steps (the old mapped-pinned
+//   scalar was never zeroed between forwards, so an atomicAdd from
+//   every step kept accumulating; local 1k × ~9 ≈ 9080 and cluster
+//   20k × ~1200 ≈ 24M were both bit-exact step-count fingerprints of
+//   that accumulator — see commit log for the diagnosis trail).
 //
 // Block layout:
 //   Forward:  grid = (B, 1, 1); block = (N_ACTIONS, 1, 1).
 //             One block per batch element, one thread per action.
 //             Shared-mem softmax (max + sumexp) computed by thread 0
 //             then broadcast. Thread 0 also writes the per-batch loss
-//             contributions (the surrogate only depends on the taken
-//             action, so no parallelism is wasted there).
+//             slots (the surrogate only depends on the taken action,
+//             so no parallelism is wasted there).
 //   Backward: same layout. Each thread writes its own logit's gradient.
 
 #define HIDDEN_DIM                       128
@@ -133,23 +126,39 @@ extern "C" __global__ void ppo_policy_logits_fwd(
 //   isv           [≥ 404]          — reads ε at 402, coef at 403
 //   B                              — batch size
 // Outputs:
-//   pi_log_prob   [B]              — log π_new(a_taken|s) for diagnostics
-//                                    and Phase E KL EMA
-//   entropy       [B]              — H(π_new) per batch sample
-//   loss_pi       [1]              — Σ_b L_π (ATOMIC; see header)
-//   loss_entropy  [1]              — Σ_b L_entropy
+//   pi_log_prob          [B]      — log π_new(a_taken|s) for diagnostics
+//                                   and Phase E KL EMA
+//   entropy              [B]      — H(π_new) per batch sample
+//   loss_pi_per_b        [B]      — per-batch L_π (single writer per slot,
+//                                   NO atomicAdd). Reduced to scalar mean
+//                                   by `ppo_loss_reduce_b`.
+//   loss_entropy_per_b   [B]      — per-batch L_entropy, same discipline.
 // ─────────────────────────────────────────────────────────────────────
 extern "C" __global__ void ppo_clipped_surrogate_fwd(
-    const float* __restrict__ logits,        // [B * N_ACTIONS]
-    const float* __restrict__ log_pi_old,    // [B]
-    const int*   __restrict__ actions,       // [B]
-    const float* __restrict__ advantages,    // [B]
-    const float* __restrict__ isv,           // [>= 404]
+    const float* __restrict__ logits,               // [B * N_ACTIONS]
+    const float* __restrict__ log_pi_old,           // [B]
+    const int*   __restrict__ actions,              // [B]
+    const float* __restrict__ advantages,           // [B]
+    const float* __restrict__ isv,                  // [>= 404]
     int          B,
-    float*       __restrict__ pi_log_prob,   // [B]
-    float*       __restrict__ entropy,       // [B]
-    float*       __restrict__ loss_pi,       // [1]
-    float*       __restrict__ loss_entropy   // [1]
+    float*       __restrict__ pi_log_prob,          // [B]
+    float*       __restrict__ entropy,              // [B]
+    float*       __restrict__ loss_pi_per_b,        // [B]
+    float*       __restrict__ loss_entropy_per_b,   // [B]
+    // B-10 (2026-06-01) G3+G4: per-batch observability scratches.
+    // Pure observability; written ALONGSIDE existing loss_pi_per_b — does
+    // NOT perturb the loss reduce path (`ppo_loss_reduce_b.cu`). Consumed
+    // by the dedicated reducer `rl_ppo_diagnostic_stats_reduce.cu` which
+    // folds these [B] arrays into ISV slots 735-742. σ_used (= sqrt(var_
+    // pre_norm) from slot 612) is constant per step → reducer computes
+    // it once and reconstructs |A_unnorm| statistics from |A_norm| stats
+    // (no per-batch unnorm scratch needed). The kernel's existing math
+    // (softmax, ratio clamp, surr1/surr2 → l_pi) is byte-identical to
+    // pre-B-10; new writes happen in the same `act == 0` branch.
+    float*       __restrict__ ppo_a_norm_pb,        // [B] |advantages[batch]|
+    float*       __restrict__ ppo_ratio_dev_pb,     // [B] |ratio − 1|
+    float*       __restrict__ ppo_ratio_clipped_pb, // [B] {0.0, 1.0} outside [1-ε, 1+ε]
+    float*       __restrict__ ppo_surrogate_pb      // [B] clipped surrogate (no entropy bonus)
 ) {
     const int batch = blockIdx.x;
     const int act   = threadIdx.x;
@@ -244,14 +253,41 @@ extern "C" __global__ void ppo_clipped_surrogate_fwd(
             const float coef  = isv[RL_ENTROPY_COEF_INDEX];
             const float l_ent = -coef * h;
 
-            // ATOMIC NOTE: see header. Phase E warp-shuffles these out.
-            // /B for batch-invariant loss reporting.
-            const float b_inv = 1.0f / (float)B;
-            atomicAdd(loss_pi,      l_pi * b_inv);
-            atomicAdd(loss_entropy, l_ent * b_inv);
+            // Sole writer of per-batch loss slots. No atomicAdd — the
+            // [B] → [1] mean reduction lives in `ppo_loss_reduce_b`.
+            loss_pi_per_b[batch]      = l_pi;
+            loss_entropy_per_b[batch] = l_ent;
+
+            // B-10 G3+G4: per-batch observability writes.
+            // surrogate (no entropy bonus) = -l_pi (l_pi negates min in line
+            // above; the canonical surrogate value Schulman PPO reports is
+            // mean of min(ratio*A, clip*A), so we re-construct it here).
+            // Magnitudes intentional: max/mean reductions need positive values.
+            ppo_a_norm_pb[batch]        = fabsf(A);
+            ppo_ratio_dev_pb[batch]     = fabsf(ratio - 1.0f);
+            // Clipped flag: ratio outside [1-ε, 1+ε] band. We use the
+            // pre-magnitude-clamp `ratio_raw` so it captures excursions
+            // the rl_ppo_ratio_clamp_controller's hard clamp would also
+            // catch; consistent with how ppo_log_ratio_abs_max_b reports.
+            const bool clipped         = (ratio_raw < 1.0f - eps) ||
+                                          (ratio_raw > 1.0f + eps);
+            ppo_ratio_clipped_pb[batch] = clipped ? 1.0f : 0.0f;
+            // Clipped surrogate (Schulman canonical): min(surr1, surr2).
+            // l_pi above = -min(surr1, surr2); negate back to the natural
+            // surrogate value so positive surrogate = positive expected
+            // policy-improvement direction.
+            ppo_surrogate_pb[batch]     = -l_pi;
         } else {
-            // Invalid action; leave diagnostics at 0, skip loss accum.
-            pi_log_prob[batch] = 0.0f;
+            // Invalid action; zero per-batch loss slots + diagnostic
+            // (caller's reducer treats these slots like any other).
+            pi_log_prob[batch]        = 0.0f;
+            loss_pi_per_b[batch]      = 0.0f;
+            loss_entropy_per_b[batch] = 0.0f;
+            // B-10: zero observability scratches consistently.
+            ppo_a_norm_pb[batch]        = 0.0f;
+            ppo_ratio_dev_pb[batch]     = 0.0f;
+            ppo_ratio_clipped_pb[batch] = 0.0f;
+            ppo_surrogate_pb[batch]     = 0.0f;
         }
     }
 }

crates/ml-alpha/cuda/ppo_loss_reduce_b.cu

@@ -0,0 +1,102 @@
+// ppo_loss_reduce_b.cu — [B] → [1] mean reducer for the two PPO loss
+// scalars produced by `ppo_clipped_surrogate_fwd`.
+//
+// Replaces the prior `atomicAdd(loss_pi, l_pi/B)` pattern. Per
+// `feedback_no_atomicadd.md`: block tree-reduce in shared memory only,
+// no atomics. The forward kernel writes per-batch values to
+// `loss_pi_per_b[B]` and `loss_entropy_per_b[B]` (single writer per
+// slot), then this kernel reduces each to a scalar mean.
+//
+// Computes:
+//   loss_pi_out[0]      = (1/B) * Σ_b loss_pi_per_b[b]
+//   loss_entropy_out[0] = (1/B) * Σ_b loss_entropy_per_b[b]
+//
+// Block layout:
+//   grid  = (1, 1, 1)
+//   block = (BLOCK_X, 1, 1)         (BLOCK_X = 256; power of 2 required)
+//   shared = 2 * BLOCK_X * sizeof(float)
+//
+// Caller passes B = batch size; the kernel grid-strides if B > BLOCK_X
+// (so a single launch supports any cluster batch size).
+
+#define BLOCK_X 256
+
+extern "C" __global__ void ppo_loss_reduce_b(
+    const float* __restrict__ loss_pi_per_b,        // [B]
+    const float* __restrict__ loss_entropy_per_b,   // [B]
+    int                       B,
+    float*       __restrict__ loss_pi_out,          // [1]  OVERWRITE
+    float*       __restrict__ loss_entropy_out      // [1]  OVERWRITE
+) {
+    __shared__ float s_pi[BLOCK_X];
+    __shared__ float s_ent[BLOCK_X];
+
+    const int tid = threadIdx.x;
+
+    // Per-thread grid-stride sum over the [B] axis.
+    float local_pi  = 0.0f;
+    float local_ent = 0.0f;
+    for (int b = tid; b < B; b += BLOCK_X) {
+        local_pi  += loss_pi_per_b[b];
+        local_ent += loss_entropy_per_b[b];
+    }
+    s_pi[tid]  = local_pi;
+    s_ent[tid] = local_ent;
+    __syncthreads();
+
+    // Block tree-reduce in shared memory. BLOCK_X must be a power of 2.
+    for (int stride = BLOCK_X / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_pi[tid]  += s_pi[tid  + stride];
+            s_ent[tid] += s_ent[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    // Single-writer store of the batch-mean diagnostics.
+    if (tid == 0) {
+        const float b_inv = 1.0f / (float)((B > 0) ? B : 1);
+        loss_pi_out[0]      = s_pi[0]  * b_inv;
+        loss_entropy_out[0] = s_ent[0] * b_inv;
+    }
+}
+
+
+// ─────────────────────────────────────────────────────────────────────
+// mean_reduce_b_f32 — single-input variant of the same pattern. Used by
+// `dqn_distributional_q_bwd` whose per-batch CE values live in
+// `loss_per_batch[B]` (single-writer already); this kernel produces
+// the scalar mean for the trainer's diagnostic readout, replacing the
+// prior `atomicAdd(loss_out, ce / B)` (Phase C "loud-flagged deferral"
+// — see dqn_distributional_q.cu header).
+//
+// Block layout: identical to `ppo_loss_reduce_b`.
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void mean_reduce_b_f32(
+    const float* __restrict__ values_per_b,   // [B]
+    int                       B,
+    float*       __restrict__ mean_out        // [1]  OVERWRITE
+) {
+    __shared__ float s_val[BLOCK_X];
+
+    const int tid = threadIdx.x;
+
+    float local = 0.0f;
+    for (int b = tid; b < B; b += BLOCK_X) {
+        local += values_per_b[b];
+    }
+    s_val[tid] = local;
+    __syncthreads();
+
+    for (int stride = BLOCK_X / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_val[tid] += s_val[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float b_inv = 1.0f / (float)((B > 0) ? B : 1);
+        mean_out[0] = s_val[0] * b_inv;
+    }
+}

crates/ml-alpha/cuda/rl_advantage_normalize.cu

@@ -0,0 +1,97 @@
+// rl_advantage_normalize.cu — Phase 4.5 per-batch advantage normalization (2026-05-30).
+//
+// Standard PPO practice (Schulman et al. 2017): normalize per-batch
+// advantages before the PPO surrogate computation:
+//
+//   mean = (1/B) Σ_b advantage[b]
+//   var  = (1/B) Σ_b (advantage[b] − mean)²
+//   std  = sqrt(var + ε²)
+//   advantage_norm[b] = (advantage[b] − mean) / std    (in-place)
+//
+// Why: PPO surrogate = ratio × A. Without normalization, |A| can vary
+// 1000× across batches → l_pi magnitude unstable → Adam's per-parameter
+// scaling still functional, but gradient direction confidence drops
+// when advantage magnitudes are wildly inconsistent.
+//
+// In Phase 4.3, V_dq baseline produced advantages with ~100× more
+// variance than Plan A v2's V_scalar baseline → l_pi grew to 1.6e9
+// vs Plan A v2's 3.6e5. Adam internally normalizes, but the policy
+// updates have higher variance per step → pnl trajectory chops.
+//
+// Per pearl_adaptive_not_tuned: this normalization is self-adaptive
+// (uses observed per-batch statistics, no tuned hyperparameters).
+// Per pearl_blend_formulas_must_have_permanent_floor: ε² floor on
+// variance prevents div-by-zero when all advantages are identical.
+//
+// Block layout: grid=(1, 1, 1), block=(BLOCK_X=1024, 1, 1). Single
+// block does parallel reduction for mean → variance → normalize.
+// Suitable for batch sizes up to B=1024 (current production scale).
+
+#define BLOCK_X 1024
+#define ADVANTAGE_VAR_FLOOR 1e-6f
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// emit raw per-batch advantage variance to ISV[612] BEFORE the in-place
+// normalize. `rl_rollout_steps_controller` consumes this as its driving
+// signal — post-normalization variance is definitionally ~ε² floor under
+// Phase 4.5 and useless as a controller input. Pre-norm variance is the
+// real signal of "how much advantage spread the policy is producing".
+#define RL_ADV_VAR_PRE_NORM_INDEX 612
+
+extern "C" __global__ void rl_advantage_normalize(
+    float* __restrict__ advantage,  // [B] in-place
+    float* __restrict__ isv,        // ISV bus — only ADV_VAR_PRE_NORM written
+    int    B
+) {
+    const int tid = threadIdx.x;
+    if (tid >= BLOCK_X) return;
+
+    // ── Pass 1: compute mean ──
+    __shared__ float s_sum[BLOCK_X];
+    float sum_partial = 0.0f;
+    for (int b = tid; b < B; b += BLOCK_X) {
+        sum_partial += advantage[b];
+    }
+    s_sum[tid] = sum_partial;
+    __syncthreads();
+
+    for (int stride = BLOCK_X / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) s_sum[tid] += s_sum[tid + stride];
+        __syncthreads();
+    }
+    __shared__ float s_mean;
+    if (tid == 0) s_mean = s_sum[0] / (float)B;
+    __syncthreads();
+    const float mean = s_mean;
+
+    // ── Pass 2: compute variance ──
+    __shared__ float s_var[BLOCK_X];
+    float var_partial = 0.0f;
+    for (int b = tid; b < B; b += BLOCK_X) {
+        const float d = advantage[b] - mean;
+        var_partial += d * d;
+    }
+    s_var[tid] = var_partial;
+    __syncthreads();
+
+    for (int stride = BLOCK_X / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) s_var[tid] += s_var[tid + stride];
+        __syncthreads();
+    }
+    __shared__ float s_inv_std;
+    if (tid == 0) {
+        const float var = s_var[0] / (float)B;
+        // Emit raw pre-normalization variance for rl_rollout_steps_controller.
+        // Done BEFORE we add the ε² floor — the controller wants the true
+        // signal, not the numerical-stability-adjusted divisor.
+        isv[RL_ADV_VAR_PRE_NORM_INDEX] = var;
+        s_inv_std = rsqrtf(var + ADVANTAGE_VAR_FLOOR);  // 1/sqrt(var + ε²)
+    }
+    __syncthreads();
+    const float inv_std = s_inv_std;
+
+    // ── Pass 3: normalize in-place ──
+    for (int b = tid; b < B; b += BLOCK_X) {
+        advantage[b] = (advantage[b] - mean) * inv_std;
+    }
+}

crates/ml-alpha/cuda/rl_atom_support_update.cu

@@ -1,7 +1,9 @@
 // rl_atom_support_update.cu — refresh `atom_supports_d` from the
 // ISV-driven [V_MIN, V_MAX] span (audit 2026-05-24 second follow-up).
 //
-// Companion to the C51 atom-span ratchet in rl_reward_clamp_controller.
+// Companion to the C51 atom-span EWMA in rl_reward_clamp_controller
+// (α=0.001, ~700-step half-life — wwcsz followup 2026-05-24 replaced
+// the original ratchet to focus atom resolution on the ACTIVE range).
 // `atom_supports_d` is the device buffer of 21 float values that the
 // non-projection C51 kernels (`argmax_expected_q`, `rl_action_kernel`,
 // `dqn_distributional_q`) read instead of recomputing the per-atom

crates/ml-alpha/cuda/rl_avg_win_loss_ema_update.cu

@@ -0,0 +1,113 @@
+// rl_avg_win_loss_ema_update.cu — Layer 4 (Kelly) input EMA producer.
+//
+// Tracks observed per-trade avg_win and avg_loss magnitudes in USD as
+// EMAs. Kelly fraction uses R-multiple = avg_win / avg_loss together
+// with win_rate to derive the safe Kelly bet size.
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Inputs:
+//   rewards[b]    f32 — per-batch realized pnl delta (shaped) this step
+//   dones[b]      f32 — 1.0 if a trade closed this step, else 0.0
+//
+// Outcome derived inline: win = (done & reward > 0); loss = (done & reward < 0).
+//
+// Outputs:
+//   ISV[RL_AVG_WIN_USD_EMA_INDEX  = 678]  (positive USD)
+//   ISV[RL_AVG_LOSS_USD_EMA_INDEX = 679]  (positive USD, magnitude)
+//
+// Bootstrap semantics per `pearl_first_observation_bootstrap`:
+//   sentinel = 0.0; first non-zero closed-trade step replaces directly.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block (sums sequentially).
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: EMA-α structural smoothing
+// parameter (same as ema_update_per_step convention).
+
+#include <stdint.h>
+
+#define RL_AVG_WIN_USD_EMA_INDEX   678
+#define RL_AVG_LOSS_USD_EMA_INDEX  679
+#define EMA_ALPHA_FAST             0.05f
+// B-6 ISV-driven adaptive asymmetric Wiener-α (2026-06-01 spec).
+// α_slow_eff = α_slow_min + (α_fast − α_slow_min) × trust_eff
+// trust_eff = trust(n) × stability(CV)
+//   trust(n) = min(1, cum_dones / n_full_threshold)         [Phase 1]
+//   stability(CV) = exp(-CV × cv_gain)                       [Phase 2]
+// Slot 721 α_slow_min, 722 n_full_threshold, 723 cv_gain.
+// Welford triplet for reward_magnitude provides CV (Phase 2).
+#define RL_EMA_ALPHA_SLOW_MIN_INDEX       721
+#define RL_EMA_TRUST_FULL_THRESHOLD_INDEX 722
+#define RL_EMA_CV_GAIN_INDEX              723
+#define RL_CUMULATIVE_DONES_INDEX         660
+#define RL_REWARD_MAG_VAR_COUNT_INDEX     615
+#define RL_REWARD_MAG_VAR_MEAN_INDEX      616
+#define RL_REWARD_MAG_VAR_M2_INDEX        617
+
+extern "C" __global__ void rl_avg_win_loss_ema_update(
+    float*       __restrict__ isv,
+    const float* __restrict__ rewards,                   // [b_size] shaped pnl
+    const float* __restrict__ dones,                     // [b_size] 1.0 = close
+    int                       b_size
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    // Sum per-trade win/loss magnitudes across the batch.
+    float sum_win  = 0.0f;
+    float sum_loss = 0.0f;
+    int   n_win    = 0;
+    int   n_loss   = 0;
+    for (int b = 0; b < b_size; ++b) {
+        if (dones[b] < 0.5f) continue;
+        const float p = rewards[b];
+        if (p > 0.0f) {
+            sum_win  += p;
+            n_win    += 1;
+        } else if (p < 0.0f) {
+            sum_loss += fabsf(p);
+            n_loss   += 1;
+        }
+    }
+
+    // B-6 ISV-driven adaptive asymmetric Wiener-α (Bayesian shrinkage).
+    // α_slow_eff blends α_slow_min → α_fast as data confidence grows.
+    const float a_slow_min  = isv[RL_EMA_ALPHA_SLOW_MIN_INDEX];
+    const float a_fast      = EMA_ALPHA_FAST;
+    const float n_trades    = isv[RL_CUMULATIVE_DONES_INDEX];
+    const float n_full      = isv[RL_EMA_TRUST_FULL_THRESHOLD_INDEX];
+    const float cv_gain     = isv[RL_EMA_CV_GAIN_INDEX];
+
+    // Phase 1: data-quantity trust (resets at fold boundary via reset_session_state)
+    float trust = (n_full > 0.0f) ? fminf(1.0f, n_trades / n_full) : 1.0f;
+
+    // Phase 2: signal-volatility gain (set cv_gain=0 to disable)
+    if (cv_gain > 0.0f) {
+        const float wf_count = isv[RL_REWARD_MAG_VAR_COUNT_INDEX];
+        if (wf_count > 1.0f) {
+            const float wf_m2   = isv[RL_REWARD_MAG_VAR_M2_INDEX];
+            const float wf_mean = isv[RL_REWARD_MAG_VAR_MEAN_INDEX];
+            const float wf_var  = wf_m2 / (wf_count - 1.0f);
+            const float cv      = (wf_mean > 1e-6f) ? sqrtf(wf_var) / wf_mean : 0.0f;
+            const float stability = expf(-cv * cv_gain);
+            trust *= stability;
+        }
+    }
+
+    const float a_slow_eff = a_slow_min + (a_fast - a_slow_min) * trust;
+
+    if (n_win > 0) {
+        const float step_avg = sum_win / (float)n_win;
+        const float prev     = isv[RL_AVG_WIN_USD_EMA_INDEX];
+        // avg_win: slow-up (skeptical of wins), fast-down (correct quickly)
+        const float alpha = (step_avg > prev) ? a_slow_eff : a_fast;
+        isv[RL_AVG_WIN_USD_EMA_INDEX] = (1.0f - alpha) * prev + alpha * step_avg;
+    }
+
+    if (n_loss > 0) {
+        const float step_avg = sum_loss / (float)n_loss;
+        const float prev     = isv[RL_AVG_LOSS_USD_EMA_INDEX];
+        // avg_loss: fast-up (admit losses, safety), slow-down (slow forget)
+        const float alpha = (step_avg > prev) ? a_fast : a_slow_eff;
+        isv[RL_AVG_LOSS_USD_EMA_INDEX] = (1.0f - alpha) * prev + alpha * step_avg;
+    }
+}

crates/ml-alpha/cuda/rl_band_frac_aggregate.cu

@@ -0,0 +1,86 @@
+// rl_band_frac_aggregate.cu — Phase 4-B per-step `frac_not_masked` reducer.
+//
+// Single-block tree-reduce over batch. Reads:
+//   * band_out [B × 2]      — (b_l, b_u) post-activation, lots units
+//   * pos_state [B × P]     — i32 position lots at offset 0
+//   * isv                    — read-only (gate slot)
+//
+// Computes the per-batch boolean `position ∈ [b_l, b_u]` and reduces
+// `(1 - in_band)` (= "this batch is FREE to trade this step") to a single
+// scalar `frac_not_masked ∈ [0, 1]`, written to
+// `RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX` (slot 812).
+//
+// Spec: docs/superpowers/specs/2026-06-03-no-transaction-band-architecture.md
+// §5.2 + §5.3 (fleet-fraction discipline per pearl_fleet_fraction_not_aggregate).
+//
+// Disciplines:
+//   * `feedback_no_atomicadd` — tree-reduce in shared memory, single-thread
+//     writes the final scalar to ISV.
+//   * `pearl_determinism_achieved` — deterministic shared-mem reduction with
+//     `__syncthreads()` barriers; no PRNG.
+//   * `feedback_no_nvrtc` — pre-compiled cubin via build.rs.
+//
+// Launch:
+//   grid = (1, 1, 1)
+//   block = (block_dim, 1, 1)  — power-of-two, ≥ b_size when possible
+//   shared_mem_bytes = block_dim × sizeof(float)
+//
+// The host caller picks `block_dim = next_power_of_two(b_size).min(1024)`
+// — matches `rl_q_pi_agree_b`'s launch shape so the reduction is fully
+// captured in a single warp-aligned tree-reduce.
+
+#include <stdint.h>
+
+#define BAND_OUT                              2
+#define RL_BAND_ENABLED_INDEX                 799
+#define RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX 812
+
+extern "C" __global__ void rl_band_frac_aggregate(
+    const float*         __restrict__ band_outputs,    // [B × 2]
+    const unsigned char* __restrict__ pos_state,       // [B × pos_bytes]
+    float*               __restrict__ isv,
+    int                                b_size,
+    int                                pos_bytes
+) {
+    extern __shared__ float s_partial[];   // [block_dim]
+
+    const int tid = threadIdx.x;
+    const int bdim = blockDim.x;
+
+    // Master gate: if band disabled, write sentinel 0.0 and return — the
+    // controller's master-gate guard will skip the EMA update.
+    const float enabled = isv[RL_BAND_ENABLED_INDEX];
+    if (enabled <= 0.5f) {
+        if (tid == 0) {
+            isv[RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX] = 0.0f;
+        }
+        return;
+    }
+
+    // Per-thread accumulation: walk over batch indices in strides of bdim.
+    float local = 0.0f;
+    for (int b = tid; b < b_size; b += bdim) {
+        const int position_lots =
+            *reinterpret_cast<const int*>(pos_state + b * pos_bytes);
+        const float pos_f = (float)position_lots;
+        const float b_l = band_outputs[b * BAND_OUT + 0];
+        const float b_u = band_outputs[b * BAND_OUT + 1];
+        const float in_band = (pos_f >= b_l && pos_f <= b_u) ? 1.0f : 0.0f;
+        local += (1.0f - in_band);
+    }
+    s_partial[tid] = local;
+    __syncthreads();
+
+    // Tree-reduce.
+    for (int stride = bdim / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_partial[tid] += s_partial[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float inv_b = 1.0f / (float)b_size;
+        isv[RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX] = s_partial[0] * inv_b;
+    }
+}

crates/ml-alpha/cuda/rl_band_head_backward.cu

@@ -0,0 +1,136 @@
+// rl_band_head_backward.cu — Phase 4-B band-head backward chain.
+//
+// Spec: docs/superpowers/specs/2026-06-03-no-transaction-band-architecture.md
+// §3.3 (backward chain into encoder).
+//
+// Forward chain (recap, see `rl_band_head_forward.cu`):
+//     band_pre[b, j] = b_band[j] + Σ_c W_band[j, c] · h_t[b, c]
+//     b_l = -|tanh(band_pre[b, 0])| × N_max_eff
+//     b_u = +|tanh(band_pre[b, 1])| × N_max_eff
+//
+// Backward chain (this file):
+//   Given dL/d(b_l) = grad_band[b, 0] and dL/d(b_u) = grad_band[b, 1] from
+//   the turnover-loss kernel:
+//
+//     dL/d(band_pre[b, 0]) = grad_band[b, 0] · d(b_l)/d(pre)
+//                          = grad_band[b, 0] · (-sign(t_l)) · (1 - t_l²) · N_max
+//                          = grad_band[b, 0] · (-sign(t_l)) · sech²(pre_l) · N_max
+//     dL/d(band_pre[b, 1]) = grad_band[b, 1] · d(b_u)/d(pre)
+//                          = grad_band[b, 1] · (+sign(t_u)) · sech²(pre_u) · N_max
+//
+//   Then the linear backward:
+//     dL/d(W_band[j, c]) per batch = dL/d(pre[b, j]) · h_t[b, c]
+//     dL/d(b_band[j])    per batch = dL/d(pre[b, j])
+//     dL/d(h_t[b, c])             = Σ_j dL/d(pre[b, j]) · W_band[j, c]
+//
+// Outputs (per-batch scratch; caller reduces via `reduce_axis0`):
+//   grad_w_per_batch [B × BAND_OUT × HIDDEN_DIM]
+//   grad_b_per_batch [B × BAND_OUT]
+//   grad_h_t         [B × HIDDEN_DIM] (OVERWRITE — caller folds into encoder
+//                                      grad via `grad_h_accumulate_scaled`)
+//
+// Disciplines:
+//   * `feedback_no_atomicadd`        — per-batch scratch + reduce_axis0
+//   * `feedback_no_nvrtc`            — pre-compiled cubin via build.rs
+//   * `pearl_determinism_achieved`   — sole-writer per (b, j, c); no PRNG
+//   * `pearl_no_host_branches_in_captured_graph` — only kernel args, no
+//     host scalars in control flow
+//
+// Launch:
+//   grid  = (B, 1, 1)
+//   block = (HIDDEN_DIM, 1, 1)
+//   shared_mem_bytes = BAND_OUT × sizeof(float)   (s_dpre[2] staging)
+//
+// Per-block: thread c writes its own grad_w[b, 0, c], grad_w[b, 1, c],
+// grad_h_t[b, c]. Thread 0 additionally writes grad_b[b, 0] and grad_b[b, 1].
+
+#include <stdint.h>
+#include <math.h>
+
+#define HIDDEN_DIM                          128
+#define BAND_OUT                            2
+#define RL_BAND_ENABLED_INDEX               799
+#define RL_HEAT_CAP_MAX_LOTS_INDEX          504
+
+extern "C" __global__ void rl_band_head_backward(
+    const float* __restrict__ w_band,             // [BAND_OUT × HIDDEN_DIM]
+    const float* __restrict__ band_pre,           // [B × BAND_OUT]
+    const float* __restrict__ h_t,                // [B × HIDDEN_DIM]
+    const float* __restrict__ grad_band,          // [B × BAND_OUT]
+    const float* __restrict__ isv,
+    int                       b_size,
+    float*       __restrict__ grad_w_per_batch,   // [B × BAND_OUT × HIDDEN_DIM]
+    float*       __restrict__ grad_b_per_batch,   // [B × BAND_OUT]
+    float*       __restrict__ grad_h_t            // [B × HIDDEN_DIM] (OVERWRITE)
+) {
+    const int b = blockIdx.x;
+    const int c = threadIdx.x;
+    if (b >= b_size || c >= HIDDEN_DIM) return;
+
+    __shared__ float s_dpre[BAND_OUT];
+
+    // Master gate: write zeros and return so the caller's reduce_axis0 +
+    // accumulate_grad_h chain produces no encoder-grad contribution. The
+    // host-side branch in the trainer ALSO short-circuits the launch when
+    // disabled — this device-side guard is defense-in-depth so the kernel
+    // is safe to launch unconditionally during graph capture.
+    const float enabled = isv[RL_BAND_ENABLED_INDEX];
+    if (enabled <= 0.5f) {
+        grad_w_per_batch[(b * BAND_OUT + 0) * HIDDEN_DIM + c] = 0.0f;
+        grad_w_per_batch[(b * BAND_OUT + 1) * HIDDEN_DIM + c] = 0.0f;
+        grad_h_t[b * HIDDEN_DIM + c] = 0.0f;
+        if (c == 0) {
+            grad_b_per_batch[b * BAND_OUT + 0] = 0.0f;
+            grad_b_per_batch[b * BAND_OUT + 1] = 0.0f;
+        }
+        return;
+    }
+
+    // ── Stage 1: thread 0 computes the two activation-derivative scalars ─
+    if (c == 0) {
+        const float n_max_eff = isv[RL_HEAT_CAP_MAX_LOTS_INDEX];
+
+        const float pre_l = band_pre[b * BAND_OUT + 0];
+        const float pre_u = band_pre[b * BAND_OUT + 1];
+        const float t_l = tanhf(pre_l);
+        const float t_u = tanhf(pre_u);
+        // sech²(x) = 1 − tanh²(x)
+        const float sech2_l = 1.0f - t_l * t_l;
+        const float sech2_u = 1.0f - t_u * t_u;
+        // d(b_l)/d(pre_l) = -sign(t_l) · sech²(pre_l) · N_max
+        // d(b_u)/d(pre_u) = +sign(t_u) · sech²(pre_u) · N_max
+        // sign(0) = 0 — at pre = 0 the gradient is zero (the activation
+        // is non-differentiable at the cusp |tanh| → 0). Treat as zero;
+        // upstream signs propagate cleanly.
+        const float sign_l = (t_l > 0.0f) ? 1.0f : ((t_l < 0.0f) ? -1.0f : 0.0f);
+        const float sign_u = (t_u > 0.0f) ? 1.0f : ((t_u < 0.0f) ? -1.0f : 0.0f);
+
+        const float g_b_l = grad_band[b * BAND_OUT + 0];
+        const float g_b_u = grad_band[b * BAND_OUT + 1];
+        // dL/d(pre_l) = g_b_l · (-sign_l · sech2_l · N_max)
+        // dL/d(pre_u) = g_b_u · (+sign_u · sech2_u · N_max)
+        s_dpre[0] = g_b_l * (-sign_l) * sech2_l * n_max_eff;
+        s_dpre[1] = g_b_u * (+sign_u) * sech2_u * n_max_eff;
+
+        // grad_b_band per batch is just dL/d(pre[b, j]).
+        grad_b_per_batch[b * BAND_OUT + 0] = s_dpre[0];
+        grad_b_per_batch[b * BAND_OUT + 1] = s_dpre[1];
+    }
+    __syncthreads();
+
+    const float dpre_l = s_dpre[0];
+    const float dpre_u = s_dpre[1];
+
+    // ── Stage 2: per-(b, c) writes ───────────────────────────────────
+    // grad_w_band[j, c] per batch = dpre[j] · h_t[b, c]
+    const float h_bc = h_t[b * HIDDEN_DIM + c];
+    grad_w_per_batch[(b * BAND_OUT + 0) * HIDDEN_DIM + c] = dpre_l * h_bc;
+    grad_w_per_batch[(b * BAND_OUT + 1) * HIDDEN_DIM + c] = dpre_u * h_bc;
+
+    // grad_h_t[b, c] = dpre_l · W_band[0, c] + dpre_u · W_band[1, c]
+    // OVERWRITE — caller's `grad_h_accumulate_scaled` folds into encoder
+    // grad via additive +=.
+    const float w_lc = w_band[0 * HIDDEN_DIM + c];
+    const float w_uc = w_band[1 * HIDDEN_DIM + c];
+    grad_h_t[b * HIDDEN_DIM + c] = dpre_l * w_lc + dpre_u * w_uc;
+}

crates/ml-alpha/cuda/rl_band_head_forward.cu

@@ -0,0 +1,96 @@
+// rl_band_head_forward.cu — Phase 4-A band-head forward.
+//
+// Two entry points:
+//   * `rl_band_head_linear_fwd` — small linear projection
+//         band_pre[b, j] = b_band[j] + Σ_c W_band[j, c] · h_t[b, c]
+//     for j ∈ {0 (b_l), 1 (b_u)}. Grid = (B, 2, 1), Block = (HIDDEN_DIM, 1, 1)
+//     (matches the `ppo_policy_logits_fwd` launch shape for parity with
+//     `PolicyHead::forward_logits`).
+//   * `rl_band_apply_activation` — asymmetric ±|tanh| activation that
+//     enforces `b_l ≤ 0 ≤ b_u` by construction:
+//         b_l = -|tanh(band_pre[b, 0])| × N_max_eff
+//         b_u = +|tanh(band_pre[b, 1])| × N_max_eff
+//     where `N_max_eff` is read from `RL_HEAT_CAP_MAX_LOTS_INDEX`. Grid =
+//     (ceil(B/32), 1, 1), Block = (32, 1, 1); single-thread-per-batch
+//     element, deterministic.
+//
+// No PRNG, no atomicAdd, no shared mem. Pure read-deterministic;
+// graph-capturable. The forward is independent of the master gate at slot
+// 799 — the trainer skips the launch when the band is disabled.
+//
+// Per `pearl_determinism_achieved` discipline; per spec §1.1 / §1.3.
+
+#include <stdint.h>
+#include <math.h>
+
+#define HIDDEN_DIM                        128
+#define BAND_OUT                          2
+#define RL_HEAT_CAP_MAX_LOTS_INDEX       504
+
+// ── Linear forward: band_pre[b, j] = b_band[j] + Σ_c W_band[j, c] · h_t[b, c]
+//
+// Block-reduce over HIDDEN_DIM threads via shared memory. Matches the
+// existing `ppo_policy_logits_fwd` reduction pattern; deterministic
+// tree-reduce (no atomics) so output is bit-equal across runs.
+extern "C" __global__ void rl_band_head_linear_fwd(
+    const float* __restrict__ w_band,    // [BAND_OUT × HIDDEN_DIM]
+    const float* __restrict__ b_band,    // [BAND_OUT]
+    const float* __restrict__ h_t,       // [B × HIDDEN_DIM]
+    int                       b_size,
+    float* __restrict__       band_pre   // [B × BAND_OUT]
+) {
+    const int b = blockIdx.x;
+    const int j = blockIdx.y;
+    if (b >= b_size || j >= BAND_OUT) return;
+
+    const int tid = threadIdx.x;
+
+    __shared__ float partial[HIDDEN_DIM];
+    const float* w_row = w_band + j * HIDDEN_DIM;
+    const float* h_row = h_t + b * HIDDEN_DIM;
+
+    partial[tid] = w_row[tid] * h_row[tid];
+    __syncthreads();
+
+    // Tree-reduce over HIDDEN_DIM (assumed power-of-two = 128).
+    for (int stride = HIDDEN_DIM / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            partial[tid] += partial[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        band_pre[b * BAND_OUT + j] = partial[0] + b_band[j];
+    }
+}
+
+// ── Asymmetric ±|tanh| activation, scaled by N_max_eff.
+//
+// Output layout (per spec §1.1):
+//   band_out[b, 0] = -|tanh(band_pre[b, 0])| × N_max_eff    (≤ 0)
+//   band_out[b, 1] = +|tanh(band_pre[b, 1])| × N_max_eff    (≥ 0)
+//
+// Guarantees `b_l ≤ 0 ≤ b_u` for every batch element by construction —
+// Davis-Norman optimality theorem requires position 0 (flat) to lie inside
+// the no-transaction region; this activation enforces it.
+extern "C" __global__ void rl_band_apply_activation(
+    const float* __restrict__ band_pre,  // [B × BAND_OUT]
+    const float* __restrict__ isv,
+    int                       b_size,
+    float* __restrict__       band_out   // [B × BAND_OUT]
+) {
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
+    if (b >= b_size) return;
+
+    const float n_max_eff = isv[RL_HEAT_CAP_MAX_LOTS_INDEX];
+
+    const float pre_l = band_pre[b * BAND_OUT + 0];
+    const float pre_u = band_pre[b * BAND_OUT + 1];
+
+    const float t_l = tanhf(pre_l);
+    const float t_u = tanhf(pre_u);
+
+    band_out[b * BAND_OUT + 0] = -fabsf(t_l) * n_max_eff;
+    band_out[b * BAND_OUT + 1] = +fabsf(t_u) * n_max_eff;
+}

crates/ml-alpha/cuda/rl_band_mask.cu

@@ -0,0 +1,91 @@
+// rl_band_mask.cu — Phase 4-A no-transaction-band action override.
+//
+// When the current position lies inside the learned band `[b_l, b_u]`,
+// force `actions[b] = Hold` regardless of the sampled / argmax action.
+// This is the architectural default of the Davis-Norman (1990) no-trade
+// region (extended to deep RL by Imaki-Imajo-Ito 2021, arXiv:2103.01775).
+//
+// Layout matches `rl_confidence_gate.cu`:
+//   * Grid=(B, 1, 1), Block=(1, 1, 1).
+//   * One block per batch, single thread — pos_state read + 2-float band
+//     read + scalar compare; no reduction.
+//   * Master gate at `RL_BAND_ENABLED_INDEX` (slot 799). When ≤ 0.5f the
+//     kernel returns immediately, preserving Phase 3D bit-equality.
+//   * No atomicAdd; no shared mem; no PRNG; pure device-side, fully
+//     graph-capturable BUT launched OUTSIDE graph capture per spec §9.5
+//     so the host can branch on the master gate value without runtime
+//     graph rebuild.
+//
+// Per `feedback_no_atomicadd`, `feedback_cpu_is_read_only`,
+// `pearl_fleet_fraction_not_aggregate`.
+
+#include <stdint.h>
+
+#define ACTION_HOLD                       2
+#define RL_BAND_ENABLED_INDEX             799
+#define RL_BAND_MAX_MASK_FRAC_INDEX       813
+
+extern "C" __global__ void rl_band_mask(
+    int*                 __restrict__ actions,        // [B]    IN/OUT
+    const float*         __restrict__ band_outputs,   // [B × 2] (b_l, b_u)
+    const unsigned char* __restrict__ pos_state,      // [B × pos_bytes]
+    const float*         __restrict__ isv,
+    int                                b_size,
+    int                                pos_bytes
+) {
+    const int b = blockIdx.x;
+    if (b >= b_size) return;
+
+    // Master gate — bootstrap default is OFF (slot 799 = 0.0). When the
+    // operator flips it to 1.0 the band defaults engage.
+    const float enabled = isv[RL_BAND_ENABLED_INDEX];
+    if (enabled <= 0.5f) return;
+
+    // Phase 4-A2 exploration bypass — guarantee at least
+    // `(1 − max_mask) · B` batches are NEVER masked, so positions vary
+    // and the sigmoid surrogate gradient on (b_l, b_u) can flow into the
+    // band head. Without this the band collapses to the dead-signal trap
+    // observed at 552d91bf4 (Phase 4-B smoke): all positions stuck at 0,
+    // deep-in-band sigmoid argument, ~zero gradient, band stays wide.
+    //
+    // Bypass is DETERMINISTIC (lowest-index batches bypass) — random
+    // sampling would break `pearl_determinism_achieved` bit-equality.
+    // Spec §2.2 (kernel) + §9.1 Mitigation 2 (justification).
+    const float max_mask = isv[RL_BAND_MAX_MASK_FRAC_INDEX];
+    const int min_explore = (int)((float)b_size * (1.0f - max_mask));
+    if (b < min_explore) return;
+
+    // Position layout: pos_state[b * pos_bytes + 0..4] = position_lots:i32
+    // (canonical foxhunt offset; see PosFlat at
+    // crates/ml-backtesting/src/lob/mod.rs and the rl_confidence_gate
+    // reader at line 72).
+    const int position_lots =
+        *reinterpret_cast<const int*>(pos_state + b * pos_bytes);
+
+    // Phase 4-A3 (2026-06-04): Davis-Norman position-zero exception.
+    // The Davis-Norman (1990) no-transaction band is a theorem about
+    // MANAGING an EXISTING hedge position — it tells the agent NOT to
+    // micro-adjust within the band. It says nothing about whether to
+    // open a position from flat.
+    //
+    // The `±|tanh|` activation in `rl_band_head_forward.cu` guarantees
+    // `b_l ≤ 0 ≤ b_u` (the Davis-Norman invariant). Combined with the
+    // foxhunt invariant that agents start FLAT (position = 0), every
+    // single flat-batch would be masked to Hold — agents never open,
+    // positions never move, the sigmoid surrogate on (b_l, b_u) sits
+    // deep-in-band where its derivative ≈ 0, and the band loss has no
+    // gradient signal. Verified empirically at 1c23ff368 (Phase 4-A2):
+    // action_hist collapsed to bimodal [0,0,109,0,0,0,0,0,19,0,0] from
+    // step 100 onward, total_trades = 8 over 2000 steps.
+    //
+    // Flat positions get free choice — opens are NOT band-constrained.
+    if (position_lots == 0) return;
+
+    const float b_l = band_outputs[b * 2 + 0];
+    const float b_u = band_outputs[b * 2 + 1];
+
+    const float pos_f = (float)position_lots;
+    if (pos_f >= b_l && pos_f <= b_u) {
+        actions[b] = ACTION_HOLD;
+    }
+}

crates/ml-alpha/cuda/rl_band_turnover_controller.cu

@@ -0,0 +1,108 @@
+// rl_band_turnover_controller.cu — Phase 4-B adaptive turnover-target
+// controller.
+//
+// Spec: docs/superpowers/specs/2026-06-03-no-transaction-band-architecture.md
+// §3.1 Option (c) + §3.4 (Schulman-bounded adaptive controller).
+//
+// Reads (from ISV):
+//   * RL_BAND_ENABLED_INDEX                   (799) — master gate
+//   * RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX  (812) — per-step raw signal
+//                                                    written by
+//                                                    `rl_band_frac_aggregate.cu`
+//   * RL_BAND_TURNOVER_EMA_INDEX              (809) — EMA state (owned)
+//   * RL_BAND_CONTROLLER_BOOT_DONE_INDEX      (810) — bootstrap latch (owned)
+//   * RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX  (811) — output (owned)
+//
+// Writes (to ISV):
+//   * 809 — updated EMA (first-observation bootstrap or Wiener-α blend)
+//   * 810 — latched 1.0 on first observation
+//   * 811 — adaptive target, clamped to [TARGET_MIN, TARGET_MAX]
+//
+// Control law (per the Phase 4-B dispatch & spec §3.1 Option c):
+//   Healthy frac_not_masked target ≈ 0.4 (40% of batches free to trade,
+//   60% inside band). Asymmetric Schulman-bounded adapter:
+//
+//     if frac_not_masked_ema > OVER_THRESHOLD   (too much trading):
+//         target *= TIGHTEN_RATE   (push narrower band → fewer trades)
+//     elif frac_not_masked_ema < UNDER_THRESHOLD (band saturated):
+//         target *= LOOSEN_RATE    (push wider band → more trading)
+//     else:
+//         healthy band — leave alone.
+//     clamp(target, TARGET_MIN, TARGET_MAX).
+//
+// Per `pearl_bootstrap_must_respect_clamp_range`: bootstrap 0.05 ∈
+// [TARGET_MIN=0.01, TARGET_MAX=0.20]; controller never snaps to a clamp
+// boundary on its first emission.
+//
+// Per `pearl_dead_signal_resurrection_discipline`: the band's output gates
+// its own input (mask → fewer trades → narrower band drift → mask). The
+// asymmetric LOOSEN escape rate is faster than the TIGHTEN rate so the
+// controller can recover when frac_not_masked drops below 0.2.
+//
+// Per `feedback_no_atomicadd`: single-thread launch (1×1×1), no atomics.
+// Per `feedback_no_nvrtc`: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+#include <math.h>
+
+#define RL_BAND_ENABLED_INDEX                    799
+#define RL_BAND_TURNOVER_EMA_INDEX               809
+#define RL_BAND_CONTROLLER_BOOT_DONE_INDEX       810
+#define RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX   811
+#define RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX   812
+
+// Tuning constants (all dimensionless).
+#define BAND_CTRL_EMA_ALPHA        0.02f   // Wiener-α — ~50-step horizon
+#define BAND_CTRL_OVER_THRESHOLD   0.60f   // frac_not_masked above → too much trading
+#define BAND_CTRL_UNDER_THRESHOLD  0.20f   // frac_not_masked below → band saturated
+#define BAND_CTRL_TIGHTEN_RATE     0.97f   // −3 %/step (slow narrow)
+#define BAND_CTRL_LOOSEN_RATE      1.05f   // +5 %/step (faster escape per resurrection discipline)
+#define BAND_CTRL_TARGET_MIN       0.01f   // never below 1 % of batches trading
+#define BAND_CTRL_TARGET_MAX       0.20f   // never above 20 % — keeps band materially active
+
+extern "C" __global__ void rl_band_turnover_controller(float* isv) {
+    // Single-thread kernel — launched (1,1,1)/(1,1,1).
+    if (threadIdx.x != 0 || blockIdx.x != 0) return;
+
+    // Master gate: when the band is disabled, leave all owned slots
+    // untouched so Phase 3D bit-equality is preserved.
+    const float enabled = isv[RL_BAND_ENABLED_INDEX];
+    if (enabled <= 0.5f) return;
+
+    const float frac_now  = isv[RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX];
+    const float boot_done = isv[RL_BAND_CONTROLLER_BOOT_DONE_INDEX];
+
+    // ── EMA update (first-observation bootstrap pattern) ─────────────
+    float ema;
+    if (boot_done < 0.5f) {
+        // Replace EMA with current observation; latch flag. Necessary
+        // because slot 809 sentinel-zeroes at trainer init and blending
+        // zero with the first real measurement (likely ≈ 0.5 at warm
+        // band-start) would lag the controller by ~50 steps before it
+        // sees a representative value.
+        ema = frac_now;
+        isv[RL_BAND_CONTROLLER_BOOT_DONE_INDEX] = 1.0f;
+    } else {
+        ema = (1.0f - BAND_CTRL_EMA_ALPHA) * isv[RL_BAND_TURNOVER_EMA_INDEX]
+            + BAND_CTRL_EMA_ALPHA * frac_now;
+    }
+    isv[RL_BAND_TURNOVER_EMA_INDEX] = ema;
+
+    // ── Target update — asymmetric Schulman-bounded adapter ──────────
+    float target = isv[RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX];
+    if (ema > BAND_CTRL_OVER_THRESHOLD) {
+        // Trading too much → tighten band (smaller target → smaller
+        // frac_not_masked goal → narrower bands chase the goal).
+        target *= BAND_CTRL_TIGHTEN_RATE;
+    } else if (ema < BAND_CTRL_UNDER_THRESHOLD) {
+        // Band saturated → loosen (escape with faster rate per
+        // resurrection discipline).
+        target *= BAND_CTRL_LOOSEN_RATE;
+    }
+    // Healthy band — leave target alone.
+
+    // Clamp; bootstrap 0.05 sits strictly inside [0.01, 0.20].
+    target = fmaxf(BAND_CTRL_TARGET_MIN,
+                   fminf(target, BAND_CTRL_TARGET_MAX));
+    isv[RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX] = target;
+}

crates/ml-alpha/cuda/rl_band_turnover_loss.cu

@@ -0,0 +1,144 @@
+// rl_band_turnover_loss.cu — Phase 4-A turnover regularizer (Option b).
+//
+// Per spec §3.1 Option (b) + §3.2:
+//   * Soft turnover proxy per batch:
+//         m_soft[b] = sigmoid(s · (pos − b_l)) · sigmoid(s · (b_u − pos))
+//     where `s` is `RL_BAND_GRAD_SHARPNESS_INDEX` (slot 804). `m_soft[b]`
+//     ≈ 1.0 when position is in band (would-be-Hold), ≈ 0.0 outside.
+//     `not_masked[b] = 1 − m_soft[b]` is the differentiable surrogate for
+//     "this batch was free to trade this step".
+//   * Mean across batch: `turnover_t = mean_b (1 − m_soft[b])`.
+//   * Loss: `L = λ · (turnover_t − target)²` (same scalar for every batch
+//     element; gradient is per-batch via the chain rule below).
+//
+// In Phase 4-A this kernel emits the per-batch loss scalar and the per-
+// batch gradient on `(b_l, b_u)` for future wiring. The trainer integration
+// (step 4) launches the kernel for OBSERVABILITY only — the gradient is
+// written to a scratch buffer that is not yet folded into the encoder grad
+// path. Adaptive controller + full backward chain are Phase 4-B / 4-C.
+//
+// Gradient derivation (per spec §3.2):
+//   diff           = turnover − target
+//   d(turnover)/db_l = +(1/B) · σ' · s    (looser lower bound → fewer in band → higher turnover)
+//   d(turnover)/db_u = −(1/B) · σ' · s    (looser upper bound → more in band → lower turnover)
+// where σ' is sigmoid derivative evaluated at the boundary surrogate.
+//
+// `RL_BAND_LOSS_WEIGHT_INDEX` (802) multiplies the loss. `RL_BAND_ENABLED_INDEX`
+// (799) gates the entire write — when ≤ 0.5 the kernel writes zeros so the
+// per-batch loss reducer sees no contribution.
+//
+// Phase 4-B (2026-06-04): the turnover target is now read from the
+// adaptive controller's output at `RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX`
+// (811) instead of the static slot 803. The controller updates 811 every
+// step based on the EMA of `frac_not_masked`. Slot 803 remains in the ISV
+// (Phase 4-A clamp anchor for the controller) but is no longer the loss
+// kernel's input. See spec §3.1 Option (c) and `rl_band_turnover_controller.cu`.
+//
+// Per `feedback_no_atomicadd` (single-writer per slot), `pearl_determinism_achieved`
+// (no PRNG, single-thread-per-batch, no shared reductions across blocks).
+
+#include <stdint.h>
+#include <math.h>
+
+#define BAND_OUT                                  2
+#define RL_BAND_ENABLED_INDEX                     799
+#define RL_BAND_LOSS_WEIGHT_INDEX                 802
+#define RL_BAND_GRAD_SHARPNESS_INDEX              804
+#define RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX    811
+
+// Numerically-stable sigmoid (clamps argument to avoid expf overflow).
+static __device__ __forceinline__ float stable_sigmoid(float x) {
+    if (x >= 0.0f) {
+        const float e = expf(-fminf(x, 40.0f));
+        return 1.0f / (1.0f + e);
+    } else {
+        const float e = expf(fmaxf(x, -40.0f));
+        return e / (1.0f + e);
+    }
+}
+
+// Per-batch soft-mask + per-batch loss/grad scratch.
+//
+// Inputs:
+//   band_outputs [B × 2] — (b_l, b_u) post-activation, in lots units.
+//   pos_state    [B × pos_bytes] — i32 position lots at offset 0.
+//   isv          [..]    — read-only ISV slots.
+//   turnover_t   scalar  — current per-step soft turnover (mean across B
+//                          of (1 - m_soft)), pre-computed by a separate
+//                          reduce kernel OR passed as 0 for Phase 4-A
+//                          OBSERVABILITY-ONLY (gradient still meaningful
+//                          via diff signal).
+//
+// Outputs:
+//   m_soft_per_b [B]     — sigmoid surrogate "in band" mass ∈ [0, 1].
+//   loss_per_b   [B]     — per-batch loss contribution (same scalar).
+//   grad_band_per_b [B × 2] — per-batch grad on (b_l, b_u).
+//
+// Grid = (ceil(B/32), 1, 1), Block = (32, 1, 1).
+extern "C" __global__ void rl_band_turnover_loss(
+    const float*         __restrict__ band_outputs,    // [B × 2]
+    const unsigned char* __restrict__ pos_state,       // [B × pos_bytes]
+    const float*         __restrict__ isv,
+    float                              turnover_t,     // host-supplied scalar
+    int                                b_size,
+    int                                pos_bytes,
+    float*               __restrict__ m_soft_per_b,    // [B]
+    float*               __restrict__ loss_per_b,      // [B]
+    float*               __restrict__ grad_band_per_b  // [B × 2]
+) {
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
+    if (b >= b_size) return;
+
+    const float enabled = isv[RL_BAND_ENABLED_INDEX];
+    if (enabled <= 0.5f) {
+        m_soft_per_b[b] = 0.0f;
+        loss_per_b[b] = 0.0f;
+        grad_band_per_b[b * BAND_OUT + 0] = 0.0f;
+        grad_band_per_b[b * BAND_OUT + 1] = 0.0f;
+        return;
+    }
+
+    const int position_lots =
+        *reinterpret_cast<const int*>(pos_state + b * pos_bytes);
+    const float pos_f = (float)position_lots;
+
+    const float b_l = band_outputs[b * BAND_OUT + 0];
+    const float b_u = band_outputs[b * BAND_OUT + 1];
+
+    const float sharpness = isv[RL_BAND_GRAD_SHARPNESS_INDEX];
+    // Phase 4-B: read the adaptive controller's target instead of the
+    // static slot 803. The controller's bootstrap matches the static
+    // default so first-step behavior is identical to Phase 4-A.
+    const float target    = isv[RL_BAND_TURNOVER_TARGET_ADAPTIVE_INDEX];
+    const float loss_w    = isv[RL_BAND_LOSS_WEIGHT_INDEX];
+
+    // Sigmoid surrogate near each boundary. `m_lower` ≈ 1 when pos ≥ b_l;
+    // `m_upper` ≈ 1 when pos ≤ b_u; their product is the soft "in band".
+    const float arg_l = sharpness * (pos_f - b_l);
+    const float arg_u = sharpness * (b_u - pos_f);
+    const float s_l = stable_sigmoid(arg_l);   // ∂m/∂b_l requires −σ_l(1−σ_l)·s
+    const float s_u = stable_sigmoid(arg_u);   // ∂m/∂b_u requires +σ_u(1−σ_u)·s
+    const float m_soft = s_l * s_u;
+    m_soft_per_b[b] = m_soft;
+
+    // Loss: L = (λ × (turnover − target)²) / B, distributed evenly across
+    // batches for reduction purposes. Same value per batch element.
+    const float diff = turnover_t - target;
+    const float inv_b = 1.0f / (float)b_size;
+    loss_per_b[b] = loss_w * diff * diff * inv_b;
+
+    // d(turnover)/d(b_l) = -(1/B) · d(m_soft)/d(b_l)
+    //                    = -(1/B) · s_u · d(s_l)/d(b_l)
+    //                    = -(1/B) · s_u · (-sharpness · s_l · (1 − s_l))
+    //                    = +(1/B) · sharpness · s_l · (1 − s_l) · s_u
+    // d(turnover)/d(b_u) similarly with sign flipped.
+    const float ds_l_db_l = -sharpness * s_l * (1.0f - s_l);
+    const float ds_u_db_u = +sharpness * s_u * (1.0f - s_u);
+
+    // dL/db_l = 2 · λ · diff · d(turnover)/db_l = -2λ·diff·s_u·ds_l_db_l/B
+    // dL/db_u = -2λ·diff·s_l·ds_u_db_u/B
+    grad_band_per_b[b * BAND_OUT + 0] =
+        -2.0f * loss_w * diff * s_u * ds_l_db_l * inv_b;
+    grad_band_per_b[b * BAND_OUT + 1] =
+        -2.0f * loss_w * diff * s_l * ds_u_db_u * inv_b;
+}

crates/ml-alpha/cuda/rl_bellman_target_saturation_reduce.cu

@@ -0,0 +1,84 @@
+// rl_bellman_target_saturation_reduce.cu — B-9 cross-batch tree-reduce of
+// per-batch saturation tallies produced by `bellman_target_projection` and
+// `bellman_fused_select_project`. Writes per-step rates + extremes to ISV.
+//
+// Inputs (consumed AFTER one of the two bellman variants has run):
+//   sat_top_per_batch  [B]  — per-block count of (atom_z) where t_z > V_MAX_eff
+//   sat_bot_per_batch  [B]  — per-block count of (atom_z) where t_z < V_MIN_eff
+//   max_pre_per_batch  [B]  — per-block max(t_z)  pre-clamp
+//   min_pre_per_batch  [B]  — per-block min(t_z)  pre-clamp
+//
+// Outputs (single ISV write each, by thread 0):
+//   ISV[RL_Q_TARGET_TOP_SATURATION_RATE_INDEX = 726]  Σ(top) / (B × Q_N_ATOMS)
+//   ISV[RL_Q_TARGET_BOT_SATURATION_RATE_INDEX = 727]  Σ(bot) / (B × Q_N_ATOMS)
+//   ISV[RL_Q_TARGET_MAX_PRE_PROJ_INDEX        = 728]  max over batches
+//   ISV[RL_Q_TARGET_MIN_PRE_PROJ_INDEX        = 729]  min over batches
+//
+// Per `feedback_no_atomicadd.md`: single-block kernel, shared-mem
+// tree-reduce. Caller launches with grid_dim=(1,1,1), block_dim=(N,1,1)
+// where N is a power of 2 with N <= max(1, B/2) and N <= 256, and
+// shared bytes = 4 * N * sizeof(float).
+//
+// Block size rationale: each thread iterates B/N elements via grid-stride;
+// the tree-reduce after the strided gather is over N threads.
+
+#include <cuda_runtime.h>
+
+#define RL_Q_TARGET_TOP_SATURATION_RATE_INDEX  726
+#define RL_Q_TARGET_BOT_SATURATION_RATE_INDEX  727
+#define RL_Q_TARGET_MAX_PRE_PROJ_INDEX         728
+#define RL_Q_TARGET_MIN_PRE_PROJ_INDEX         729
+
+#define Q_N_ATOMS                              21
+
+extern "C" __global__ void rl_bellman_target_saturation_reduce(
+    float*       __restrict__ isv,
+    const float* __restrict__ sat_top_per_batch,
+    const float* __restrict__ sat_bot_per_batch,
+    const float* __restrict__ max_pre_per_batch,
+    const float* __restrict__ min_pre_per_batch,
+    int                       B
+) {
+    extern __shared__ float smem[];
+    float* s_top = smem;
+    float* s_bot = smem +     blockDim.x;
+    float* s_max = smem + 2 * blockDim.x;
+    float* s_min = smem + 3 * blockDim.x;
+    const int tid = threadIdx.x;
+
+    // Grid-stride gather. Padded identity values for max/min reductions
+    // (+/- infinity) ensure threads with no work don't pollute the
+    // result.
+    float l_top = 0.0f, l_bot = 0.0f;
+    float l_max = -INFINITY, l_min = INFINITY;
+    for (int b = tid; b < B; b += blockDim.x) {
+        l_top += sat_top_per_batch[b];
+        l_bot += sat_bot_per_batch[b];
+        l_max  = fmaxf(l_max, max_pre_per_batch[b]);
+        l_min  = fminf(l_min, min_pre_per_batch[b]);
+    }
+    s_top[tid] = l_top;
+    s_bot[tid] = l_bot;
+    s_max[tid] = l_max;
+    s_min[tid] = l_min;
+    __syncthreads();
+
+    // Power-of-2 tree reduce — blockDim.x guaranteed power of 2 by caller.
+    for (int stride = blockDim.x / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_top[tid] += s_top[tid + stride];
+            s_bot[tid] += s_bot[tid + stride];
+            s_max[tid]  = fmaxf(s_max[tid], s_max[tid + stride]);
+            s_min[tid]  = fminf(s_min[tid], s_min[tid + stride]);
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float denom = (float)(B * Q_N_ATOMS);
+        isv[RL_Q_TARGET_TOP_SATURATION_RATE_INDEX] = s_top[0] / denom;
+        isv[RL_Q_TARGET_BOT_SATURATION_RATE_INDEX] = s_bot[0] / denom;
+        isv[RL_Q_TARGET_MAX_PRE_PROJ_INDEX]        = s_max[0];
+        isv[RL_Q_TARGET_MIN_PRE_PROJ_INDEX]        = s_min[0];
+    }
+}

crates/ml-alpha/cuda/rl_cmdp_constraints_check.cu

@@ -0,0 +1,295 @@
+// rl_cmdp_constraints_check.cu — Layer 1 hard CMDP gates.
+//
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Maintains the session-level + cooldown state that downstream consumers
+// (actions_to_market_targets) read as override flags. Three independent
+// risk constraints are tracked here:
+//
+//   1. Session pnl accumulation + DD limit (sticky `triggered` flag)
+//   2. Cooldown counter decrement (after consecutive losses limit fires)
+//   3. Consecutive-loss tracking (sets cooldown when limit hit)
+//
+// Max-open-units + net-inventory checks are evaluated PER BATCH inside
+// actions_to_market_targets where per-batch unit state is available.
+// This kernel handles only session-wide state.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block, sums sequentially.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_no_partial_refactor`: ISV slots must match isv_slots.rs.
+//
+// Launch config:
+//   grid  = (1, 1, 1)
+//   block = (1, 1, 1)
+//   smem  = 0
+//   stream = main RL stream (sequenced AFTER rl_fused_reward_pipeline
+//            writes realized_pnl / outcomes, BEFORE actions_to_market_targets
+//            reads override flags).
+
+#include <stdint.h>
+
+#define RL_SESSION_PNL_USD_INDEX            662
+#define RL_SESSION_DD_LIMIT_USD_INDEX       663
+#define RL_SESSION_DD_TRIGGERED_INDEX       664
+#define RL_CONSEC_LOSS_LIMIT_INDEX          666
+#define RL_CONSEC_LOSS_COUNT_INDEX          667
+#define RL_COOLDOWN_REMAINING_STEPS_INDEX   668
+#define RL_COOLDOWN_DURATION_INDEX          669
+#define RL_SESSION_PNL_WORST_INDEX          684
+
+// Fleet-fraction observability (2026-06-01). Existing aggregates above
+// emit the SINGLE WORST batch state, which at b=1024 stays pegged at
+// the limit even when most batches are healthy. These fractions emit
+// what proportion of the fleet is currently constrained, distinguishing
+// "normal per-batch risk-management" from "fleet-wide absorbing trap".
+#define RL_CMDP_FRAC_IN_COOLDOWN_INDEX        743
+#define RL_CMDP_FRAC_CONSEC_NEAR_LIMIT_INDEX  744
+#define RL_CMDP_FRAC_DD_TRIGGERED_INDEX       745
+#define RL_CMDP_FRAC_SESSION_NEG_INDEX        746
+
+// Edge-decay detector Phase 1 (2026-06-01). Page-Hinkley change-point
+// detector on σ_welford-normalized per-trade PnL stream. Diagnostic-only
+// (no behavior change). See spec
+// docs/superpowers/specs/2026-06-01-edge-decay-detector-phase1-diagnostic.md.
+//
+// Kernel ordering: rl_cmdp_constraints_check fires BEFORE apply_reward_scale
+// and rl_popart_normalize in step_with_lobsim_gpu_body. So rewards[b] at
+// kernel entry is RAW per-step PnL (USD), NOT popart-scaled. The σ slot
+// read is the PRIOR step's σ_welford (one-step lag). Slot 725 is the
+// pre-envelope-floor Welford σ — chosen over slot 555 (σ_effective)
+// because slot 555 spikes 1000× at the eval shock window, blinding the
+// detector.
+#define RL_POPART_SIGMA_WELFORD_INDEX         725
+#define RL_EDGE_PH_TOLERANCE_INDEX            747
+#define RL_EDGE_PH_THRESHOLD_INDEX            748
+#define RL_EDGE_PH_WARMUP_MIN_INDEX           749
+#define RL_EDGE_PH_MEAN_INDEX                 750
+#define RL_EDGE_PH_FRAC_ALERTED_INDEX         751
+#define RL_EDGE_PH_FRAC_WARMUP_INDEX          752
+
+// Per-batch session-pnl + consec-loss tracking. Each batch element is an
+// independent backtest "session" with its own $35k starting capital;
+// `session_pnl_per_batch[b]` is the running PnL of that session and
+// `consec_loss_per_batch[b]` is its losing-trade streak. The kernel
+// writes per-batch state out for `actions_to_market_targets` to read
+// (per-batch DD-triggered / cooldown gating) and also writes the
+// canonical summary slots so diag + IQN-τ keep a single-account view.
+extern "C" __global__ void rl_cmdp_constraints_check(
+    float*       __restrict__ isv,
+    const float* __restrict__ rewards,                       // [b_size] RAW per-step pnl (USD)
+    const float* __restrict__ dones,                         // [b_size] 1.0 = close
+    float*       __restrict__ session_pnl_per_batch,         // [b_size] IN/OUT
+    float*       __restrict__ consec_loss_per_batch,         // [b_size] IN/OUT
+    float*       __restrict__ session_dd_triggered_per_batch,// [b_size] IN/OUT (0/1)
+    float*       __restrict__ cooldown_remaining_per_batch,  // [b_size] IN/OUT
+    // Edge-decay Phase 1: Page-Hinkley per-batch state (5 buffers).
+    // Zero-init at construction AND on every fold/eval boundary via
+    // reset_session_state (predictive-reset discipline).
+    float*       __restrict__ ph_mu_per_batch,               // [b_size] IN/OUT — pre-update Welford mean (σ-normalized y)
+    float*       __restrict__ ph_count_per_batch,            // [b_size] IN/OUT — trades observed (f32)
+    float*       __restrict__ ph_m_per_batch,                // [b_size] IN/OUT — Σ(y_i − μ̄_pre − δ) post-warmup
+    float*       __restrict__ ph_mmin_per_batch,                // [b_size] IN/OUT — min(ph_m_b) so far post-warmup
+    float*       __restrict__ ph_stat_per_batch,             // [b_size] IN/OUT — current ph_m − ph_M (the PH statistic)
+    int                       b_size
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    const float dd_limit    = isv[RL_SESSION_DD_LIMIT_USD_INDEX];
+    const float consec_lim  = isv[RL_CONSEC_LOSS_LIMIT_INDEX];
+    const float cool_dur    = isv[RL_COOLDOWN_DURATION_INDEX];
+
+    // Edge-decay Phase 1: read PH config + σ_welford for normalization.
+    // pop_sigma is clamped to 1e-6 to avoid div-by-zero in early bootstrap
+    // (before any reward has been observed, σ_welford may still be 0).
+    const float ph_delta      = isv[RL_EDGE_PH_TOLERANCE_INDEX];
+    const float ph_lambda     = isv[RL_EDGE_PH_THRESHOLD_INDEX];
+    const float ph_warmup_min = isv[RL_EDGE_PH_WARMUP_MIN_INDEX];
+    const float pop_sigma     = fmaxf(isv[RL_POPART_SIGMA_WELFORD_INDEX], 1e-6f);
+
+    // Summary aggregates (single-account view, written at end of loop).
+    //
+    // Fix B: IQN-τ reads `RL_SESSION_PNL_USD_INDEX`, so we expose the
+    // MEAN-of-active-accounts there instead of the worst — one bad
+    // account no longer drags the fleet's risk aversion to its floor.
+    // The worst per-batch pnl mirrors to `RL_SESSION_PNL_WORST_INDEX`
+    // for diag (helps spot fleet skew).
+    float worst_pnl        = 0.0f;
+    float worst_consec     = 0.0f;
+    float any_dd_trig      = 0.0f;
+    float max_cool_remain  = 0.0f;
+    float active_pnl_sum   = 0.0f;
+    int   n_active         = 0;
+
+    // Fleet-fraction observability counters (2026-06-01). See header
+    // block above for the falsification criteria these support.
+    int   n_in_cooldown     = 0;  // batches with cooldown_remaining > 0
+    int   n_consec_near_lim = 0;  // batches with consec >= limit - 1
+    int   n_dd_triggered    = 0;  // batches with dd_triggered flag set
+    int   n_session_neg     = 0;  // batches with session_pnl < 0
+
+    // Edge-decay Phase 1 fleet-fraction counters.
+    float ph_active_sum     = 0.0f;
+    int   n_ph_active       = 0;
+    int   n_ph_alerted      = 0;
+    int   n_ph_warmup       = 0;
+
+    for (int b = 0; b < b_size; ++b) {
+        // Snapshot cooldown state BEFORE Section 1, so Section 2's
+        // decrement only consumes what was already in flight from a
+        // prior step. Without this, a fresh cooldown set in Section 1
+        // would be immediately decremented in Section 2 same-step
+        // (off-by-one — G1 caught this with cool=499 vs expected 500).
+        const float cool_prev = cooldown_remaining_per_batch[b];
+
+        // ── 1. Per-batch session pnl + DD check ─────────────────
+        // Fix A: when DD trips, also START a recovery cooldown — sticky
+        // dd_triggered without a recovery path leaves accounts dead for
+        // the rest of the fold, leaking variance from popart σ and
+        // pinning IQN-τ at its floor.
+        const float pnl_new = session_pnl_per_batch[b] + rewards[b];
+        session_pnl_per_batch[b] = pnl_new;
+        const bool was_triggered = session_dd_triggered_per_batch[b] >= 0.5f;
+        if (pnl_new < dd_limit && !was_triggered) {
+            session_dd_triggered_per_batch[b] = 1.0f;
+            cooldown_remaining_per_batch[b]   = cool_dur;  // recovery clock
+        }
+
+        // ── 2. Per-batch cooldown decrement + recovery reset ────
+        // When the cooldown clock expires, give the account a fresh
+        // start — matches [[feedback_surfer_philosophy_trading]]:
+        // accept the wipeout, take the forced break, then get back on
+        // the board. Otherwise the account contributes V_target ≈
+        // γ·V(s'_unchanged) for the rest of the fold (zero-variance
+        // dead-weight that compounds in popart σ).
+        if (cool_prev > 0.0f) {
+            const float cool_new = cool_prev - 1.0f;
+            cooldown_remaining_per_batch[b] = cool_new;
+            if (cool_new == 0.0f) {
+                session_pnl_per_batch[b]          = 0.0f;
+                session_dd_triggered_per_batch[b] = 0.0f;
+                // consec already cleared at its own limit-trip path
+            }
+        }
+
+        // ── 3. Per-batch consec-loss tracking on closes ─────────
+        // r == 0 with done: ambiguous break-even, leave streak as-is.
+        float consec = consec_loss_per_batch[b];
+        if (dones[b] >= 0.5f) {
+            const float r = rewards[b];
+            if      (r < 0.0f) consec += 1.0f;
+            else if (r > 0.0f) consec  = 0.0f;
+        }
+        if (consec >= consec_lim) {
+            // Streak limit on THIS account — open its cooldown, reset
+            // streak. Other accounts unaffected. Recovery reset above
+            // will also clear it when the cooldown clock expires.
+            cooldown_remaining_per_batch[b] = cool_dur;
+            consec = 0.0f;
+        }
+        consec_loss_per_batch[b] = consec;
+
+        // ── Aggregates ──────────────────────────────────────────
+        // Active = post-recovery state (after the reset path above), so
+        // accounts that just recovered this step count as active again.
+        const float final_pnl       = session_pnl_per_batch[b];
+        const float final_consec    = consec_loss_per_batch[b];
+        const float final_cool      = cooldown_remaining_per_batch[b];
+        const float final_triggered = session_dd_triggered_per_batch[b];
+        if (final_pnl   < worst_pnl)    worst_pnl       = final_pnl;
+        if (final_consec > worst_consec) worst_consec    = final_consec;
+        if (final_triggered >= 0.5f)    any_dd_trig     = 1.0f;
+        if (final_cool > max_cool_remain) max_cool_remain = final_cool;
+        if (final_triggered < 0.5f) {
+            active_pnl_sum += final_pnl;
+            n_active       += 1;
+        }
+
+        // Fleet-fraction counters. consec_near_lim uses (limit - 1) as
+        // the threshold since the kernel resets consec to 0 the moment
+        // it hits the limit (line above), so we'd never observe consec
+        // AT limit at the aggregation point. (limit - 1) catches "about
+        // to trip" which is the diagnostic-relevant state.
+        if (final_cool > 0.0f)                       n_in_cooldown += 1;
+        if (final_consec >= consec_lim - 1.0f)       n_consec_near_lim += 1;
+        if (final_triggered >= 0.5f)                 n_dd_triggered += 1;
+        if (final_pnl < 0.0f)                        n_session_neg += 1;
+
+        // ── Edge-decay Phase 1: Page-Hinkley state update ─────────
+        // Updates ONLY on done events (close-trade gate, same as consec).
+        // σ-normalized via σ_welford (slot 725); δ, λ are unit-less.
+        // m, M only accumulate AFTER warmup completes (cnt_prev >= warmup_min)
+        // to avoid cold-start Welford bias being baked into permanent offset.
+        if (dones[b] >= 0.5f) {
+            const float y        = rewards[b] / pop_sigma;
+            const float mu_prev  = ph_mu_per_batch[b];
+            const float cnt_prev = ph_count_per_batch[b];
+            const float cnt      = cnt_prev + 1.0f;
+            // Welford mean update always runs (post-update value stored).
+            ph_mu_per_batch[b]    = mu_prev + (y - mu_prev) / cnt;
+            ph_count_per_batch[b] = cnt;
+            // PH cumulative + M gated behind warmup completion.
+            // SIGN: detect mean DECREASE (edge decay). The cumulative
+            // m = Σ(μ̄_pre − x_t − δ) grows when x_t < μ̄ − δ (signal is
+            // below recent mean by more than tolerance → degradation).
+            // The earlier formulation (x − μ̄ − δ) detects INCREASE which
+            // is the opposite of what we want; first cluster smoke
+            // (alpha-rl-n5x87 train step 1277) showed 77% of fleet
+            // alerted during normal training improvement, confirming
+            // the wrong-direction sign.
+            if (cnt_prev >= ph_warmup_min) {
+                const float m = ph_m_per_batch[b] + (mu_prev - y - ph_delta);
+                ph_m_per_batch[b] = m;
+                float M = ph_mmin_per_batch[b];
+                if (m < M) {
+                    ph_mmin_per_batch[b] = m;
+                    M = m;
+                }
+                ph_stat_per_batch[b] = m - M;
+            }
+        }
+
+        // Edge-decay fleet aggregates (every batch, every step — not gated
+        // on done). Active = past warmup; alerted = active AND stat > λ.
+        const float ph_stat_b = ph_stat_per_batch[b];
+        const float ph_cnt_b  = ph_count_per_batch[b];
+        if (ph_cnt_b < ph_warmup_min) {
+            n_ph_warmup += 1;
+        } else {
+            n_ph_active   += 1;
+            ph_active_sum += ph_stat_b;
+            if (ph_stat_b > ph_lambda) n_ph_alerted += 1;
+        }
+    }
+
+    // ── Canonical summary slots ────────────────────────────────────
+    // Fix B: IQN-τ reads `RL_SESSION_PNL_USD_INDEX` — feed it the
+    // mean-of-active-accounts so τ reflects the fleet's typical DD
+    // rather than one outlier's catastrophic loss. Worst stays
+    // visible for diag.
+    const float mean_active = (n_active > 0)
+        ? (active_pnl_sum / (float)n_active)
+        : 0.0f;
+    isv[RL_SESSION_PNL_USD_INDEX]          = mean_active;
+    isv[RL_SESSION_PNL_WORST_INDEX]        = worst_pnl;
+    isv[RL_SESSION_DD_TRIGGERED_INDEX]     = any_dd_trig;
+    isv[RL_CONSEC_LOSS_COUNT_INDEX]        = worst_consec;
+    isv[RL_COOLDOWN_REMAINING_STEPS_INDEX] = max_cool_remain;
+
+    // Fleet-fraction emits. b_size guaranteed > 0 by the launch-config
+    // assertion in the trainer (kernel returns early at threadIdx check
+    // above if b_size == 0 was somehow let through).
+    const float inv_b = 1.0f / (float)b_size;
+    isv[RL_CMDP_FRAC_IN_COOLDOWN_INDEX]       = (float)n_in_cooldown * inv_b;
+    isv[RL_CMDP_FRAC_CONSEC_NEAR_LIMIT_INDEX] = (float)n_consec_near_lim * inv_b;
+    isv[RL_CMDP_FRAC_DD_TRIGGERED_INDEX]      = (float)n_dd_triggered * inv_b;
+    isv[RL_CMDP_FRAC_SESSION_NEG_INDEX]       = (float)n_session_neg * inv_b;
+
+    // Edge-decay Phase 1 fleet emits. ph_mean and frac_ph_alerted use
+    // n_active denominator (NOT b_size) — only batches past warmup can
+    // be alerted; before warmup completes the denominator would structurally
+    // cap the alert rate. frac_ph_warmup uses b_size (proper fleet fraction).
+    isv[RL_EDGE_PH_MEAN_INDEX]         = (n_ph_active > 0) ? (ph_active_sum / (float)n_ph_active) : 0.0f;
+    isv[RL_EDGE_PH_FRAC_ALERTED_INDEX] = (n_ph_active > 0) ? ((float)n_ph_alerted / (float)n_ph_active) : 0.0f;
+    isv[RL_EDGE_PH_FRAC_WARMUP_INDEX]  = (float)n_ph_warmup * inv_b;
+}

crates/ml-alpha/cuda/rl_confidence_gate.cu

@@ -34,8 +34,15 @@
 #define RL_HOLD_TARGET_FRAC_INDEX      575
 #define RL_HOLD_FRAC_EMA_INDEX         576
 #define RL_CONF_GATE_MAX_HOLD_FRAC_INDEX 584
-#define RL_STOP_LOSS_THRESHOLD_INDEX    587
-#define RL_MEAN_ABS_PNL_EMA_INDEX      423
+// Phase 7b F5 (2026-06-05) Option A — interop with state-conditional
+// action availability mask. When F5 master gate (slot 823) is engaged
+// AND position is flat, F5 has DELIBERATELY forced the agent into an
+// opening action by masking Hold (and other invalid actions) in
+// pi_logits. Overriding that back to Hold here neutralizes F5's
+// surfer→trend choice-set forcing and prevents F5-G1 from achieving
+// `hold_frac_flat == 0`. The suppression is gated on F5-engaged AND
+// flat — in-position safety overrides are preserved verbatim.
+#define RL_F5_STATE_MASK_ENABLED_INDEX 823
 #define THRESHOLD_MIN                  0.05f
 #define THRESHOLD_MAX                  0.95f
 #define HOLD_EMA_ALPHA                 0.1f
@@ -53,35 +60,6 @@ extern "C" __global__ void rl_confidence_gate(
     const int b = blockIdx.x;
     if (b >= b_size) return;
 
-    // ── Hard stop-loss: override action to Flat when unrealized loss
-    // exceeds ISV-driven threshold. Fires BEFORE gate logic so the
-    // lobsim actually closes the position (no state mismatch).
-    // unrealized_loss = |vwap - mid| × |lots|; normalized by mean_abs_pnl.
-    {
-        const unsigned char* p = pos_state + b * pos_bytes;
-        const int lots = *(const int*)(p + 0);
-        if (lots != 0) {
-            const float stop_thresh = isv[RL_STOP_LOSS_THRESHOLD_INDEX];
-            const float mean_abs = fmaxf(isv[RL_MEAN_ABS_PNL_EMA_INDEX], 1e-6f);
-            // Approximate mid from the first bid/ask level would need
-            // book data; instead use the realized_pnl delta as a proxy
-            // for position health. Simpler: use vwap vs realized_pnl trend.
-            // For now, use the unit_entry_price-based unrealized_r from
-            // trade_context — but that runs AFTER this kernel.
-            //
-            // Practical approach: read peak_equity (offset 12) and
-            // realized_pnl (offset 8). Drawdown from peak = peak - realized.
-            const float realized = *(const float*)(p + 8);
-            const float peak = *(const float*)(p + 12);
-            const float drawdown = peak - realized;
-            const float normalized_dd = drawdown / mean_abs;
-            if (normalized_dd > stop_thresh) {
-                actions[b] = (lots > 0) ? 3 : 4;  // FlatFromLong / FlatFromShort
-                return;
-            }
-        }
-    }
-
     const int current_step = (int)isv[RL_STEP_COUNTER_ISV_INDEX];
     const int warmup = (int)isv[RL_GATE_WARMUP_STEPS_INDEX];
     if (current_step < warmup) return;
@@ -97,6 +75,13 @@ extern "C" __global__ void rl_confidence_gate(
     const int action = actions[b];
     if (action == ACTION_HOLD) return;
 
+    // Gate is opening-only: a non-flat position has already cleared
+    // the confidence check, so overriding it to Hold would suppress
+    // legitimate adds/exits. pos_state[0..4] = position_lots:i32.
+    const int position_lots =
+        *reinterpret_cast<const int*>(pos_state + b * pos_bytes);
+    if (position_lots != 0) return;
+
     const float threshold  = isv[RL_CONF_GATE_THRESHOLD_INDEX];
     const float lambda     = isv[RL_CONF_GATE_LAMBDA_INDEX];
     const float sigma_norm = isv[RL_CONF_GATE_SIGMA_NORM_INDEX];
@@ -142,7 +127,14 @@ extern "C" __global__ void rl_confidence_gate(
     const float lcb = (mu - v_min) - lambda * sigma;
     const float conf = fmaxf(0.0f, fminf(lcb / span, 1.0f));
 
-    if (conf < threshold) {
+    // Phase 7b F5 (2026-06-05) Option A — suppress Hold override when
+    // F5 is engaged and we are flat. F5 has masked Hold (and other
+    // invalid actions) in pi_logits, so the sampled action is a
+    // deliberate F5-allowed opening. The early-return at line above
+    // (`position_lots != 0 → return`) already restricts us to flat
+    // here, so checking only the F5 master gate is sufficient.
+    const bool f5_engaged = (isv[RL_F5_STATE_MASK_ENABLED_INDEX] > 0.5f);
+    if (conf < threshold && !f5_engaged) {
         actions[b] = ACTION_HOLD;
         isv[RL_CONF_GATE_FIRED_COUNT_INDEX] += 1.0f;
     }

crates/ml-alpha/cuda/rl_deterministic_checksum.cu

@@ -0,0 +1,79 @@
+// rl_deterministic_checksum.cu — provably deterministic sum-of-squares.
+//
+// Phase 1 of the determinism foundation
+// (`docs/superpowers/specs/2026-06-02-determinism-foundation.md` §1.1).
+//
+// Computes `Σ data[i]^2` over `n` elements with construction-guaranteed
+// determinism. Launch geometry is hard-coded (1,1,1)/(1,1,1) — a single
+// thread iterates sequentially. The accumulator is double precision; no
+// intermediate fp32 round-off varies with launch geometry or block count.
+//
+// Trade-off vs throughput:
+//   * RTX 3050 / L40S sum-of-squares throughput at single-thread is on the
+//     order of 10^9 elements/s. The largest tensor in foxhunt's RL train
+//     loop is ~24k floats (Q-head grad_w). Cost per launch is therefore
+//     dominated by launch overhead (~5-20 μs) — 15 launches/step add
+//     ~150-300 μs total, well within the dev-mode budget per §4 of the
+//     spec.
+//   * The deliberately slow accumulation order is the entire point. Any
+//     parallel reduction tree introduces order-of-addition variance that
+//     would invalidate the diagnostic.
+//
+// Per `feedback_no_atomicadd`: zero atomics — pure sequential accumulation.
+// Per `feedback_no_stubs`: kernel always executes, no early-exit; n=0
+// writes 0.0 (defined behavior).
+// Per `feedback_no_nvrtc`: registered in `crates/ml-alpha/build.rs` for
+// AOT compilation to per-arch cubin.
+//
+// Output is f64 (one element). Reading it from the host is the only CPU
+// roundtrip; the value itself is computed entirely on device, satisfying
+// `feedback_cpu_is_read_only`.
+
+#include <cuda_runtime.h>
+#include <stdint.h>
+
+// `n` is passed as int (32-bit) to match the kernel arg-passing
+// convention used throughout foxhunt (raw_launch + RawArgs::push_i32).
+// All checksum-able tensors in the RL trainer are < 2 billion elements
+// (the largest, Q-head weights with HIDDEN_DIM * N_ACTIONS * Q_N_ATOMS,
+// is on the order of 1e5 floats), so int is safe.
+
+extern "C" __global__ void rl_deterministic_checksum_f32(
+    const float* __restrict__ data,
+    int                       n,
+    double*      __restrict__ out
+) {
+    // Single block, single thread — only thread 0 does anything.
+    if (threadIdx.x != 0 || blockIdx.x != 0) {
+        return;
+    }
+    double acc = 0.0;
+    for (int i = 0; i < n; ++i) {
+        const double v = static_cast<double>(data[i]);
+        acc += v * v;
+    }
+    out[0] = acc;
+}
+
+// Integer variant for replay indices and other u32/i32 tensors. Same
+// accumulation discipline; the input is cast through int64 to avoid
+// signed-overflow UB on the sum-of-squares accumulation.
+extern "C" __global__ void rl_deterministic_checksum_i32(
+    const int*   __restrict__ data,
+    int                       n,
+    double*      __restrict__ out
+) {
+    if (threadIdx.x != 0 || blockIdx.x != 0) {
+        return;
+    }
+    double acc = 0.0;
+    for (int i = 0; i < n; ++i) {
+        // Cast to int64 first to widen — int32^2 fits in int64 exactly;
+        // double's 53-bit mantissa may round large sums but the
+        // accumulation ORDER is still deterministic, which is the
+        // contract.
+        const int64_t v = static_cast<int64_t>(data[i]);
+        acc += static_cast<double>(v) * static_cast<double>(v);
+    }
+    out[0] = acc;
+}

crates/ml-alpha/cuda/rl_drawdown_stop.cu

@@ -1,49 +0,0 @@
-// rl_drawdown_stop.cu — per-step drawdown penalty + hard stop-loss.
-//
-// Runs AFTER rl_trade_context_update (which computes unrealized_r).
-// Reads unrealized_r from trade_context_d and applies:
-//
-//   1. Per-step drawdown penalty: adds min(0, unrealized_r) × PENALTY_RATE
-//      to rewards[b]. Creates continuous exit gradient on losing positions.
-//      Penalty-only (never positive) = no exposure incentive.
-//
-//   2. Hard stop-loss: when unrealized_r < -STOP_THRESHOLD, force-close
-//      by setting dones[b] = 1. The realized PnL at this point becomes
-//      the final trade reward. Caps max loss per trade.
-//
-// Both thresholds are ISV-driven per feedback_isv_for_adaptive_bounds.
-// Grid: ceil(B/32), Block: 32.
-
-#define RL_DRAWDOWN_PENALTY_RATE_INDEX  586
-#define RL_STOP_LOSS_THRESHOLD_INDEX    587
-#define TRADE_CONTEXT_STRIDE            5
-#define UNREALIZED_R_OFFSET             1
-
-extern "C" __global__ void rl_drawdown_stop(
-    const float* __restrict__ trade_context,  // [B, TRADE_CONTEXT_STRIDE]
-    float*       __restrict__ rewards,         // [B] IN/OUT
-    float*       __restrict__ dones,           // [B] IN/OUT
-    float*       __restrict__ isv,
-    int          b_size
-) {
-    const int b = blockIdx.x * blockDim.x + threadIdx.x;
-    if (b >= b_size) return;
-
-    const float unrealized_r = trade_context[b * TRADE_CONTEXT_STRIDE + UNREALIZED_R_OFFSET];
-    const float penalty_rate = isv[RL_DRAWDOWN_PENALTY_RATE_INDEX];
-    const float stop_thresh  = isv[RL_STOP_LOSS_THRESHOLD_INDEX];
-
-    // Per-step drawdown penalty: only fires when losing (unrealized_r < 0).
-    // min(0, x) * rate is always <= 0.
-    if (unrealized_r < 0.0f) {
-        rewards[b] += unrealized_r * penalty_rate;
-    }
-
-    // Hard stop-loss DISABLED: setting dones=1 here creates a state
-    // mismatch — the lobsim position stays open while Q sees a false
-    // close. The done signal must come from actual position changes
-    // in the lobsim, not synthetic overrides. To implement hard
-    // stop-loss properly, the action must be overridden to FlatL/FlatS
-    // BEFORE the lobsim step, not after.
-    (void) stop_thresh;
-}

crates/ml-alpha/cuda/rl_dueling_q_bellman_target.cu

@@ -0,0 +1,57 @@
+// rl_dueling_q_bellman_target.cu — Phase 4 Bellman target build.
+//
+// Picks argmax_a' over the target net's composed_Q at s_{t+1}, then
+// builds the scalar Bellman target:
+//
+//   a*_b           = argmax_a' target_composed_Q[b, a']
+//   target_value[b] = r[b] + γ × (1 − done[b]) × target_composed_Q[b, a*_b]
+//
+// γ read from ISV bus at runtime — same source as C51 / IQN Bellman
+// target kernels (RL_GAMMA_INDEX=400). For n-step returns, the
+// per-batch n_step_gammas are passed (matches existing PER convention).
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (N_ACTIONS, 1, 1)
+//   One block per batch. Each thread holds one action's value.
+//   Tree-reduce in shared mem to find argmax. Thread 0 computes the
+//   final target.
+//
+// Per feedback_no_atomicadd: sole-writer per output cell.
+
+#define N_ACTIONS  11
+
+extern "C" __global__ void rl_dueling_q_bellman_target_build(
+    const float* __restrict__ target_composed_q,  // [B × N_ACTIONS]
+    const float* __restrict__ rewards,            // [B]
+    const float* __restrict__ dones,              // [B]
+    const float* __restrict__ n_step_gammas,      // [B] (γ^n_step per sample)
+    int          B,
+    float*       __restrict__ target_value_out    // [B]
+) {
+    const int b = blockIdx.x;
+    const int a = threadIdx.x;
+    if (b >= B)          return;
+    if (a >= N_ACTIONS)  return;
+
+    __shared__ float s_q[N_ACTIONS];
+    s_q[a] = target_composed_q[b * N_ACTIONS + a];
+    __syncthreads();
+
+    if (a == 0) {
+        // Find argmax serially (small N).
+        float best = s_q[0];
+        #pragma unroll
+        for (int i = 1; i < N_ACTIONS; ++i) {
+            if (s_q[i] > best) best = s_q[i];
+        }
+
+        const float r       = rewards[b];
+        const float done    = dones[b];
+        const float gamma_n = n_step_gammas[b];
+
+        // Standard Bellman with done masking:
+        //   target = r + γ^n × (1 − done) × max_q
+        target_value_out[b] = r + gamma_n * (1.0f - done) * best;
+    }
+}

crates/ml-alpha/cuda/rl_dueling_q_decompose_and_bwd.cu

@@ -0,0 +1,89 @@
+// rl_dueling_q_decompose_and_bwd.cu — Phase 4 decompose grad + weight grad.
+//
+// Decompose:
+//   composed_Q[b, a] = V[b] + A[b, a] − (1/N) Σ_a' A[b, a']
+//
+// Chain rule (only taken action has nonzero grad_composed[b, a]):
+//   grad_V[b]    = Σ_a grad_composed[b, a] = grad_composed[b, a_taken]
+//   grad_A[b, a] = grad_composed[b, a] − (1/N) × grad_V[b]
+//
+// For a == a_taken: grad_A[b, a] = (1 − 1/N) × grad_composed[b, a_taken]
+// For a ≠ a_taken: grad_A[b, a] = −(1/N) × grad_composed[b, a_taken]
+//
+// After decompose, compute per-batch weight gradients via outer
+// product with h_t:
+//   grad_w_v_pb[b, c]    = grad_V[b] × h_t[b, c]
+//   grad_b_v_pb[b]       = grad_V[b]
+//   grad_w_a_pb[b, c, a] = grad_A[b, a] × h_t[b, c]
+//   grad_b_a_pb[b, a]    = grad_A[b, a]
+//
+// Caller reduces per-batch grads via reduce_axis0 to final shapes:
+//   grad_w_v [HIDDEN_DIM]
+//   grad_b_v [1]
+//   grad_w_a [HIDDEN_DIM × N_ACTIONS]
+//   grad_b_a [N_ACTIONS]
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (HIDDEN_DIM, 1, 1)  — one thread per hidden-dim index
+//   Each thread loops over N_ACTIONS to write A weights, plus the
+//   single V weight. Thread 0 additionally writes grad_b_v_pb +
+//   grad_b_a_pb (small).
+//
+// Per feedback_no_atomicadd: sole-writer per (b, c, a) and (b, c) cells.
+
+#define HIDDEN_DIM 128
+#define N_ACTIONS  11
+
+extern "C" __global__ void rl_dueling_q_decompose_and_weight_grad(
+    const float* __restrict__ h_t,             // [B × HIDDEN_DIM]
+    const float* __restrict__ grad_composed,   // [B × N_ACTIONS] (only taken cell nonzero)
+    const int*   __restrict__ actions_taken,   // [B]
+    int          B,
+    float*       __restrict__ grad_w_v_pb,     // [B × HIDDEN_DIM]
+    float*       __restrict__ grad_b_v_pb,     // [B]
+    float*       __restrict__ grad_w_a_pb,     // [B × HIDDEN_DIM × N_ACTIONS]
+    float*       __restrict__ grad_b_a_pb      // [B × N_ACTIONS]
+) {
+    const int b = blockIdx.x;
+    const int c = threadIdx.x;
+    if (b >= B)          return;
+    if (c >= HIDDEN_DIM) return;
+
+    int a_t = actions_taken[b];
+    if (a_t < 0)            a_t = 0;
+    if (a_t >= N_ACTIONS)   a_t = 0;
+
+    // grad_composed is nonzero only at a == a_t.
+    const float gc_taken = grad_composed[b * N_ACTIONS + a_t];
+
+    // grad_V[b] = Σ_a grad_composed[b, a] = gc_taken (others are 0).
+    const float grad_v = gc_taken;
+
+    // h_t[b, c].
+    const float h_bc = h_t[b * HIDDEN_DIM + c];
+
+    // Per-batch V weight grad.
+    grad_w_v_pb[b * HIDDEN_DIM + c] = grad_v * h_bc;
+
+    // Per-batch A weight grad (one thread writes N_ACTIONS values).
+    // grad_A[b, a] = grad_composed[b, a] − (1/N) × grad_V[b]
+    //              = (a == a_t ? gc_taken : 0) − (1/N) × gc_taken
+    const float inv_N = 1.0f / (float)N_ACTIONS;
+    #pragma unroll
+    for (int a = 0; a < N_ACTIONS; ++a) {
+        const float grad_a = (a == a_t ? gc_taken : 0.0f) - inv_N * gc_taken;
+        // Layout: grad_w_a_pb[b, c, a] = h_bc * grad_a
+        grad_w_a_pb[b * HIDDEN_DIM * N_ACTIONS + c * N_ACTIONS + a] = h_bc * grad_a;
+    }
+
+    // Thread 0 writes biases (small).
+    if (c == 0) {
+        grad_b_v_pb[b] = grad_v;
+        #pragma unroll
+        for (int a = 0; a < N_ACTIONS; ++a) {
+            const float grad_a = (a == a_t ? gc_taken : 0.0f) - inv_N * gc_taken;
+            grad_b_a_pb[b * N_ACTIONS + a] = grad_a;
+        }
+    }
+}

crates/ml-alpha/cuda/rl_dueling_q_forward.cu

@@ -0,0 +1,121 @@
+// rl_dueling_q_forward.cu — Phase 4 Independent Dueling Q head forward.
+//
+// Per spec docs/superpowers/specs/2026-05-30-phase4-independent-dueling-head-design.md.
+//
+// Architecture: parallel head to C51/IQN/π/value_head with ZERO shared
+// state with downstream consumers (ensemble, distill, action selection).
+// Trains its own V + A weights via Bellman loss on composed_Q at taken
+// action. V output feeds PPO advantage baseline (Phase 4.3) — composed_Q
+// is internal to this head's loss path and never consumed elsewhere.
+//
+// Why this design (vs Phase 2 v2 / Phase 3.x failures):
+//   - Phase 2 v2 (scalar V + categorical CE): N/A here — uses scalar
+//     Bellman loss, no softmax math eating V.
+//   - Phase 3.2 (V_IQN cross-architecture calibration): V_dq trained
+//     on same Bellman reward signal as C51, scales align by construction.
+//   - Phase 3.1 (composed Q perturbs ensemble): composed_Q_dq never
+//     feeds ensemble. Only feeds its own Bellman loss + diag.
+//   - Phase 3.1-fix (gradient structure mismatch contaminates weights):
+//     DuelingQHead has its OWN weights — mean-zero A grad pattern only
+//     affects DuelingQHead's training, no shared weights with C51/IQN.
+//
+// Forward computation:
+//   V[b]            = Σ_c w_v[c] × h_t[b, c] + b_v[0]
+//   A[b, a]         = Σ_c w_a[c, a] × h_t[b, c] + b_a[a]    for a in 0..N
+//   composed_Q[b, a] = V[b] + A[b, a] − (1/N) Σ_a' A[b, a']
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (HIDDEN_DIM = 128, 1, 1)
+//   One block per batch. Each thread computes one hidden-dim term and
+//   participates in tree-reduce. Then thread 0 broadcasts to A
+//   computation. Each thread computes one action's matmul contribution.
+//   Mean reduction over N_ACTIONS done in shared mem.
+//
+// Memory:
+//   shared float s_h[HIDDEN_DIM]                — cached h_t row
+//   shared float s_v                            — scalar V value
+//   shared float s_a[N_ACTIONS]                 — A values (post-bias)
+//
+// Per feedback_no_atomicadd: sole-writer per output cell.
+// Per feedback_cpu_is_read_only: pure device kernel.
+
+#define HIDDEN_DIM 128
+#define N_ACTIONS  11
+
+extern "C" __global__ void rl_dueling_q_forward(
+    const float* __restrict__ h_t,            // [B × HIDDEN_DIM]
+    const float* __restrict__ w_v,            // [HIDDEN_DIM]
+    const float* __restrict__ b_v,            // [1]
+    const float* __restrict__ w_a,            // [HIDDEN_DIM × N_ACTIONS], row-major
+    const float* __restrict__ b_a,            // [N_ACTIONS]
+    int          B,
+    float*       __restrict__ v_out,          // [B]
+    float*       __restrict__ a_out,          // [B × N_ACTIONS]
+    float*       __restrict__ q_composed_out  // [B × N_ACTIONS]
+) {
+    const int b = blockIdx.x;
+    const int c = threadIdx.x;
+    if (b >= B)          return;
+    if (c >= HIDDEN_DIM) return;
+
+    extern __shared__ float s_h[];  // [HIDDEN_DIM], sized by smem arg
+
+    // ── Load h_t[b] into shared mem ──
+    s_h[c] = h_t[b * HIDDEN_DIM + c];
+    __syncthreads();
+
+    // ── V projection (block-reduce) ──
+    // V[b] = Σ_c w_v[c] × s_h[c] + b_v[0]
+    // Tree reduction over HIDDEN_DIM threads.
+    __shared__ float s_v_partial[HIDDEN_DIM];
+    s_v_partial[c] = w_v[c] * s_h[c];
+    __syncthreads();
+    // Tree reduce
+    for (int stride = HIDDEN_DIM / 2; stride > 0; stride >>= 1) {
+        if (c < stride) {
+            s_v_partial[c] += s_v_partial[c + stride];
+        }
+        __syncthreads();
+    }
+    __shared__ float s_v;
+    if (c == 0) {
+        s_v = s_v_partial[0] + b_v[0];
+        v_out[b] = s_v;
+    }
+    __syncthreads();
+
+    // ── A projection (each thread handles one action) ──
+    // A[b, a] = Σ_c w_a[c, a] × s_h[c] + b_a[a]
+    // Threads 0..N_ACTIONS-1 compute one action each.
+    // Other threads idle for this section.
+    __shared__ float s_a[N_ACTIONS];
+    if (c < N_ACTIONS) {
+        float acc = 0.0f;
+        #pragma unroll
+        for (int i = 0; i < HIDDEN_DIM; ++i) {
+            acc += w_a[i * N_ACTIONS + c] * s_h[i];
+        }
+        acc += b_a[c];
+        s_a[c] = acc;
+        a_out[b * N_ACTIONS + c] = acc;
+    }
+    __syncthreads();
+
+    // ── Mean over actions (thread 0 only — small N) ──
+    __shared__ float s_mean_a;
+    if (c == 0) {
+        float sum = 0.0f;
+        #pragma unroll
+        for (int i = 0; i < N_ACTIONS; ++i) {
+            sum += s_a[i];
+        }
+        s_mean_a = sum * (1.0f / (float)N_ACTIONS);
+    }
+    __syncthreads();
+
+    // ── Compose Q (each thread for one action writes the result) ──
+    if (c < N_ACTIONS) {
+        q_composed_out[b * N_ACTIONS + c] = s_v + s_a[c] - s_mean_a;
+    }
+}

crates/ml-alpha/cuda/rl_dueling_q_loss_and_grad.cu

@@ -0,0 +1,83 @@
+// rl_dueling_q_loss_and_grad.cu — Phase 4 Bellman loss + decompose backward.
+//
+// Computes the scalar Huber loss on (target − online_composed_Q[taken])
+// AND emits grad_composed[B × N_ACTIONS] in one fused kernel.
+//
+// Loss (per-batch):
+//   δ_b         = target_value[b] − online_composed_Q[b, a_taken[b]]
+//   L_b         = Huber(δ_b, κ=1.0) / B    (mean over batch)
+//   loss_per_batch[b] = L_b
+//
+// Gradient w.r.t. online_composed_Q (mostly zero, nonzero at taken):
+//   For a_taken: dL/d_composed[b, a_taken] = −(1/B) × Huber'(δ_b)
+//   For a ≠ a_taken: dL/d_composed[b, a] = 0
+//
+// Huber'(δ) = δ                  if |δ| ≤ κ
+//           = κ × sign(δ)        if |δ| > κ
+//
+// Block layout:
+//   grid  = (B, 1, 1)
+//   block = (N_ACTIONS, 1, 1)
+//   Each thread writes one (b, a) cell of grad_composed; thread 0
+//   computes loss + the nonzero gradient scalar.
+//
+// Per feedback_no_atomicadd: sole-writer per cell.
+
+#define N_ACTIONS  11
+#define HUBER_KAPPA 1.0f
+
+extern "C" __global__ void rl_dueling_q_loss_and_grad(
+    const float* __restrict__ online_composed_q,  // [B × N_ACTIONS]
+    const float* __restrict__ target_value,       // [B]
+    const int*   __restrict__ actions_taken,      // [B]
+    int          B,
+    float*       __restrict__ loss_per_batch,     // [B]
+    float*       __restrict__ grad_composed       // [B × N_ACTIONS]
+) {
+    const int b = blockIdx.x;
+    const int a = threadIdx.x;
+    if (b >= B)          return;
+    if (a >= N_ACTIONS)  return;
+
+    // Defensive clamp on actions_taken (trainer should never produce
+    // out-of-range, but guard against corrupt indices).
+    int a_t = actions_taken[b];
+    if (a_t < 0)            a_t = 0;
+    if (a_t >= N_ACTIONS)   a_t = 0;
+
+    __shared__ float s_grad_scalar;
+
+    if (a == 0) {
+        const float q_taken = online_composed_q[b * N_ACTIONS + a_t];
+        const float target  = target_value[b];
+        const float delta   = target - q_taken;
+        const float abs_d   = fabsf(delta);
+        const float inv_B   = 1.0f / (float)B;
+
+        // Huber loss.
+        float l;
+        if (abs_d <= HUBER_KAPPA) {
+            l = 0.5f * delta * delta;
+        } else {
+            l = HUBER_KAPPA * (abs_d - 0.5f * HUBER_KAPPA);
+        }
+        loss_per_batch[b] = l * inv_B;
+
+        // Huber'(δ) — gradient of l w.r.t. delta.
+        float huber_grad;
+        if (abs_d <= HUBER_KAPPA) {
+            huber_grad = delta;
+        } else {
+            huber_grad = HUBER_KAPPA * ((delta > 0.0f) ? 1.0f : -1.0f);
+        }
+        // dL/d_composed[a_taken] = (dL/dδ) × (dδ/d_composed[a_taken])
+        //                        = (−1/B) × huber_grad   (δ = target − Q)
+        s_grad_scalar = -inv_B * huber_grad;
+    }
+    __syncthreads();
+
+    // All threads write grad_composed. Only the taken action gets a
+    // nonzero value (CE on a single Q value).
+    const int idx = b * N_ACTIONS + a;
+    grad_composed[idx] = (a == a_t) ? s_grad_scalar : 0.0f;
+}

crates/ml-alpha/cuda/rl_entropy_coef_controller.cu

@@ -46,13 +46,35 @@
 
 #define RL_ENTROPY_COEF_INDEX 403
 #define N_ACTIONS               11
-#define COEF_MIN              0.0f
-#define COEF_MAX              0.5f
+// COEF MIN/MAX clamp bounds are now ISV-driven per the 2026-05-30
+// clamp-bound extension. Runtime-tunable + visible in diag.
+#define RL_ENTROPY_COEF_MIN_INDEX     645
+#define RL_ENTROPY_COEF_MAX_INDEX     646
 // ISV-driven entropy-target fraction per `feedback_isv_for_adaptive_bounds`.
 // Default 0.7 (70% of ln(N_ACTIONS) = "explore but not too randomly").
 // Seeded by rl_isv_write at trainer init.
 #define RL_ENTROPY_TARGET_FRAC_INDEX 458
-#define WIENER_ALPHA_FLOOR    0.4f
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX  659
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// noise floor derives from observed entropy_observed_ema variance via
+// Welford triples. Replaces the hardcoded `0.5f` emergency-bypass fraction
+// with `max(h_target × 0.5, h_target − 2σ)` — under Phase 4.5 the entropy
+// distribution narrows around the SAC target and the hardcoded 0.5×h_target
+// emergency gate never fires, leaving the Wiener blend to drag coef to MIN
+// (alpha-rl-... fold 0 confirmed entropy_coef stuck at 0.01).
+// Asymmetric Schulman semantics: coef RAISES on a single below-target
+// observation (entropy collapse = safety signal, act fast); coef DROPS
+// only after N consecutive above-target observations (healthy entropy =
+// drift coef down patiently).
+#define RL_ENTROPY_OBS_VAR_COUNT_INDEX     600
+#define RL_ENTROPY_OBS_VAR_M2_INDEX        602
+#define RL_ENTROPY_OBS_BELOW_COUNT_INDEX   603
+#define RL_SCHULMAN_TOLERANCE_INDEX        468
+#define NOISE_FLOOR_TARGET_FRAC            0.5f  // floor ≥ 50% of target
+#define NOISE_FLOOR_STD_MULTIPLIER         2.0f  // floor ≥ 2σ of observed signal
+#define WIDEN_PATIENCE_CONSECUTIVE         3.0f  // descent requires N above-band steps
 
 
 // ─────────────────────────────────────────────────────────────────────
@@ -101,10 +123,12 @@ extern "C" __global__ void rl_entropy_coef_controller(
     // At h_obs = 0 (total collapse): coef = COEF_MAX (emergency)
     // At h_obs > h_target: coef = COEF_FLOOR (no penalty for exploring)
     const float COEF_FLOOR = 0.01f;
+    const float coef_min = isv[RL_ENTROPY_COEF_MIN_INDEX];
+    const float coef_max = isv[RL_ENTROPY_COEF_MAX_INDEX];
     const float deficit_frac = fmaxf(0.0f,
         fminf((h_target - entropy_observed_ema) / fmaxf(h_target, 1e-6f), 1.0f));
-    float coef_target = COEF_FLOOR + (COEF_MAX - COEF_FLOOR) * deficit_frac;
-    coef_target = fmaxf(COEF_MIN, fminf(coef_target, COEF_MAX));
+    float coef_target = COEF_FLOOR + (coef_max - COEF_FLOOR) * deficit_frac;
+    coef_target = fmaxf(coef_min, fminf(coef_target, coef_max));
 
     // Bootstrap on sentinel 0.0 per pearl_first_observation_bootstrap:
     // first emit replaces directly with the computed target. At cold
@@ -117,17 +141,56 @@ extern "C" __global__ void rl_entropy_coef_controller(
         return;
     }
 
-    // Emergency: bypass Wiener blend when entropy is below 50% of target.
-    // The slow blend can't react fast enough to prevent Hold collapse.
-    if (entropy_observed_ema < h_target * 0.5f && entropy_observed_ema > 0.0f) {
+    // Adaptive noise floor — signal-driven per
+    // `pearl_zscore_normalization_for_magnitude_asymmetric_signals` and
+    // `feedback_adaptive_not_tuned`. Replaces hardcoded `h_target × 0.5`
+    // emergency-bypass threshold with adaptive `max(h_target × 0.5,
+    // h_target − 2σ_observed)` so the emergency path still fires when
+    // entropy drops more than 2σ below its observed mean even if the
+    // distribution is so narrow that 50% × h_target is unreachable.
+    // Welford sample variance = M² / (count − 1) when count > 1.
+    const float h_count = isv[RL_ENTROPY_OBS_VAR_COUNT_INDEX];
+    const float h_var = (h_count > 1.0f)
+        ? isv[RL_ENTROPY_OBS_VAR_M2_INDEX] / (h_count - 1.0f)
+        : 0.0f;
+    const float h_std = sqrtf(h_var);
+    const float emergency_floor = fmaxf(h_target * NOISE_FLOOR_TARGET_FRAC,
+                                         h_target - h_std * NOISE_FLOOR_STD_MULTIPLIER);
+
+    // Asymmetric Schulman (spec 2026-05-30): RAISE coef on a single
+    // below-emergency-floor observation — entropy collapse is a safety
+    // signal we act on fast. DROP coef only after N consecutive
+    // above-band observations so a single noisy spike of healthy
+    // entropy can't drag coef toward MIN. Below-counter is on the
+    // "healthy entropy" direction here (entropy_observed > h_target ×
+    // tolerance), distinct from the canonical Schulman semantics where
+    // below-counter means "input below band."
+    if (entropy_observed_ema > 0.0f && entropy_observed_ema < emergency_floor) {
         isv[RL_ENTROPY_COEF_INDEX] = coef_target;
+        isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = 0.0f;
         return;
     }
 
-    // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a        = fmaxf(alpha, WIENER_ALPHA_FLOOR);
-    float       coef_new = (1.0f - a) * coef_prev + a * coef_target;
+    const float tolerance = isv[RL_SCHULMAN_TOLERANCE_INDEX];
+    const float wiener_a  = fmaxf(alpha, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
+    float       coef_new  = (1.0f - wiener_a) * coef_prev + wiener_a * coef_target;
+    coef_new = fmaxf(coef_min, fminf(coef_new, coef_max));
+
+    if (coef_new < coef_prev && entropy_observed_ema > h_target * tolerance) {
+        // Healthy-entropy direction — require N consecutive observations
+        // before letting the Wiener blend drag coef downward. Single noisy
+        // high-entropy spike must not erode the entropy bonus.
+        const float new_count = isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] + 1.0f;
+        isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = new_count;
+        if (new_count < WIDEN_PATIENCE_CONSECUTIVE) {
+            // Hold coef at previous value until patience accumulates.
+            isv[RL_ENTROPY_COEF_INDEX] = coef_prev;
+            return;
+        }
+    } else {
+        // Either entropy unhealthy (coef rising) or in-band — reset patience.
+        isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = 0.0f;
+    }
 
-    coef_new = fmaxf(COEF_MIN, fminf(coef_new, COEF_MAX));
     isv[RL_ENTROPY_COEF_INDEX] = coef_new;
 }

crates/ml-alpha/cuda/rl_eval_warmup_decay.cu

@@ -0,0 +1,105 @@
+// rl_eval_warmup_decay.cu — defensive eval-boundary calibration (v9).
+//
+// Spec: docs/superpowers/specs/2026-05-31-v9-defensive-eval-boundary-calibration.md
+// Pearl: pearl_adaptive_carryover_discipline
+//
+// At every regime boundary (train→eval, fold transition), the trainer
+// calls `reset_session_state` which sets `RL_REGIME_TRANSITION_REMAINING_INDEX`
+// to the configured warmup duration. This kernel runs once per step
+// thereafter; while the counter is positive, it overrides four
+// risk-sizing controller floors with conservative defensive values.
+//
+// Schedule (let R = warmup_remaining, W = warmup_steps, D = decay_steps):
+//
+//   R > D            full defensive overrides written
+//   0 < R ≤ D        linear interpolation: defensive (1) → normal (0)
+//   R = 0            normal values written once, counter goes to -1
+//   R < 0            no-op (warmup completed, controllers run unimpeded)
+//
+// The override slots affected are read-only by their consuming controllers
+// (Kelly safety_frac, IQN τ_min, entropy_coef_min, PPO clip ε_min), so
+// last-writer-wins applies cleanly when this kernel runs AFTER the
+// controller batch.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block, no atomics.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: defensive override values, normal
+//   target values, warmup/decay durations are all ISV-driven.
+
+#include <stdint.h>
+
+#define RL_REGIME_TRANSITION_REMAINING_INDEX              685
+#define RL_REGIME_TRANSITION_STEPS_CONFIG_INDEX           686
+#define RL_REGIME_TRANSITION_DECAY_STEPS_CONFIG_INDEX     687
+#define RL_EVAL_KELLY_SAFETY_DEFENSIVE_INDEX        688
+#define RL_EVAL_IQN_TAU_MIN_DEFENSIVE_INDEX         689
+#define RL_EVAL_ENTROPY_COEF_MIN_DEFENSIVE_INDEX    690
+#define RL_EVAL_PPO_CLIP_EPS_MIN_DEFENSIVE_INDEX    691
+#define RL_EVAL_KELLY_SAFETY_NORMAL_INDEX           692
+#define RL_EVAL_IQN_TAU_MIN_NORMAL_INDEX            693
+#define RL_EVAL_ENTROPY_COEF_MIN_NORMAL_INDEX       694
+#define RL_EVAL_PPO_CLIP_EPS_MIN_NORMAL_INDEX       695
+
+// Consumer slots (controller floors that this kernel overrides during warmup).
+#define RL_KELLY_SAFETY_FRAC_INDEX                  680
+#define RL_IQN_ACTION_TAU_MIN_INDEX                 672
+#define RL_ENTROPY_COEF_MIN_INDEX                   645
+#define RL_PPO_CLIP_EPS_MIN_INDEX                   640
+
+extern "C" __global__ void rl_eval_warmup_decay(
+    float* __restrict__ isv
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    const float remaining = isv[RL_REGIME_TRANSITION_REMAINING_INDEX];
+
+    // Post-warmup steady state: do nothing. The normal floors stay at
+    // their bootstrap values (or whatever the last-warmup-step wrote).
+    if (remaining < 0.0f) {
+        return;
+    }
+
+    // Read configured durations + override / normal values.
+    const float warmup_steps = isv[RL_REGIME_TRANSITION_STEPS_CONFIG_INDEX];
+    const float decay_steps  = isv[RL_REGIME_TRANSITION_DECAY_STEPS_CONFIG_INDEX];
+
+    const float kelly_def    = isv[RL_EVAL_KELLY_SAFETY_DEFENSIVE_INDEX];
+    const float tau_def      = isv[RL_EVAL_IQN_TAU_MIN_DEFENSIVE_INDEX];
+    const float entropy_def  = isv[RL_EVAL_ENTROPY_COEF_MIN_DEFENSIVE_INDEX];
+    const float ppo_def      = isv[RL_EVAL_PPO_CLIP_EPS_MIN_DEFENSIVE_INDEX];
+
+    const float kelly_norm   = isv[RL_EVAL_KELLY_SAFETY_NORMAL_INDEX];
+    const float tau_norm     = isv[RL_EVAL_IQN_TAU_MIN_NORMAL_INDEX];
+    const float entropy_norm = isv[RL_EVAL_ENTROPY_COEF_MIN_NORMAL_INDEX];
+    const float ppo_norm     = isv[RL_EVAL_PPO_CLIP_EPS_MIN_NORMAL_INDEX];
+
+    // Phase selection:
+    //   pure warmup       remaining > decay_steps       → blend = 1.0 (full defensive)
+    //   decay phase       0 < remaining ≤ decay_steps   → blend = remaining/decay_steps
+    //   final boundary    remaining == 0                → blend = 0.0 (full normal)
+    float blend;
+    if (remaining > decay_steps) {
+        blend = 1.0f;
+    } else if (decay_steps > 0.0f) {
+        blend = remaining / decay_steps;  // 1.0 → 0.0 as remaining → 0
+    } else {
+        // Defensive: decay_steps configured to 0 means no decay phase.
+        blend = (remaining > 0.0f) ? 1.0f : 0.0f;
+    }
+
+    // Linear interpolation: blend × defensive + (1−blend) × normal.
+    isv[RL_KELLY_SAFETY_FRAC_INDEX] = blend * kelly_def   + (1.0f - blend) * kelly_norm;
+    isv[RL_IQN_ACTION_TAU_MIN_INDEX] = blend * tau_def    + (1.0f - blend) * tau_norm;
+    isv[RL_ENTROPY_COEF_MIN_INDEX]   = blend * entropy_def + (1.0f - blend) * entropy_norm;
+    isv[RL_PPO_CLIP_EPS_MIN_INDEX]   = blend * ppo_def    + (1.0f - blend) * ppo_norm;
+
+    // Decrement counter for next step. When it crosses 0, the next step
+    // sees remaining = -1 and returns early (controllers run unimpeded).
+    isv[RL_REGIME_TRANSITION_REMAINING_INDEX] = remaining - 1.0f;
+    // Spec note: warmup_steps is used only by the trainer to set the
+    // initial counter value; this kernel reads warmup_steps only to make
+    // the `remaining > decay_steps` comparison meaningful for non-default
+    // configurations (e.g., shorter warmup with same decay).
+    (void) warmup_steps;
+}

crates/ml-alpha/cuda/rl_frd_gate.cu

@@ -35,6 +35,15 @@
 #define RL_FRD_GATE_FIRED_COUNT_INDEX  518
 #define RL_GATE_WARMUP_STEPS_INDEX    524
 #define RL_STEP_COUNTER_ISV_INDEX     548
+// Phase 7b F5 (2026-06-05) Option A — interop with state-conditional
+// action availability mask. When F5 master gate (slot 823) is engaged
+// AND position is flat, F5 has DELIBERATELY forced the agent into an
+// opening action by masking Hold (and other invalid actions) in
+// pi_logits. Overriding that back to Hold here neutralizes F5's
+// surfer→trend choice-set forcing and prevents F5-G1 from achieving
+// `hold_frac_flat == 0`. The suppression is gated on F5-engaged AND
+// flat — in-position safety overrides are preserved verbatim.
+#define RL_F5_STATE_MASK_ENABLED_INDEX 823
 
 extern "C" __global__ void rl_frd_gate(
     int*                 __restrict__ actions,      // [B] IN/OUT
@@ -60,6 +69,15 @@ extern "C" __global__ void rl_frd_gate(
     const int position_lots = *(const int*)(pos_state + b * pos_bytes);
     if (position_lots != 0) return;
 
+    // Phase 7b F5 (2026-06-05) Option A — short-circuit before quality
+    // computation when F5 is engaged and we are flat. F5 has masked
+    // Hold in pi_logits so the sampled opening is deliberate; overriding
+    // here would neutralize F5-G1 (`hold_frac_flat == 0` from flat).
+    // The early `position_lots != 0 → return` above already restricts
+    // us to flat, so checking the F5 master gate alone is sufficient.
+    const bool f5_engaged = (isv[RL_F5_STATE_MASK_ENABLED_INDEX] > 0.5f);
+    if (f5_engaged) return;
+
     // Horizon 2 logits for this batch.
     const float* h2 = frd_logits + b * (FRD_N_HORIZONS * FRD_N_ATOMS) + FRD_H2_OFFSET;
 

crates/ml-alpha/cuda/rl_fused_controllers.cu

@@ -1,21 +1,29 @@
-// rl_fused_controllers.cu — single-kernel fusion of 10 RL ISV controllers.
+// rl_fused_controllers.cu — single-kernel fusion of 13 RL ISV controllers.
 //
-// Eliminates 9 kernel-launch overheads (~40-80μs/step) by running all
+// Eliminates 12 kernel-launch overheads (~55-100μs/step) by running all
 // controllers sequentially in one thread. Each controller's logic is
-// copied verbatim from its standalone .cu file. The standalone files
-// are retained for documentation and individual testing.
+// MIRRORED from its standalone .cu file (post-2026-05-30 adaptive
+// controller-floor + risk-management refactors): adaptive noise floor
+// derived from Welford variance, asymmetric Schulman patience counters,
+// ISV-driven clamp bounds + Wiener-α floor. Per `feedback_no_partial_refactor`
+// and the "fused kernel must be semantically equivalent to running all
+// individual controllers in sequence" contract, every branch below matches
+// its standalone counterpart's ISV reads, math, and counter semantics.
 //
 // Controllers fused (in execution order):
 //   1. rl_gamma_controller           ISV[400] ← ISV[input_slots[0]]
 //   2. rl_target_tau_controller      ISV[401] ← ISV[input_slots[1]]
 //   3. rl_ppo_clip_controller        ISV[402] ← ISV[input_slots[2]]
 //   4. rl_entropy_coef_controller    ISV[403] ← ISV[input_slots[3]]
-//   5. rl_rollout_steps_controller   ISV[404] ← ISV[input_slots[4]]
+//   5. rl_rollout_steps_controller   ISV[404] ← ISV[input_slots[4]]  (caller passes ADV_VAR_PRE_NORM=612)
 //   6. rl_per_alpha_controller       ISV[405] ← ISV[input_slots[5]]
 //   7. rl_reward_scale_controller    ISV[406] ← ISV[input_slots[6]]
 //   8. rl_ppo_ratio_clamp_controller ISV[440] ← ISV[402] (reads ε just written)
 //   9. rl_gate_threshold_controller  ISV[512,516,517] ← dones[B]
 //  10. rl_q_distill_lambda_controller ISV[486] ← ISV[488]
+//  11. rl_iqn_action_tau_controller   ISV[671] ← ISV[662]  (Layer 2, spec 2026-05-30-adaptive-risk-management)
+//  12. rl_inventory_beta_controller   ISV[674] ← ISV[675,614]  (Layer 3)
+//  13. rl_kelly_fraction_controller   ISV[676] ← ISV[677,678,679,680,681,660]  (Layer 4)
 //
 // Per `feedback_no_atomicadd`: single thread, no atomics.
 // Per `feedback_cpu_is_read_only`: all state in ISV, no host roundtrip.
@@ -24,65 +32,116 @@
 
 // ═══════════════════════════════════════════════════════════════════════
 // ISV slot indices — mirrored from individual controller headers.
+// All MIN/MAX/threshold/rate constants are ISV-resident per the 2026-05-30
+// adaptive controller-floor design. The few remaining `#define`s below are
+// architectural exemptions (physics/math constants, structural safeguards).
 // ═══════════════════════════════════════════════════════════════════════
 
-// --- 1. Gamma controller ---
+// --- Output slots (controller emits) ---
 #define RL_GAMMA_INDEX                     400
-#define GAMMA_MIN                          0.995f
-#define GAMMA_MAX                          0.999f
+#define RL_TARGET_TAU_INDEX                401
+#define RL_PPO_CLIP_INDEX                  402
+#define RL_ENTROPY_COEF_INDEX              403
+#define RL_N_ROLLOUT_STEPS_INDEX           404
+#define RL_PER_ALPHA_INDEX                 405
+#define RL_REWARD_SCALE_INDEX              406
+#define RL_PPO_RATIO_CLAMP_MAX_INDEX       440
+#define RL_Q_DISTILL_LAMBDA_INDEX          486
+
+// --- 1. Gamma controller (Special G) ---
+// γ MIN now adaptive via RL_GAMMA_MIN_ADAPTIVE_INDEX (slot 613) derived
+// from the Welford mean of trade duration. γ MAX is ISV-resident.
+#define RL_GAMMA_MAX_INDEX                 649
+#define RL_GAMMA_MIN_ADAPTIVE_INDEX        613
+#define RL_TRADE_DUR_VAR_COUNT_INDEX       608
+// Reward-floor fix (2026-05-30 follow-up): track REAL cumulative closed
+// trades via dones-sum accumulation. The Welford trade-duration counter
+// increments per closed-trade STEP, not per closed trade — at b=1024 with
+// ~7 dones/step this released the floor after only ~700 actual trades.
+#define RL_CUMULATIVE_DONES_INDEX          660
+#define RL_MIN_TRADES_FOR_RELEASE_INDEX    661
+// Monotonic 0→1 latch (2026-05-31 eval-boundary addendum). Set ONCE when
+// cumulative_dones first crosses min_trades; persists across reset_session_state
+// (NEVER reset). Replaces the prior `(cumulative_dones < min_trades)` test in
+// reward_scale's boot_floor gate so the floor doesn't re-fire at fold boundaries
+// when cumulative_dones is reset for Kelly's predictive-warmup purpose.
+#define RL_REWARD_SCALE_CONTROLLER_WARMED_FLAG_INDEX  716
+#define RL_TRADE_DUR_VAR_MEAN_INDEX        609
+#define RL_MEAN_TRADE_DURATION_EMA_INDEX   417
+#define GAMMA_MIN_ABSOLUTE                 0.9f      // architectural: don't degenerate to bandit
+#define HORIZON_MULTIPLIER                 2.0f      // architectural: effective horizon = 2× transaction horizon
+#define WELFORD_WARMUP_OBS                 100.0f    // architectural: confidence threshold, not magnitude calibration
+#define HORIZON_FLOOR                      10.0f     // architectural: `1/d` numerical-stability floor
 
 // --- 2. Target tau controller ---
-#define RL_TARGET_TAU_INDEX                401
-#define TAU_MIN                            0.001f
+#define RL_TARGET_TAU_MIN_INDEX            642
 #define RL_TARGET_TAU_MAX_INDEX            573
 #define RL_TAU_BOOTSTRAP_INDEX             473
 #define RL_DIV_TARGET_INDEX                457
-#define DIV_NOISE_FLOOR_FRAC               0.01f
+#define RL_Q_DIV_VAR_COUNT_INDEX           592
+#define RL_Q_DIV_VAR_M2_INDEX              594
+#define RL_Q_DIV_BELOW_COUNT_INDEX         595
 
-// --- 3. PPO clip controller ---
-#define RL_PPO_CLIP_INDEX                  402
-#define EPS_MIN                            0.05f
-#define EPS_MAX                            0.5f
+// --- 3. PPO clip controller (canonical pattern) ---
+#define RL_PPO_CLIP_EPS_MIN_INDEX          640
+#define RL_PPO_CLIP_EPS_MAX_INDEX          641
 #define RL_EPS_BOOTSTRAP_INDEX             474
 #define RL_KL_TARGET_INDEX                 454
-#define KL_NOISE_FLOOR_FRAC                0.01f
+#define RL_KL_PI_VAR_COUNT_INDEX           588
+#define RL_KL_PI_VAR_M2_INDEX              590
+#define RL_KL_PI_BELOW_COUNT_INDEX         591
 
 // --- 4. Entropy coef controller ---
-#define RL_ENTROPY_COEF_INDEX              403
-#define N_ACTIONS                          11
-#define COEF_MIN                           0.0f
-#define COEF_MAX                           0.5f
+#define N_ACTIONS                          11        // architectural: matches Q head / action space dim
+#define RL_ENTROPY_COEF_MIN_INDEX          645
+#define RL_ENTROPY_COEF_MAX_INDEX          646
 #define RL_ENTROPY_TARGET_FRAC_INDEX       458
+#define RL_ENTROPY_OBS_VAR_COUNT_INDEX     600
+#define RL_ENTROPY_OBS_VAR_M2_INDEX        602
+#define RL_ENTROPY_OBS_BELOW_COUNT_INDEX   603
 
 // --- 5. Rollout steps controller ---
-#define RL_N_ROLLOUT_STEPS_INDEX           404
-#define ROLLOUT_MIN                        256.0f
-#define ROLLOUT_MAX                        8192.0f
+// Input slot is now RL_ADV_VAR_PRE_NORM_INDEX=612 (caller-supplied via
+// input_slots[4]) since post-Phase-4.5 advantage variance is definitionally
+// near-zero and useless. See `rl_rollout_steps_controller.cu` comments.
+#define RL_ROLLOUT_MIN_INDEX               643
+#define RL_ROLLOUT_MAX_INDEX               644
 #define RL_ROLLOUT_BOOTSTRAP_INDEX         475
 #define RL_ADV_VAR_RATIO_TARGET_INDEX      449
-#define ADV_VAR_RATIO_NOISE_FLOOR_FRAC     0.01f
+#define RL_ADV_VAR_VAR_COUNT_INDEX         596
+#define RL_ADV_VAR_VAR_M2_INDEX            598
+#define RL_ADV_VAR_BELOW_COUNT_INDEX       599
 
 // --- 6. PER alpha controller ---
-#define RL_PER_ALPHA_INDEX                 405
-#define PER_ALPHA_MIN                      0.3f
-#define PER_ALPHA_MAX                      1.0f
+#define RL_PER_ALPHA_MIN_INDEX             647
+#define RL_PER_ALPHA_MAX_INDEX             648
 #define RL_KURT_GAUSSIAN_INDEX             471
 #define RL_KURT_NOISE_FLOOR_INDEX          472
 #define RL_KURT_LIFT_SCALE_INDEX           459
+#define RL_TD_KURT_VAR_COUNT_INDEX         604
+#define RL_TD_KURT_VAR_M2_INDEX            606
+#define RL_TD_KURT_BELOW_COUNT_INDEX       607
 
-// --- 7. Reward scale controller ---
-#define RL_REWARD_SCALE_INDEX              406
+// --- 7. Reward scale controller (Special R) ---
 #define RL_REWARD_SCALE_MIN_INDEX          492
-#define REWARD_SCALE_MAX                   1e3f
 #define RL_REWARD_SCALE_BOOTSTRAP_INDEX    476
-#define EPS_PNL                            1e-3f
+#define RL_REWARD_MAGNITUDE_EMA_INDEX      614
+#define EPS_PNL                            1e-3f     // architectural: div-by-zero guard
+#define REWARD_SCALE_MAX                   1e3f      // architectural: 5-order-of-magnitude runaway guard
+#define BOOTSTRAP_FRACTION_FLOOR           0.1f      // architectural: early-training spiral guard (spec §Special R)
+#define MIN_TRADES_FOR_RELEASE             100.0f    // architectural: confidence threshold for releasing bootstrap floor
+#define ASYM_DECREASE_RATE                 1.05f     // architectural: asymmetric per-step decrease cap
 
 // --- 8. PPO ratio clamp controller ---
-#define RL_PPO_RATIO_CLAMP_MAX_INDEX       440
-#define RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX 477
-#define RL_PPO_CLAMP_MARGIN_INDEX          460
-#define PPO_RATIO_CLAMP_MIN_OUT            2.0f
-#define PPO_RATIO_CLAMP_MAX_OUT            1000.0f
+// MIN_OUT now adaptive from observed ratio variance; MAX_OUT is ISV-resident.
+#define RL_PPO_RATIO_CLAMP_MAX_ADAPTIVE_INDEX 629
+#define RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX    477
+#define RL_PPO_CLAMP_MARGIN_INDEX             460
+#define RL_PPO_RATIO_VAR_COUNT_INDEX          630
+#define RL_PPO_RATIO_VAR_M2_INDEX             632
+#define PPO_RATIO_MIN_ABSOLUTE                2.0f   // architectural exemption: vanilla-PG safeguard
+#define PPO_RATIO_MIN_STD_SCALE               3.0f   // architectural: 3σ healthy-update coverage
+#define PPO_RATIO_MAX_OVER_MIN_FACTOR         5.0f   // architectural: ensure max ≥ 5× min
 
 // --- 9. Gate threshold controller ---
 #define RL_CONF_GATE_THRESHOLD_INDEX       512
@@ -96,27 +155,73 @@
 #define RL_GATE_FRD_MIN_INDEX              529
 #define RL_GATE_FRD_MAX_INDEX              530
 #define RL_GATE_ADJUST_RATE_INDEX          531
+#define RL_GATE_EMA_ALPHA_INDEX            638
 
-// --- 10. Q distill lambda controller ---
-#define RL_Q_DISTILL_LAMBDA_INDEX          486
+// --- 10. Q distill lambda controller (Special Q) ---
 #define RL_Q_DISTILL_KL_EMA_INDEX          488
 #define RL_Q_DISTILL_KL_TARGET_INDEX       491
-#define MIN_LAMBDA                         0.05f
-#define MAX_LAMBDA                         1.0f
-#define KL_TOLERANCE                       3.0f
-#define LAMBDA_RAMP_RATE                   1.2f
-#define LAMBDA_DECAY_RATE                  0.998f
+#define RL_Q_DISTILL_KL_VAR_COUNT_INDEX    618
+#define RL_Q_DISTILL_KL_VAR_M2_INDEX       620
+#define RL_Q_DISTILL_LAMBDA_MIN_ADAPTIVE_INDEX 639
+#define RL_Q_DISTILL_LAMBDA_MAX_INDEX      650
+#define RL_Q_DISTILL_KL_TOLERANCE_INDEX    651
+#define RL_Q_DISTILL_LAMBDA_RAMP_RATE_INDEX  652
+#define RL_Q_DISTILL_LAMBDA_DECAY_RATE_INDEX 653
+#define ADAPTIVE_MIN_ABSOLUTE              0.001f    // architectural: q_distill_lambda safety floor
+#define ADAPTIVE_MIN_STD_SCALE             0.05f    // architectural: signal-noise proportional scale
 
 // --- Shared Schulman params ---
 #define RL_SCHULMAN_TOLERANCE_INDEX        468
 #define RL_SCHULMAN_ADJUST_RATE_INDEX      469
 
-// --- Shared Wiener ---
-#define WIENER_ALPHA_FLOOR                 0.4f
+// --- Shared adaptive-floor constants (spec 2026-05-30) ---
+#define NOISE_FLOOR_TARGET_FRAC            0.5f      // floor ≥ 50% of target
+#define NOISE_FLOOR_STD_MULTIPLIER         2.0f      // floor ≥ 2σ of observed signal
+#define WIDEN_PATIENCE_CONSECUTIVE         3.0f      // widen/descend requires N below-band steps
+
+// --- Shared Wiener-α floor ---
+#define RL_WIENER_ALPHA_FLOOR_INDEX        659
 
 // --- Step counter (device-resident) ---
 #define RL_STEP_COUNTER_ISV_INDEX          548
 
+// ═══════════════════════════════════════════════════════════════════════
+// Adaptive risk management — spec 2026-05-30-adaptive-risk-management.
+// Layers 2/3/4 controllers fused below. Layer 1 (CMDP gates) runs as a
+// separate kernel because it needs per-step `realized_pnl` + `outcome`
+// arrays not available here. Layer D (trail factors) is read-only ISV.
+// ═══════════════════════════════════════════════════════════════════════
+
+// --- 11. Layer 2: IQN action τ controller ---
+#define RL_SESSION_PNL_USD_INDEX                  662
+#define RL_IQN_ACTION_TAU_INDEX                   671
+#define RL_IQN_ACTION_TAU_MIN_INDEX               672
+#define RL_IQN_ACTION_TAU_DD_SENSITIVITY_INDEX    673
+#define RL_REGIME_TAIL_EVENT_RECENCY_INDEX        701
+#define RL_IQN_TAU_TAIL_BOOST_FACTOR_INDEX        711
+#define RL_IQN_TAU_TAIL_BOOST_N_WINDOW_INDEX      712
+#define DEFAULT_STARTING_CAPITAL_USD              35000.0f
+
+// --- 12. Layer 3: Inventory β controller ---
+#define RL_INVENTORY_PENALTY_BETA_INDEX           674
+#define RL_INVENTORY_VARIANCE_EMA_INDEX           675
+// (RL_REWARD_MAGNITUDE_EMA_INDEX 614 already defined above)
+#define BETA_TARGET_FRAC_OF_REWARD                0.01f
+#define BETA_SIGMA_MULTIPLIER                     2.0f
+
+// --- 13. Layer 4: Kelly fraction controller ---
+#define RL_KELLY_FRACTION_INDEX                   676
+#define RL_WIN_RATE_EMA_INDEX                     677
+#define RL_AVG_WIN_USD_EMA_INDEX                  678
+#define RL_AVG_LOSS_USD_EMA_INDEX                 679
+#define RL_KELLY_SAFETY_FRAC_INDEX                680
+#define RL_KELLY_MIN_TRADES_FOR_RELEASE_INDEX     681
+#define RL_KELLY_BOOTSTRAP_FLOOR_INDEX            720  // B-3 fractional-trust floor
+// (RL_CUMULATIVE_DONES_INDEX 660 already defined above)
+#define RL_REGIME_DEAD_ZONE_FLAG_INDEX            696
+#define RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX    698
+#define RL_KELLY_EPS_RECOVERY_LIVE_INDEX          706
+
 
 // ═══════════════════════════════════════════════════════════════════════
 // Fused kernel: all 10 controllers in one launch.
@@ -126,7 +231,7 @@
 //   [1] = RL_Q_DIVERGENCE_EMA_INDEX        (418) — target_tau
 //   [2] = RL_KL_PI_EMA_INDEX               (419) — ppo_clip
 //   [3] = RL_ENTROPY_OBSERVED_EMA_INDEX     (420) — entropy_coef
-//   [4] = RL_ADVANTAGE_VAR_RATIO_EMA_INDEX  (421) — rollout_steps
+//   [4] = RL_ADV_VAR_PRE_NORM_INDEX         (612) — rollout_steps (post-Phase-4.5)
 //   [5] = RL_TD_KURTOSIS_EMA_INDEX          (422) — per_alpha
 //   [6] = RL_MEAN_ABS_PNL_EMA_INDEX         (423) — reward_scale
 // ═══════════════════════════════════════════════════════════════════════
@@ -140,29 +245,44 @@ extern "C" __global__ void rl_fused_controllers(
     if (threadIdx.x != 0 || blockIdx.x != 0) return;
 
     const int current_step = (int)isv[RL_STEP_COUNTER_ISV_INDEX];
+    const float wiener_floor = isv[RL_WIENER_ALPHA_FLOOR_INDEX];
 
     // ═══════════════════════════════════════════════════════════════════
-    // 1. Gamma controller → ISV[400]
+    // 1. Gamma controller → ISV[400]  (Special G)
     // ═══════════════════════════════════════════════════════════════════
     {
         const float gamma_prev = isv[RL_GAMMA_INDEX];
+
+        // Adaptive GAMMA_MIN: Welford mean of trade duration after warmup,
+        // EMA before warmup. See rl_gamma_controller.cu Special case G.
+        const float d_welford_count = isv[RL_TRADE_DUR_VAR_COUNT_INDEX];
+        const float d_welford_mean  = isv[RL_TRADE_DUR_VAR_MEAN_INDEX];
+        const float d_smoothed = (d_welford_count >= WELFORD_WARMUP_OBS)
+            ? d_welford_mean
+            : isv[RL_MEAN_TRADE_DURATION_EMA_INDEX];
+        const float adaptive_min = fmaxf(GAMMA_MIN_ABSOLUTE,
+                                          1.0f - 1.0f / fmaxf(d_smoothed * HORIZON_MULTIPLIER,
+                                                              HORIZON_FLOOR));
+        isv[RL_GAMMA_MIN_ADAPTIVE_INDEX] = adaptive_min;
+
         const float mean_trade_duration_events = isv[input_slots[0]];
         const float d            = fmaxf(mean_trade_duration_events, 1.0f);
+        const float gamma_max    = isv[RL_GAMMA_MAX_INDEX];
         float       gamma_target = powf(0.5f, 1.0f / d);
-        gamma_target = fmaxf(GAMMA_MIN, fminf(gamma_target, GAMMA_MAX));
+        gamma_target = fmaxf(adaptive_min, fminf(gamma_target, gamma_max));
 
         if (gamma_prev == 0.0f) {
             isv[RL_GAMMA_INDEX] = gamma_target;
         } else {
-            const float a         = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+            const float a         = fmaxf(alpha, wiener_floor);
             float       gamma_new = (1.0f - a) * gamma_prev + a * gamma_target;
-            gamma_new = fmaxf(GAMMA_MIN, fminf(gamma_new, GAMMA_MAX));
+            gamma_new = fmaxf(adaptive_min, fminf(gamma_new, gamma_max));
             isv[RL_GAMMA_INDEX] = gamma_new;
         }
     }
 
     // ═══════════════════════════════════════════════════════════════════
-    // 2. Target tau controller → ISV[401]
+    // 2. Target tau controller → ISV[401]  (canonical pattern)
     // ═══════════════════════════════════════════════════════════════════
     {
         const float tau_prev = isv[RL_TARGET_TAU_INDEX];
@@ -172,28 +292,44 @@ extern "C" __global__ void rl_fused_controllers(
             const float q_divergence_norm = isv[input_slots[1]];
             if (q_divergence_norm != 0.0f) {
                 const float div_target = isv[RL_DIV_TARGET_INDEX];
-                const float div_noise_floor = div_target * DIV_NOISE_FLOOR_FRAC;
+
+                // Adaptive noise floor — signal-driven via Welford variance.
+                const float div_count = isv[RL_Q_DIV_VAR_COUNT_INDEX];
+                const float div_var = (div_count > 1.0f)
+                    ? isv[RL_Q_DIV_VAR_M2_INDEX] / (div_count - 1.0f)
+                    : 0.0f;
+                const float div_std = sqrtf(div_var);
+                const float div_noise_floor = fmaxf(div_target * NOISE_FLOOR_TARGET_FRAC,
+                                                     div_std * NOISE_FLOOR_STD_MULTIPLIER);
+
                 if (q_divergence_norm >= div_noise_floor) {
-                    float ratio;
+                    // Asymmetric Schulman: raise τ on single observation,
+                    // lower τ requires N consecutive below-band observations.
                     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
                     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
+                    float ratio;
                     if (q_divergence_norm > div_target * tolerance) {
                         ratio = adjust_rate;
+                        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = 0.0f;
                     } else if (q_divergence_norm < div_target / tolerance) {
-                        ratio = 1.0f / adjust_rate;
+                        const float new_count = isv[RL_Q_DIV_BELOW_COUNT_INDEX] + 1.0f;
+                        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = new_count;
+                        ratio = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? (1.0f / adjust_rate) : 1.0f;
                     } else {
+                        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = 0.0f;
                         ratio = 1.0f;
                     }
                     float tau_target = tau_prev * ratio;
-                                        const float tau_max_isv = isv[RL_TARGET_TAU_MAX_INDEX];
-                    tau_target = fmaxf(TAU_MIN, fminf(tau_target, tau_max_isv));
+                    const float tau_min = isv[RL_TARGET_TAU_MIN_INDEX];
+                    const float tau_max = isv[RL_TARGET_TAU_MAX_INDEX];
+                    tau_target = fmaxf(tau_min, fminf(tau_target, tau_max));
 
                     if (tau_prev == isv[RL_TAU_BOOTSTRAP_INDEX]) {
                         isv[RL_TARGET_TAU_INDEX] = tau_target;
                     } else {
-                        const float a       = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                        const float a       = fmaxf(alpha, wiener_floor);
                         float       tau_new = (1.0f - a) * tau_prev + a * tau_target;
-                                                tau_new = fmaxf(TAU_MIN, fminf(tau_new, tau_max_isv));
+                        tau_new = fmaxf(tau_min, fminf(tau_new, tau_max));
                         isv[RL_TARGET_TAU_INDEX] = tau_new;
                     }
                 }
@@ -202,7 +338,7 @@ extern "C" __global__ void rl_fused_controllers(
     }
 
     // ═══════════════════════════════════════════════════════════════════
-    // 3. PPO clip controller → ISV[402]
+    // 3. PPO clip controller → ISV[402]  (canonical pattern — reference)
     // ═══════════════════════════════════════════════════════════════════
     {
         const float eps_prev = isv[RL_PPO_CLIP_INDEX];
@@ -212,27 +348,44 @@ extern "C" __global__ void rl_fused_controllers(
             const float kl_ema = isv[input_slots[2]];
             if (kl_ema != 0.0f) {
                 const float kl_target = isv[RL_KL_TARGET_INDEX];
-                const float kl_noise_floor = kl_target * KL_NOISE_FLOOR_FRAC;
+
+                // Adaptive noise floor — signal-driven via Welford variance.
+                const float kl_count = isv[RL_KL_PI_VAR_COUNT_INDEX];
+                const float kl_var = (kl_count > 1.0f)
+                    ? isv[RL_KL_PI_VAR_M2_INDEX] / (kl_count - 1.0f)
+                    : 0.0f;
+                const float kl_std = sqrtf(kl_var);
+                const float kl_noise_floor = fmaxf(kl_target * NOISE_FLOOR_TARGET_FRAC,
+                                                    kl_std * NOISE_FLOOR_STD_MULTIPLIER);
+
                 if (kl_ema >= kl_noise_floor) {
+                    // Asymmetric Schulman: tighten on single observation,
+                    // widen requires N consecutive below-band observations.
                     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
                     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
                     float ratio;
                     if (kl_ema > kl_target * tolerance) {
                         ratio = 1.0f / adjust_rate;
+                        isv[RL_KL_PI_BELOW_COUNT_INDEX] = 0.0f;
                     } else if (kl_ema < kl_target / tolerance) {
-                        ratio = adjust_rate;
+                        const float new_count = isv[RL_KL_PI_BELOW_COUNT_INDEX] + 1.0f;
+                        isv[RL_KL_PI_BELOW_COUNT_INDEX] = new_count;
+                        ratio = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? adjust_rate : 1.0f;
                     } else {
+                        isv[RL_KL_PI_BELOW_COUNT_INDEX] = 0.0f;
                         ratio = 1.0f;
                     }
+                    const float eps_min = isv[RL_PPO_CLIP_EPS_MIN_INDEX];
+                    const float eps_max = isv[RL_PPO_CLIP_EPS_MAX_INDEX];
                     float eps_target = eps_prev * ratio;
-                    eps_target = fmaxf(EPS_MIN, fminf(eps_target, EPS_MAX));
+                    eps_target = fmaxf(eps_min, fminf(eps_target, eps_max));
 
                     if (eps_prev == isv[RL_EPS_BOOTSTRAP_INDEX]) {
                         isv[RL_PPO_CLIP_INDEX] = eps_target;
                     } else {
-                        const float a       = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                        const float a       = fmaxf(alpha, wiener_floor);
                         float       eps_new = (1.0f - a) * eps_prev + a * eps_target;
-                        eps_new = fmaxf(EPS_MIN, fminf(eps_new, EPS_MAX));
+                        eps_new = fmaxf(eps_min, fminf(eps_new, eps_max));
                         isv[RL_PPO_CLIP_INDEX] = eps_new;
                     }
                 }
@@ -242,6 +395,8 @@ extern "C" __global__ void rl_fused_controllers(
 
     // ═══════════════════════════════════════════════════════════════════
     // 4. Entropy coef controller → ISV[403]
+    //    Asymmetric: raise coef on single below-floor observation,
+    //    drop coef requires N consecutive above-band observations.
     // ═══════════════════════════════════════════════════════════════════
     {
         const float coef_prev = isv[RL_ENTROPY_COEF_INDEX];
@@ -249,26 +404,57 @@ extern "C" __global__ void rl_fused_controllers(
         const float h_max       = logf((float)N_ACTIONS);
         const float target_frac = isv[RL_ENTROPY_TARGET_FRAC_INDEX];
         const float h_target    = target_frac * h_max;
-        const float COEF_FLOOR  = 0.01f;
+        const float COEF_FLOOR  = 0.01f;  // architectural: maintenance pressure baseline
+        const float coef_min    = isv[RL_ENTROPY_COEF_MIN_INDEX];
+        const float coef_max    = isv[RL_ENTROPY_COEF_MAX_INDEX];
         const float deficit_frac = fmaxf(0.0f,
             fminf((h_target - entropy_observed_ema) / fmaxf(h_target, 1e-6f), 1.0f));
-        float coef_target = COEF_FLOOR + (COEF_MAX - COEF_FLOOR) * deficit_frac;
-        coef_target = fmaxf(COEF_MIN, fminf(coef_target, COEF_MAX));
+        float coef_target = COEF_FLOOR + (coef_max - COEF_FLOOR) * deficit_frac;
+        coef_target = fmaxf(coef_min, fminf(coef_target, coef_max));
 
         if (coef_prev == 0.0f) {
             isv[RL_ENTROPY_COEF_INDEX] = coef_target;
-        } else if (entropy_observed_ema < h_target * 0.5f && entropy_observed_ema > 0.0f) {
-            isv[RL_ENTROPY_COEF_INDEX] = coef_target;
         } else {
-            const float a        = fmaxf(alpha, WIENER_ALPHA_FLOOR);
-            float       coef_new = (1.0f - a) * coef_prev + a * coef_target;
-            coef_new = fmaxf(COEF_MIN, fminf(coef_new, COEF_MAX));
-            isv[RL_ENTROPY_COEF_INDEX] = coef_new;
+            // Adaptive emergency floor (signal-driven via Welford variance).
+            const float h_count = isv[RL_ENTROPY_OBS_VAR_COUNT_INDEX];
+            const float h_var = (h_count > 1.0f)
+                ? isv[RL_ENTROPY_OBS_VAR_M2_INDEX] / (h_count - 1.0f)
+                : 0.0f;
+            const float h_std = sqrtf(h_var);
+            const float emergency_floor = fmaxf(h_target * NOISE_FLOOR_TARGET_FRAC,
+                                                 h_target - h_std * NOISE_FLOOR_STD_MULTIPLIER);
+
+            if (entropy_observed_ema > 0.0f && entropy_observed_ema < emergency_floor) {
+                // Single-observation emergency raise; reset patience.
+                isv[RL_ENTROPY_COEF_INDEX] = coef_target;
+                isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = 0.0f;
+            } else {
+                const float tolerance = isv[RL_SCHULMAN_TOLERANCE_INDEX];
+                const float a         = fmaxf(alpha, wiener_floor);
+                float       coef_new  = (1.0f - a) * coef_prev + a * coef_target;
+                coef_new = fmaxf(coef_min, fminf(coef_new, coef_max));
+
+                if (coef_new < coef_prev && entropy_observed_ema > h_target * tolerance) {
+                    // Healthy-entropy descent direction — require N consecutive observations
+                    // before letting Wiener drag coef downward.
+                    const float new_count = isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] + 1.0f;
+                    isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = new_count;
+                    if (new_count < WIDEN_PATIENCE_CONSECUTIVE) {
+                        isv[RL_ENTROPY_COEF_INDEX] = coef_prev;
+                    } else {
+                        isv[RL_ENTROPY_COEF_INDEX] = coef_new;
+                    }
+                } else {
+                    isv[RL_ENTROPY_OBS_BELOW_COUNT_INDEX] = 0.0f;
+                    isv[RL_ENTROPY_COEF_INDEX] = coef_new;
+                }
+            }
         }
     }
 
     // ═══════════════════════════════════════════════════════════════════
     // 5. Rollout steps controller → ISV[404]
+    //    Input now is RL_ADV_VAR_PRE_NORM_INDEX=612 (caller via input_slots[4]).
     // ═══════════════════════════════════════════════════════════════════
     {
         const float prev = isv[RL_N_ROLLOUT_STEPS_INDEX];
@@ -278,28 +464,44 @@ extern "C" __global__ void rl_fused_controllers(
             const float advantage_var_over_abs_mean = isv[input_slots[4]];
             if (advantage_var_over_abs_mean != 0.0f) {
                 const float adv_var_target = isv[RL_ADV_VAR_RATIO_TARGET_INDEX];
-                const float adv_var_noise_floor =
-                    adv_var_target * ADV_VAR_RATIO_NOISE_FLOOR_FRAC;
+
+                // Adaptive noise floor — signal-driven via Welford variance.
+                const float adv_count = isv[RL_ADV_VAR_VAR_COUNT_INDEX];
+                const float adv_var = (adv_count > 1.0f)
+                    ? isv[RL_ADV_VAR_VAR_M2_INDEX] / (adv_count - 1.0f)
+                    : 0.0f;
+                const float adv_std = sqrtf(adv_var);
+                const float adv_var_noise_floor = fmaxf(adv_var_target * NOISE_FLOOR_TARGET_FRAC,
+                                                         adv_std * NOISE_FLOOR_STD_MULTIPLIER);
+
                 if (advantage_var_over_abs_mean >= adv_var_noise_floor) {
+                    // Asymmetric Schulman: widen rollout on single above-band observation,
+                    // shrink requires N consecutive below-band observations.
                     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
                     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
                     float scale;
                     if (advantage_var_over_abs_mean > adv_var_target * tolerance) {
                         scale = adjust_rate;
+                        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = 0.0f;
                     } else if (advantage_var_over_abs_mean < adv_var_target / tolerance) {
-                        scale = 1.0f / adjust_rate;
+                        const float new_count = isv[RL_ADV_VAR_BELOW_COUNT_INDEX] + 1.0f;
+                        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = new_count;
+                        scale = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? (1.0f / adjust_rate) : 1.0f;
                     } else {
+                        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = 0.0f;
                         scale = 1.0f;
                     }
+                    const float rollout_min = isv[RL_ROLLOUT_MIN_INDEX];
+                    const float rollout_max = isv[RL_ROLLOUT_MAX_INDEX];
                     float target = prev * scale;
-                    target = fmaxf(ROLLOUT_MIN, fminf(target, ROLLOUT_MAX));
+                    target = fmaxf(rollout_min, fminf(target, rollout_max));
 
                     if (prev == isv[RL_ROLLOUT_BOOTSTRAP_INDEX]) {
                         isv[RL_N_ROLLOUT_STEPS_INDEX] = target;
                     } else {
-                        const float a   = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                        const float a   = fmaxf(alpha, wiener_floor);
                         float       out = (1.0f - a) * prev + a * target;
-                        out = fmaxf(ROLLOUT_MIN, fminf(out, ROLLOUT_MAX));
+                        out = fmaxf(rollout_min, fminf(out, rollout_max));
                         isv[RL_N_ROLLOUT_STEPS_INDEX] = out;
                     }
                 }
@@ -309,35 +511,90 @@ extern "C" __global__ void rl_fused_controllers(
 
     // ═══════════════════════════════════════════════════════════════════
     // 6. PER alpha controller → ISV[405]
+    //    Asymmetric Schulman patience on descent direction (light tails).
     // ═══════════════════════════════════════════════════════════════════
     {
         const float prev = isv[RL_PER_ALPHA_INDEX];
         const float td_kurtosis_ema = isv[input_slots[5]];
 
-        if (td_kurtosis_ema > 0.0f && td_kurtosis_ema < isv[RL_KURT_NOISE_FLOOR_INDEX]) {
+        // Adaptive noise floor: combines absolute ISV floor with Welford-derived
+        // adaptive component (std-scaled).
+        const float kurt_count = isv[RL_TD_KURT_VAR_COUNT_INDEX];
+        const float kurt_var = (kurt_count > 1.0f)
+            ? isv[RL_TD_KURT_VAR_M2_INDEX] / (kurt_count - 1.0f)
+            : 0.0f;
+        const float kurt_std = sqrtf(kurt_var);
+        const float adaptive_noise_floor = fmaxf(isv[RL_KURT_NOISE_FLOOR_INDEX],
+                                                  kurt_std * NOISE_FLOOR_STD_MULTIPLIER);
+
+        // Hold-at-prev when signal present but below adaptive noise floor
+        // (matches standalone semantics: cold-start prev==0 takes the
+        // bootstrap path below, otherwise return).
+        if (td_kurtosis_ema > 0.0f && td_kurtosis_ema < adaptive_noise_floor) {
             if (prev != 0.0f) goto per_alpha_done;
         }
 
         {
+            const float per_alpha_min = isv[RL_PER_ALPHA_MIN_INDEX];
+            const float per_alpha_max = isv[RL_PER_ALPHA_MAX_INDEX];
             const float kurt_excess = fmaxf(0.0f, td_kurtosis_ema - isv[RL_KURT_GAUSSIAN_INDEX]);
             const float kurt_lift_scale = isv[RL_KURT_LIFT_SCALE_INDEX];
             float       target      = 0.4f + 0.2f * (kurt_excess / kurt_lift_scale);
-            target = fmaxf(PER_ALPHA_MIN, fminf(target, PER_ALPHA_MAX));
+            target = fmaxf(per_alpha_min, fminf(target, per_alpha_max));
 
             if (prev == 0.0f) {
                 isv[RL_PER_ALPHA_INDEX] = target;
             } else {
-                const float a   = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                const float a   = fmaxf(alpha, wiener_floor);
                 float       out = (1.0f - a) * prev + a * target;
-                out = fmaxf(PER_ALPHA_MIN, fminf(out, PER_ALPHA_MAX));
-                isv[RL_PER_ALPHA_INDEX] = out;
+                out = fmaxf(per_alpha_min, fminf(out, per_alpha_max));
+
+                // Asymmetric Schulman patience on the DESCENT direction:
+                // α rises on a single above-band observation, falls only
+                // after N consecutive below-band observations.
+                const float kurt_gaussian = isv[RL_KURT_GAUSSIAN_INDEX];
+                const float tolerance     = isv[RL_SCHULMAN_TOLERANCE_INDEX];
+                if (out < prev && td_kurtosis_ema < kurt_gaussian / tolerance) {
+                    const float new_count = isv[RL_TD_KURT_BELOW_COUNT_INDEX] + 1.0f;
+                    isv[RL_TD_KURT_BELOW_COUNT_INDEX] = new_count;
+                    if (new_count < WIDEN_PATIENCE_CONSECUTIVE) {
+                        isv[RL_PER_ALPHA_INDEX] = prev;
+                    } else {
+                        isv[RL_PER_ALPHA_INDEX] = out;
+                    }
+                } else {
+                    isv[RL_TD_KURT_BELOW_COUNT_INDEX] = 0.0f;
+                    isv[RL_PER_ALPHA_INDEX] = out;
+                }
             }
         }
         per_alpha_done:;
     }
 
     // ═══════════════════════════════════════════════════════════════════
-    // 7. Reward scale controller → ISV[406]
+    // 7a. Cumulative dones accumulator → ISV[660]  (reward-floor-fix follow-up)
+    //
+    // Sums `dones[b]` across this step's batch and accumulates into the
+    // cumulative-closed-trades slot. Used by the reward_scale bootstrap-
+    // floor gate below. Replaces the prior `RL_TRADE_DUR_VAR_COUNT_INDEX`
+    // gate which counted closed-trade STEPS (not closed trades) and
+    // released the floor ~100× too early in real-trade terms.
+    //
+    // Per `feedback_no_atomicadd`: single-thread sum-and-write — no atomic
+    // needed since the fused kernel is single-thread / single-block.
+    // ═══════════════════════════════════════════════════════════════════
+    {
+        float dones_this_step = 0.0f;
+        for (int b = 0; b < b_size; b++) {
+            dones_this_step += dones[b];
+        }
+        isv[RL_CUMULATIVE_DONES_INDEX] = isv[RL_CUMULATIVE_DONES_INDEX] + dones_this_step;
+    }
+
+    // ═══════════════════════════════════════════════════════════════════
+    // 7. Reward scale controller → ISV[406]  (Special R)
+    //    Asymmetric per-step decrease cap (5%) + bootstrap-fraction floor
+    //    (10% of bootstrap) until N=100 closed trades.
     // ═══════════════════════════════════════════════════════════════════
     {
         const float prev = isv[RL_REWARD_SCALE_INDEX];
@@ -346,23 +603,67 @@ extern "C" __global__ void rl_fused_controllers(
         } else {
             const float mean_abs_pnl_ema = isv[input_slots[6]];
             if (mean_abs_pnl_ema != 0.0f) {
+                // Emit per-batch pnl magnitude EMA to the public slot for
+                // downstream Welford-variance kernel consumption.
+                isv[RL_REWARD_MAGNITUDE_EMA_INDEX] = mean_abs_pnl_ema;
+
                 const float denom  = fmaxf(mean_abs_pnl_ema, EPS_PNL);
                 float       target = 1.0f / denom;
                 const float scale_min = isv[RL_REWARD_SCALE_MIN_INDEX];
                 target = fmaxf(scale_min, fminf(target, REWARD_SCALE_MAX));
 
-                if (prev == isv[RL_REWARD_SCALE_BOOTSTRAP_INDEX]) {
-                    isv[RL_REWARD_SCALE_INDEX] = target;
+                // Bootstrap-fraction floor: at COLD START, scale cannot drop below
+                // 10% of bootstrap until the controller has demonstrated it can adapt
+                // to real PnL magnitudes (i.e. cumulative_dones first crosses min_trades).
+                // After that one-time warmup, the floor relaxes to scale_min permanently.
+                //
+                // Audit 2026-05-31 (eval-boundary addendum): the prior test
+                // `(cumulative_dones < min_trades)` fired spuriously at every fold
+                // boundary because `reset_session_state` zeroes cumulative_dones to
+                // re-enter Kelly's predictive-safety warmup. The boot_floor's intent
+                // is "is this the cold-start regime where scale could crash before any
+                // trade ground truth?" — NOT "have we accumulated trades in the current
+                // session?". Decouple via a persistent latch (slot 716): set once when
+                // cumulative_dones FIRST crosses min_trades, never reset. Past that
+                // point the floor stays at scale_min regardless of session resets.
+                const float trade_count  = isv[RL_CUMULATIVE_DONES_INDEX];
+                const float min_trades   = isv[RL_MIN_TRADES_FOR_RELEASE_INDEX];
+                const float warmed_flag  = isv[RL_REWARD_SCALE_CONTROLLER_WARMED_FLAG_INDEX];
+                const float boot         = isv[RL_REWARD_SCALE_BOOTSTRAP_INDEX];
+                const float boot_floor   = (warmed_flag == 0.0f)
+                    ? boot * BOOTSTRAP_FRACTION_FLOOR
+                    : scale_min;
+                // Latch the warmed flag exactly once when cumulative_dones first
+                // crosses the threshold. Monotonic 0→1 — never cleared by any path.
+                if (warmed_flag == 0.0f && trade_count >= min_trades) {
+                    isv[RL_REWARD_SCALE_CONTROLLER_WARMED_FLAG_INDEX] = 1.0f;
+                }
+
+                if (prev == boot) {
+                    // First-observation replace-directly with asymmetric DECREASE
+                    // rate-limit applied (per spec §Special R bullet (a)).
+                    float first = target;
+                    if (first < prev) {
+                        first = fmaxf(first, prev / ASYM_DECREASE_RATE);
+                    }
+                    first = fmaxf(boot_floor, fminf(first, REWARD_SCALE_MAX));
+                    isv[RL_REWARD_SCALE_INDEX] = first;
                 } else {
-                    const float a   = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                    const float a   = fmaxf(alpha, wiener_floor);
                     float       out = (1.0f - a) * prev + a * target;
 
-                    // Per-step ±2% movement clamp.
+                    // Per-step ±2% symmetric movement clamp.
                     const float max_move = prev * 1.02f;
                     const float min_move = prev * 0.98f;
                     out = fmaxf(min_move, fminf(out, max_move));
 
-                    out = fmaxf(scale_min, fminf(out, REWARD_SCALE_MAX));
+                    // Asymmetric DECREASE rate limit (belt-and-braces — documents
+                    // the controller invariant even if 2% symmetric clamp relaxes).
+                    if (out < prev) {
+                        out = fmaxf(out, prev / ASYM_DECREASE_RATE);
+                    }
+
+                    out = fmaxf(boot_floor, fminf(out, REWARD_SCALE_MAX));
                     isv[RL_REWARD_SCALE_INDEX] = out;
                 }
             }
@@ -372,6 +673,7 @@ extern "C" __global__ void rl_fused_controllers(
     // ═══════════════════════════════════════════════════════════════════
     // 8. PPO ratio clamp controller → ISV[440]
     //    Reads ε from ISV[402] which was just written above.
+    //    MIN_OUT adaptive from observed ratio variance; MAX_OUT ISV-driven.
     // ═══════════════════════════════════════════════════════════════════
     {
         const float prev = isv[RL_PPO_RATIO_CLAMP_MAX_INDEX];
@@ -381,16 +683,26 @@ extern "C" __global__ void rl_fused_controllers(
             const float eps          = isv[RL_PPO_CLIP_INDEX];
             const float clamp_margin = isv[RL_PPO_CLAMP_MARGIN_INDEX];
             float       target       = (1.0f + eps) * clamp_margin;
-            target = fmaxf(PPO_RATIO_CLAMP_MIN_OUT,
-                           fminf(target, PPO_RATIO_CLAMP_MAX_OUT));
+
+            // Adaptive MIN/MAX from observed log-ratio variance.
+            const float ratio_count = isv[RL_PPO_RATIO_VAR_COUNT_INDEX];
+            const float ratio_var = (ratio_count > 1.0f)
+                ? isv[RL_PPO_RATIO_VAR_M2_INDEX] / (ratio_count - 1.0f)
+                : 0.0f;
+            const float ratio_std = sqrtf(ratio_var);
+            const float adaptive_min = fmaxf(PPO_RATIO_MIN_ABSOLUTE,
+                                              1.0f + ratio_std * PPO_RATIO_MIN_STD_SCALE);
+            const float adaptive_max = fmaxf(adaptive_min * PPO_RATIO_MAX_OVER_MIN_FACTOR,
+                                              isv[RL_PPO_RATIO_CLAMP_MAX_ADAPTIVE_INDEX]);
+
+            target = fmaxf(adaptive_min, fminf(target, adaptive_max));
 
             if (prev == isv[RL_PPO_RATIO_CLAMP_BOOTSTRAP_INDEX]) {
                 isv[RL_PPO_RATIO_CLAMP_MAX_INDEX] = target;
             } else {
-                const float a   = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+                const float a   = fmaxf(alpha, wiener_floor);
                 float       out = (1.0f - a) * prev + a * target;
-                out = fmaxf(PPO_RATIO_CLAMP_MIN_OUT,
-                            fminf(out, PPO_RATIO_CLAMP_MAX_OUT));
+                out = fmaxf(adaptive_min, fminf(out, adaptive_max));
                 isv[RL_PPO_RATIO_CLAMP_MAX_INDEX] = out;
             }
         }
@@ -399,7 +711,7 @@ extern "C" __global__ void rl_fused_controllers(
     // ═══════════════════════════════════════════════════════════════════
     // 9. Gate threshold controller → ISV[512,516,517]
     //    Scans dones[B] to compute done_rate EMA → ISV[525].
-    //    Adjusts conf + FRD thresholds via Schulman bounded step.
+    //    EMA-α is now ISV-resident (slot 638) per spec §Group B Task 13.
     // ═══════════════════════════════════════════════════════════════════
     {
         const int warmup = (int)isv[RL_GATE_WARMUP_STEPS_INDEX];
@@ -409,7 +721,7 @@ extern "C" __global__ void rl_fused_controllers(
                 if (dones[b] > 0.5f) done_count += 1.0f;
             }
             const float done_rate = done_count / (float)b_size;
-            const float gate_alpha = 0.01f;
+            const float gate_alpha = isv[RL_GATE_EMA_ALPHA_INDEX];
             const float prev_ema = isv[RL_GATE_DONES_EMA_INDEX];
             const float dones_ema = (prev_ema == 0.0f && done_rate > 0.0f)
                 ? done_rate
@@ -445,8 +757,9 @@ extern "C" __global__ void rl_fused_controllers(
     }
 
     // ═══════════════════════════════════════════════════════════════════
-    // 10. Q→π distill lambda controller → ISV[486]
-    //     Asymmetric bounded step on KL_EMA vs target.
+    // 10. Q→π distill lambda controller → ISV[486]  (Special Q)
+    //     Adaptive MIN from Welford-var of q_distill_kl_ema; MAX + rates
+    //     ISV-driven (slots 650/651/652/653).
     // ═══════════════════════════════════════════════════════════════════
     {
         const float kl_observed = isv[RL_Q_DISTILL_KL_EMA_INDEX];
@@ -454,16 +767,134 @@ extern "C" __global__ void rl_fused_controllers(
         float       lambda      = isv[RL_Q_DISTILL_LAMBDA_INDEX];
 
         if (kl_observed > 0.0f && kl_target > 0.0f && lambda > 0.0f) {
-            const float upper = kl_target * KL_TOLERANCE;
-            const float lower = kl_target / KL_TOLERANCE;
+            // Adaptive MIN: max(0.001, sqrt(var) × 0.05).
+            const float kl_var_count = isv[RL_Q_DISTILL_KL_VAR_COUNT_INDEX];
+            const float kl_var = (kl_var_count > 1.0f)
+                ? isv[RL_Q_DISTILL_KL_VAR_M2_INDEX] / (kl_var_count - 1.0f)
+                : 0.0f;
+            const float kl_std = sqrtf(kl_var);
+            const float adaptive_min = fmaxf(ADAPTIVE_MIN_ABSOLUTE,
+                                              kl_std * ADAPTIVE_MIN_STD_SCALE);
+            isv[RL_Q_DISTILL_LAMBDA_MIN_ADAPTIVE_INDEX] = adaptive_min;
+
+            const float max_lambda        = isv[RL_Q_DISTILL_LAMBDA_MAX_INDEX];
+            const float kl_tolerance      = isv[RL_Q_DISTILL_KL_TOLERANCE_INDEX];
+            const float lambda_ramp_rate  = isv[RL_Q_DISTILL_LAMBDA_RAMP_RATE_INDEX];
+            const float lambda_decay_rate = isv[RL_Q_DISTILL_LAMBDA_DECAY_RATE_INDEX];
+
+            const float upper = kl_target * kl_tolerance;
+            const float lower = kl_target / kl_tolerance;
 
             if (kl_observed > upper) {
-                lambda = fminf(MAX_LAMBDA, lambda * LAMBDA_RAMP_RATE);
+                lambda = fminf(max_lambda, lambda * lambda_ramp_rate);
             } else if (kl_observed < lower) {
-                lambda = fmaxf(MIN_LAMBDA, lambda * LAMBDA_DECAY_RATE);
+                lambda = fmaxf(adaptive_min, lambda * lambda_decay_rate);
             }
 
             isv[RL_Q_DISTILL_LAMBDA_INDEX] = lambda;
         }
     }
+
+    // ═══════════════════════════════════════════════════════════════════
+    // 11. Layer 2 — IQN action τ controller → ISV[671]
+    //     τ = clamp(τ_min, 0.5 - sensitivity × drawdown_frac, 1.0)
+    //     drawdown_frac = max(0, -session_pnl) / starting_capital
+    // ═══════════════════════════════════════════════════════════════════
+    {
+        const float session_pnl   = isv[RL_SESSION_PNL_USD_INDEX];
+        const float drawdown_usd  = fmaxf(0.0f, -session_pnl);
+        const float drawdown_frac = drawdown_usd / DEFAULT_STARTING_CAPITAL_USD;
+
+        const float tau_min     = isv[RL_IQN_ACTION_TAU_MIN_INDEX];
+        const float sensitivity = isv[RL_IQN_ACTION_TAU_DD_SENSITIVITY_INDEX];
+        float       tau_action  = 0.5f - sensitivity * drawdown_frac;
+        tau_action = fmaxf(tau_min, fminf(tau_action, 1.0f));
+
+        // Tail-recency τ_min boost (defense in depth, F5 / spec v3)
+        const float recency     = isv[RL_REGIME_TAIL_EVENT_RECENCY_INDEX];
+        const float tail_window = isv[RL_IQN_TAU_TAIL_BOOST_N_WINDOW_INDEX];
+        const float boost       = isv[RL_IQN_TAU_TAIL_BOOST_FACTOR_INDEX];
+
+        float tau_min_eff = tau_min;
+        if (recency < tail_window) {
+            tau_min_eff *= boost;
+        }
+        tau_action = fmaxf(tau_action, tau_min_eff);
+
+        isv[RL_IQN_ACTION_TAU_INDEX] = tau_action;
+    }
+
+    // ═══════════════════════════════════════════════════════════════════
+    // 12. Layer 3 — Inventory β controller → ISV[674]
+    //     β_target = 0.01 × E[|reward|] / (2 × σ_inventory)
+    //     Sentinel-zero bootstrap; Wiener-α blend with floor 0.4 after.
+    // ═══════════════════════════════════════════════════════════════════
+    {
+        const float reward_mag = isv[RL_REWARD_MAGNITUDE_EMA_INDEX];
+        const float inv_var    = isv[RL_INVENTORY_VARIANCE_EMA_INDEX];
+        if (inv_var > 0.0f && reward_mag > 0.0f) {
+            const float inv_std     = sqrtf(inv_var);
+            const float beta_target = BETA_TARGET_FRAC_OF_REWARD * reward_mag
+                                    / (BETA_SIGMA_MULTIPLIER * inv_std);
+            const float prev = isv[RL_INVENTORY_PENALTY_BETA_INDEX];
+            if (prev == 0.0f) {
+                isv[RL_INVENTORY_PENALTY_BETA_INDEX] = beta_target;
+            } else {
+                const float a = fmaxf(alpha, wiener_floor);
+                isv[RL_INVENTORY_PENALTY_BETA_INDEX] =
+                    (1.0f - a) * prev + a * beta_target;
+            }
+        }
+    }
+
+    // ═══════════════════════════════════════════════════════════════════
+    // 13. Layer 4 — Kelly fraction controller → ISV[676]
+    //     B-3 fractional-trust schedule (2026-05-31):
+    //       trust(n) = max(f_floor, min(1, n/N_full))
+    //       f_safe   = max(f_floor·safety, f_kelly · trust · safety)
+    //     Replaces binary warmup gate which forced f=1.0 (max sizing) at
+    //     every fold boundary (4xmxm eval[1] → 53% positions → -$100M).
+    //     Math: Hoeffding ε(n=200) ≈ 0.10 → N_full=200 gives 10% precision.
+    //     f_floor=0.05 prevents Kelly trade-stream death.
+    // ═══════════════════════════════════════════════════════════════════
+    {
+        const float p        = isv[RL_WIN_RATE_EMA_INDEX];
+        const float avg_win  = isv[RL_AVG_WIN_USD_EMA_INDEX];
+        const float avg_loss = isv[RL_AVG_LOSS_USD_EMA_INDEX];
+        const float safety   = isv[RL_KELLY_SAFETY_FRAC_INDEX];
+
+        const float n_trades = isv[RL_CUMULATIVE_DONES_INDEX];
+        const float n_full   = isv[RL_KELLY_MIN_TRADES_FOR_RELEASE_INDEX];
+        const float f_floor  = isv[RL_KELLY_BOOTSTRAP_FLOOR_INDEX];
+        const float trust    = (n_full > 0.0f)
+            ? fmaxf(f_floor, fminf(1.0f, n_trades / n_full))
+            : 1.0f;
+
+        if (avg_loss <= 0.0f || avg_win <= 0.0f) {
+            // Dead-signal: trust × safety floor keeps trades flowing.
+            isv[RL_KELLY_FRACTION_INDEX] = fmaxf(0.0f, fminf(trust * safety, 1.0f));
+        } else {
+            const float b_ratio = avg_win / avg_loss;
+            const float q       = 1.0f - p;
+            const float f_kelly = (p * b_ratio - q) / b_ratio;
+            const float f_raw   = f_kelly * trust * safety;
+            const float f_min   = f_floor * safety;
+            float       f       = fmaxf(f_min, f_raw);
+            f = fmaxf(0.0f, fminf(f, 1.0f));
+            isv[RL_KELLY_FRACTION_INDEX] = f;
+        }
+
+        // Kelly resurrection (Theorem 1): override analytic kelly if DEAD_ZONE_FLAG fires.
+        //
+        // Two safety checks:
+        //   1. DEAD_ZONE_TIMEOUT_FLAG: if dead-zone has persisted > MAX_DURATION steps,
+        //      stop trying to resurrect (let kelly stay at 0; halt the bleed).
+        //      The trainer monitors TIMEOUT_FLAG as a halt-training signal.
+        //   2. Otherwise: kelly_f overridden with ε_recovery_live (computed by regime_observer).
+        const int dead_zone = (int)isv[RL_REGIME_DEAD_ZONE_FLAG_INDEX];
+        const int timeout   = (int)isv[RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX];
+        if (dead_zone && !timeout) {
+            isv[RL_KELLY_FRACTION_INDEX] = isv[RL_KELLY_EPS_RECOVERY_LIVE_INDEX];
+        }
+    }
 }

crates/ml-alpha/cuda/rl_fused_reward_pipeline.cu

@@ -39,6 +39,33 @@
 #define RL_SHORT_HOLD_PENALTY_INDEX        534
 #define RL_HOLD_BONUS_INDEX                535
 #define RL_OUTCOME_ALPHA_INDEX             520
+// Layer 3 (inventory penalty — spec 2026-05-30-adaptive-risk-management).
+#define RL_INVENTORY_PENALTY_BETA_INDEX    674
+// Adaptive surfer-scaffold shaping (spec v5 2026-06-01 §6).
+// w ∈ [0, 1] multiplies the Phase 5 shaping contribution:
+//   w = 1 → full shaping (surfer-baseline dd049d9a4 path)
+//   w = 0 → pure realized_pnl_delta reward
+//   0<w<1 → smooth interpolation
+// Driven by rl_surfer_scaffold_controller (reads wr_ema + cumulative
+// dones + edge_decay_frac_alerted; fades w as agent crosses break-even).
+#define RL_SURFER_SCAFFOLD_WEIGHT_INDEX    753
+
+// Phase 3D-B (2026-06-03): quadratic-in-trade-size impact-aware cost
+// (Cao et al. 2026 arXiv:2603.29086). cost = α·|Δlots| + β·(Δlots)²
+// applied per env step in Phase 1.5 BETWEEN realized_pnl_delta (Phase 1)
+// and surfer-scaffold shaping (Phase 5). Disabled when gate slot is ≤ 0.5.
+#define RL_QUADRATIC_COST_ALPHA_INDEX      794
+#define RL_QUADRATIC_COST_BETA_INDEX       795
+#define RL_QUADRATIC_COST_ENABLED_INDEX    796
+
+// Phase 5 (2026-06-04) MTM reward — per-step reward proportional to
+// total-wealth delta (realized + unrealized). Breaks the bimodal
+// Hold+TrailLoosen pathology where held losers emit zero reward
+// regardless of how badly they're going. With MTM enabled every step
+// underwater contributes negative reward → Q learns held losers are
+// costly → policy prefers to close earlier.
+#define RL_MTM_REWARD_ENABLED_INDEX        815
+#define RL_MTM_REWARD_WEIGHT_INDEX         816
 
 #define MAX_UNITS 4
 
@@ -71,6 +98,16 @@ extern "C" __global__ void rl_fused_reward_pipeline(
     float*    __restrict__ reward_abs,           // [B] OUT
     float*    __restrict__ raw_rewards,          // [B] OUT
     float*    __restrict__ outcome_ema,          // [B] IN/OUT
+    // --- Phase 5 (2026-06-04) MTM reward ---
+    // bid/ask top-of-book — to compute mid_price for unrealized PnL.
+    // Single shared book across batches (the GPU LobSim uses a per-batch
+    // book; bid_px/ask_px are the [BOOK_LEVELS]-arrays for batch 0
+    // only — but at b=1024 the LobSim runs the SAME book across batches
+    // per its design, see lobsim_cuda.cu). Caller passes the head
+    // pointer; the kernel reads bid_px[0], ask_px[0].
+    const float* __restrict__ bid_px,            // [BOOK_LEVELS]
+    const float* __restrict__ ask_px,            // [BOOK_LEVELS]
+    float*    __restrict__ prev_unrealized_pnl,  // [B] IN/OUT
     float*    __restrict__ isv,
     int       b_size,
     int       pos_bytes
@@ -99,6 +136,83 @@ extern "C" __global__ void rl_fused_reward_pipeline(
     rewards[b] = reward;
     dones[b]   = done;
 
+    // ================================================================
+    // PHASE 1.5 (Phase 3D-B, 2026-06-03): Cao et al. 2026
+    // quadratic-in-trade-size impact-aware cost.
+    //
+    // cost = α·|Δlots| + β·(Δlots)²
+    //
+    // Applied BEFORE Phase 5 shaping so the shaped-vs-raw weight w (slot
+    // 753) does not amplify or mute the cost. Discourages overtrading
+    // even when reward is pnl-aligned. Trail-stop actions (7, 8) are
+    // no-ops in actions_to_market_targets and don't change current_lots,
+    // so Δlots = 0 for those and the cost stays at 0. Hold (2) likewise
+    // produces no position change → no cost. FlatFrom* / HalfFlat* /
+    // open actions all incur position changes proportional to their
+    // size, so they pay an impact penalty scaled by the change magnitude.
+    //
+    // Reward units: pts × lots (matches realized_pnl_delta convention).
+    // Bootstrap α=0.5, β=2.0 yields: 1-lot=2.5, 4-lot flip=34, 8-lot flip=132.
+    // ================================================================
+    if (isv[RL_QUADRATIC_COST_ENABLED_INDEX] > 0.5f) {
+        const float trade_size = fabsf((float)(current_lots - prev_lots));
+        if (trade_size > 0.0f) {
+            const float alpha_cost = isv[RL_QUADRATIC_COST_ALPHA_INDEX];
+            const float beta_cost  = isv[RL_QUADRATIC_COST_BETA_INDEX];
+            const float cost = alpha_cost * trade_size
+                             + beta_cost  * trade_size * trade_size;
+            reward    -= cost;
+            rewards[b] = reward;
+        }
+    }
+
+    // ================================================================
+    // PHASE 1.6 (Phase 5, 2026-06-04): mark-to-market reward.
+    //
+    // Reward component proportional to total-wealth delta (realized +
+    // unrealized). Without this, the agent learns to widen trails on
+    // losing positions indefinitely (TrailLoosen pathology surfaced in
+    // Phase 4-A3 smoke at 65c328d3f) because:
+    //   - close-event-only reward = 0 during holds, < 0 only at close
+    //   - TrailLoosen emits no market order → no realization → reward 0
+    //   - Q learns the arbitrage: TrailLoosen > Close on losing positions
+    //
+    // MTM fix: every step underwater emits negative reward proportional
+    // to the unrealized delta. Over a complete trade the SUMMED reward
+    // is invariant vs close-event-only (unrealized → 0 at close); only
+    // the TEMPORAL DISTRIBUTION changes — with γ < 1, held losers are
+    // visibly painful in the discounted return.
+    //
+    // unrealized_pnl = direction · (mid − vwap_entry) · |lots|
+    //   (lots is signed; direction = sign(lots); |lots| × direction = lots
+    //    so unrealized_pnl = (mid − vwap_entry) × lots — same identity
+    //    as in `rl_trade_context_update.cu` line 73 modulo `initial_r`
+    //    normalisation.)
+    //
+    // Note on units: realized_pnl from `pos_state` is in
+    // (price-points × lots) — same units as our MTM component. Mixing
+    // is unit-consistent.
+    //
+    // Determinism: pure per-thread arithmetic over per-batch buffers
+    // and a SHARED bid_px[0]/ask_px[0] read — no atomics. Equivalent
+    // to the existing `rl_trade_context_update.cu` mid computation.
+    // ================================================================
+    if (isv[RL_MTM_REWARD_ENABLED_INDEX] > 0.5f) {
+        const float w_mtm = isv[RL_MTM_REWARD_WEIGHT_INDEX];
+        const float mid = 0.5f * (bid_px[0] + ask_px[0]);
+        // current_lots is the post-fill position (set above). vwap is
+        // the post-fill VWAP — when current_lots == 0 the position is
+        // flat and unrealized must be zero (vwap may carry stale data
+        // from the close).
+        const float unrealized_now = (current_lots != 0)
+            ? (mid - vwap) * (float)current_lots
+            : 0.0f;
+        const float unrealized_prev = prev_unrealized_pnl[b];
+        reward    += w_mtm * (unrealized_now - unrealized_prev);
+        rewards[b] = reward;
+        prev_unrealized_pnl[b] = unrealized_now;
+    }
+
     // ================================================================
     // PHASE 2: rl_unit_state_update
     // ================================================================
@@ -204,8 +318,19 @@ extern "C" __global__ void rl_fused_reward_pipeline(
     reward_abs[b] = fabsf(reward);
 
     // ================================================================
-    // PHASE 5: rl_reward_shaping (surfer philosophy)
+    // PHASE 5: rl_reward_shaping (adaptive surfer-scaffold, spec v5)
     // ================================================================
+    // Adaptive scaffold weight w ∈ [0,1]: each shaping contribution is
+    // multiplied by w so the kernel smoothly interpolates between the
+    // pre-v4 surfer-baseline path (w=1) and pure pnl (w=0). Controller
+    // `rl_surfer_scaffold_controller` writes w per step from wr_ema +
+    // cumulative_dones + edge_decay_frac_alerted.
+    //
+    // LERP forms (preserve w=1 ↔ legacy shaping):
+    //   additive a:  r += w * a               (entry_cost neg, hold_bonus pos)
+    //   multiplicative m:  r *= (1 + w*(m-1)) (penalty, ride_mult)
+    const float w = fmaxf(0.0f, fminf(1.0f, isv[RL_SURFER_SCAFFOLD_WEIGHT_INDEX]));
+
     const float entry_cost = isv[RL_ENTRY_COST_INDEX];
     const float min_hold   = isv[RL_SHORT_HOLD_MIN_STEPS_INDEX];
     const float penalty    = isv[RL_SHORT_HOLD_PENALTY_INDEX];
@@ -217,23 +342,34 @@ extern "C" __global__ void rl_fused_reward_pipeline(
 
     // 1. Entry cost: flat → positioned transition.
     if (prev_lots == 0 && current_lots != 0) {
-        r -= entry_cost;
+        r -= w * entry_cost;
     }
 
     // 2. Short-hold penalty: trade close with hold time below minimum.
     if (done > 0.5f && (float)hold_time < min_hold) {
-        r *= penalty;
+        r *= (1.0f + w * (penalty - 1.0f));
     }
 
     // 3. Long-ride bonus: profitable close amplified by hold time.
     if (done > 0.5f && r > 0.0f && hold_time > 0) {
         const float ride_mult = 1.0f + hold_bonus * sqrtf((float)hold_time);
-        r *= ride_mult;
+        r *= (1.0f + w * (ride_mult - 1.0f));
     }
 
     // 4. Per-step hold bonus for staying in a profitable position.
     if (prev_lots != 0 && current_lots != 0 && r > 0.0f && hold_time > 0) {
-        r += hold_bonus * sqrtf((float)hold_time);
+        r += w * hold_bonus * sqrtf((float)hold_time);
+    }
+
+    // ================================================================
+    // PHASE 5b: Layer 3 inventory penalty (spec 2026-05-30-adaptive-risk-management).
+    // Apply BEFORE raw_rewards snapshot. β = 0 (sentinel) → no-op.
+    // Also weighted by w: Layers 1/2/4 own inventory risk when w → 0.
+    // ================================================================
+    const float inv_beta = isv[RL_INVENTORY_PENALTY_BETA_INDEX];
+    if (inv_beta > 0.0f) {
+        const float net_pos_mag = (float)((current_lots < 0) ? -current_lots : current_lots);
+        r -= w * inv_beta * net_pos_mag;
     }
 
     // Write shaped reward back.

crates/ml-alpha/cuda/rl_gamma_controller.cu

@@ -45,9 +45,35 @@
 // the policy myopic).
 
 #define RL_GAMMA_INDEX   400
-#define GAMMA_MIN        0.995f
-#define GAMMA_MAX        0.999f
-#define WIENER_ALPHA_FLOOR 0.4f
+// γ MAX clamp ceiling is now ISV-driven per the 2026-05-30 clamp-bound
+// extension. γ MIN already adaptive via RL_GAMMA_MIN_ADAPTIVE_INDEX (613).
+#define RL_GAMMA_MAX_INDEX           649
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX  659
+
+// Adaptive controller floors (spec 2026-05-30 Special case G):
+// hardcoded `GAMMA_MIN = 0.995f` replaced with an adaptive bound derived
+// from the Welford mean of trade duration. With short-horizon trade
+// regimes (d_ema = 15.6 in fold 0) the static 0.995 floor pinned gamma
+// for the entire run; adaptive bound `1 - 1/(d_smoothed × 2)` lets the
+// controller drop gamma low enough for the current regime while keeping
+// a hard `GAMMA_MIN_ABSOLUTE = 0.9` to prevent bandit-mode degenerate.
+//
+// Smoothed-duration choice: Welford mean (slot 609) is used after a
+// 100-observation warmup so the gamma↔trade_duration feedback loop is
+// damped by the natural N-smoothing of running mean. Before warmup, the
+// EMA at slot 417 is used directly (less stable but available
+// immediately at cold-start).
+#define RL_GAMMA_MIN_ADAPTIVE_INDEX        613
+#define RL_TRADE_DUR_VAR_COUNT_INDEX       608
+#define RL_TRADE_DUR_VAR_MEAN_INDEX        609
+#define RL_MEAN_TRADE_DURATION_EMA_INDEX   417
+#define GAMMA_MIN_ABSOLUTE                 0.9f
+#define HORIZON_MULTIPLIER                 2.0f
+#define WELFORD_WARMUP_OBS                 100.0f
+// Floor for `d × HORIZON_MULTIPLIER` to prevent the `1/d` term from
+// blowing up when trade duration is very small (cold start, no closes).
+#define HORIZON_FLOOR                      10.0f
 
 
 // ─────────────────────────────────────────────────────────────────────
@@ -84,6 +110,27 @@ extern "C" __global__ void rl_gamma_controller(
 
     const float gamma_prev = isv[RL_GAMMA_INDEX];
 
+    // Adaptive GAMMA_MIN (spec 2026-05-30 Special case G).
+    // Replaces hardcoded `GAMMA_MIN = 0.995f`. With d_ema = 15.6 (fold 0)
+    // the static 0.995 floor pinned γ for the entire run — the target
+    // formula `0.5^(1/d)` produces γ_target = 0.936 at d = 15.6, which
+    // clamps to 0.995 = floor and never moves. Adaptive bound
+    // `1 - 1/(d × 2)` gives γ_min ≈ 0.968 at d = 15.6 — leaving room
+    // for the controller to track the actual trade horizon.
+    //
+    // After 100 Welford observations the running mean is used (more
+    // stable than EMA against per-batch outliers); before that the EMA
+    // at slot 417 is used directly so cold-start has a usable signal.
+    const float d_welford_count = isv[RL_TRADE_DUR_VAR_COUNT_INDEX];
+    const float d_welford_mean  = isv[RL_TRADE_DUR_VAR_MEAN_INDEX];
+    const float d_smoothed = (d_welford_count >= WELFORD_WARMUP_OBS)
+        ? d_welford_mean
+        : isv[RL_MEAN_TRADE_DURATION_EMA_INDEX];
+    const float adaptive_min = fmaxf(GAMMA_MIN_ABSOLUTE,
+                                      1.0f - 1.0f / fmaxf(d_smoothed * HORIZON_MULTIPLIER,
+                                                          HORIZON_FLOOR));
+    isv[RL_GAMMA_MIN_ADAPTIVE_INDEX] = adaptive_min;
+
     // Compute target from the current input EMA. Shared between
     // bootstrap and per-step paths so the dead-zone coincidence with
     // a hardcoded bootstrap cannot recur.
@@ -91,26 +138,25 @@ extern "C" __global__ void rl_gamma_controller(
     //   single-event trade doesn't push γ to 0.5.
     const float mean_trade_duration_events = isv[input_slot];
     const float d            = fmaxf(mean_trade_duration_events, 1.0f);
+    const float gamma_max    = isv[RL_GAMMA_MAX_INDEX];
     float       gamma_target = powf(0.5f, 1.0f / d);
-    gamma_target = fmaxf(GAMMA_MIN, fminf(gamma_target, GAMMA_MAX));
+    gamma_target = fmaxf(adaptive_min, fminf(gamma_target, gamma_max));
 
     // Bootstrap on sentinel 0.0 per pearl_first_observation_bootstrap:
     // first emit replaces directly with the computed target. At cold
     // start (input EMA also sentinel-zero), clamped d=1, target=0.5,
-    // clamped to GAMMA_MIN = 0.90 (the floor). Any non-sentinel input
-    // produces target ≥ 0.90 → ≤ 0.999, distinct from the floor so
-    // the per-step Wiener blend on subsequent calls always sees a
-    // prev vs target delta.
+    // clamped to adaptive_min (≥ GAMMA_MIN_ABSOLUTE = 0.90). Any
+    // non-sentinel input produces target ≥ adaptive_min → ≤ 0.999.
     if (gamma_prev == 0.0f) {
         isv[RL_GAMMA_INDEX] = gamma_target;
         return;
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a            = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+    const float a            = fmaxf(alpha, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       gamma_new    = (1.0f - a) * gamma_prev + a * gamma_target;
 
     // Clamp into the bounded range; runaway protection.
-    gamma_new = fmaxf(GAMMA_MIN, fminf(gamma_new, GAMMA_MAX));
+    gamma_new = fmaxf(adaptive_min, fminf(gamma_new, gamma_max));
     isv[RL_GAMMA_INDEX] = gamma_new;
 }

crates/ml-alpha/cuda/rl_gate_lr_multiplier_controller.cu

@@ -0,0 +1,121 @@
+// rl_gate_lr_multiplier_controller.cu — adaptive gate-LR multiplier (B1.3).
+//
+// Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//       Phase 2A-D fix B1.3 dispatch (2026-06-03).
+//
+// Reads (from ISV):
+//   RL_POLICY_GATE_ENTROPY_MEAN_INDEX (781)             — produced per-step
+//                                                          by `multi_head_policy_aggregate_diag.cu`
+//                                                          (Phase 2A-D); mean over batches
+//                                                          of `−Σ_k p[b,k]·log p[b,k]`.
+//   RL_POLICY_GATE_ENTROPY_EMA_INDEX (791)              — EMA state; this kernel
+//                                                          owns it.
+//   RL_POLICY_GATE_CONTROLLER_BOOTSTRAP_DONE_INDEX (792) — monotonic 0→1 latch.
+//   RL_POLICY_GATE_LR_MULTIPLIER_INDEX (790)             — output, also the
+//                                                          previous-step value.
+//   RL_POLICY_NUM_HEADS_INDEX (761)                      — K (active head count),
+//                                                          drives regime-adaptive
+//                                                          entropy thresholds.
+//
+// Writes (to ISV):
+//   slot 791 — updated EMA
+//   slot 792 — bootstrap-done flag (latched to 1.0 on first observation)
+//   slot 790 — updated multiplier (clamped to [MIN_FLOOR, MAX_CEIL])
+//
+// Control law (per `pearl_dead_signal_resurrection_discipline`):
+//   • EMA Wiener-α = 0.02 (~50-step horizon) — smooths per-step noise.
+//   • Escalate +0.3 %/step (compounds to ≈+50 % over 137 steps) when
+//     `entropy_ema > 0.85·log(K)` — gate is "under-learning" / stuck
+//     near uniform.
+//   • Decay −5 %/step (emergency back-off) when
+//     `entropy_ema < 0.20·log(K)` — gate is at risk of collapse to
+//     single-head routing.
+//   • Healthy band [0.20·log(K), 0.85·log(K)]: leave multiplier alone
+//     (current value is working — no need to hunt).
+//   • Clamp to [1.0, 50.0] per `pearl_bootstrap_must_respect_clamp_range`
+//     so the bootstrap 5.0 lies strictly inside the range.
+//
+// Per `pearl_bootstrap_must_respect_clamp_range`: bootstrap 5.0 ∈ [1.0,
+// 50.0]; controller never snaps to a clamp boundary on its first signal.
+//
+// Per `pearl_welford_trade_count_is_step_not_trade`: the first-observation
+// EMA initialisation is gated by a dedicated `bootstrap_done` flag at
+// slot 792; the controller cannot rely on `prev == bootstrap` because 5.0
+// is also a valid steady-state value the controller may visit after
+// escalating from a lower point.
+//
+// Per `feedback_no_atomicadd`: single-thread launch (1×1×1), no atomics.
+// Per `feedback_cpu_is_read_only`: pure device-side; reads + writes are
+// all ISV slots.
+// Per `feedback_no_nvrtc`: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+#include <math_constants.h>
+
+// ISV slot indices (must match crates/ml-alpha/src/rl/isv_slots.rs).
+#define RL_POLICY_NUM_HEADS_INDEX                           761
+#define RL_POLICY_GATE_ENTROPY_MEAN_INDEX                   781
+#define RL_POLICY_GATE_LR_MULTIPLIER_INDEX                  790
+#define RL_POLICY_GATE_ENTROPY_EMA_INDEX                    791
+#define RL_POLICY_GATE_CONTROLLER_BOOTSTRAP_DONE_INDEX      792
+
+// Tuning constants (B1.3 design — anchored on the B1.2 dose-response).
+// All values are dimensionless ratios or rate scalars.
+#define GATE_LR_CTRL_EMA_ALPHA       0.02f   // Wiener-α — ~50-step horizon
+#define GATE_LR_CTRL_OVER_FRAC       0.85f   // multiplier of log(K) — under-learning threshold
+#define GATE_LR_CTRL_COLLAPSE_FRAC   0.20f   // multiplier of log(K) — collapse threshold
+#define GATE_LR_CTRL_ESCALATE_RATE   1.003f  // +0.3 %/step (≈+50 % in 137 steps)
+#define GATE_LR_CTRL_DECAY_RATE      0.95f   // −5 %/step (emergency back-off)
+#define GATE_LR_CTRL_MIN_FLOOR       1.0f    // never below 1× (effectively off)
+#define GATE_LR_CTRL_MAX_CEIL        50.0f   // saturation cap (B1.2 plateau ≈20×)
+
+extern "C" __global__ void rl_gate_lr_multiplier_controller(float* isv) {
+    // Single-thread kernel — launched (1,1,1)/(1,1,1).
+    if (threadIdx.x != 0 || blockIdx.x != 0) return;
+
+    const float entropy_now = isv[RL_POLICY_GATE_ENTROPY_MEAN_INDEX];
+    const float boot_done   = isv[RL_POLICY_GATE_CONTROLLER_BOOTSTRAP_DONE_INDEX];
+    const float k_active    = isv[RL_POLICY_NUM_HEADS_INDEX];
+
+    // ── EMA update (first-observation bootstrap pattern) ─────────────
+    float entropy_ema;
+    if (boot_done < 0.5f) {
+        // First call: replace EMA with current observation; latch flag.
+        // Necessary because slot 791 sentinel-zeroes at trainer init and
+        // blending zero with the first real measurement (~log(K) ≈ 1.10
+        // for K=3) would lag the controller by ~50 steps before it ever
+        // sees a representative value.
+        entropy_ema = entropy_now;
+        isv[RL_POLICY_GATE_CONTROLLER_BOOTSTRAP_DONE_INDEX] = 1.0f;
+    } else {
+        entropy_ema = (1.0f - GATE_LR_CTRL_EMA_ALPHA) * isv[RL_POLICY_GATE_ENTROPY_EMA_INDEX]
+                    + GATE_LR_CTRL_EMA_ALPHA * entropy_now;
+    }
+    isv[RL_POLICY_GATE_ENTROPY_EMA_INDEX] = entropy_ema;
+
+    // ── Regime-adaptive thresholds (scale with K) ────────────────────
+    // K ≥ 1 by construction (multi-head policy bootstraps NUM_HEADS to 3
+    // or higher in the same flag-on block); guard with fmaxf so logf is
+    // well-defined even if a future caller writes K=0 (would degenerate
+    // to single-head and the controller becomes a no-op via the healthy
+    // band → multiplier left alone, which is the right behaviour).
+    const float log_k = logf(fmaxf(k_active, 1.0f));
+    const float over_threshold     = GATE_LR_CTRL_OVER_FRAC * log_k;
+    const float collapse_threshold = GATE_LR_CTRL_COLLAPSE_FRAC * log_k;
+
+    // ── Multiplier update ─────────────────────────────────────────────
+    float multiplier = isv[RL_POLICY_GATE_LR_MULTIPLIER_INDEX];
+    if (entropy_ema > over_threshold) {
+        // Under-learning: slowly compound up.
+        multiplier *= GATE_LR_CTRL_ESCALATE_RATE;
+    } else if (entropy_ema < collapse_threshold) {
+        // Collapse risk: fast back-off.
+        multiplier *= GATE_LR_CTRL_DECAY_RATE;
+    }
+    // Healthy band — leave multiplier alone.
+
+    // Clamp; bootstrap 5.0 sits strictly inside [1.0, 50.0].
+    multiplier = fmaxf(GATE_LR_CTRL_MIN_FLOOR,
+                       fminf(multiplier, GATE_LR_CTRL_MAX_CEIL));
+    isv[RL_POLICY_GATE_LR_MULTIPLIER_INDEX] = multiplier;
+}

crates/ml-alpha/cuda/rl_gate_threshold_controller.cu

@@ -23,6 +23,12 @@
 #define RL_GATE_FRD_MAX_INDEX           530
 #define RL_GATE_ADJUST_RATE_INDEX       531
 #define RL_STEP_COUNTER_ISV_INDEX       548
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// EMA smoothing α was hardcoded 0.01f; ISV slot 638 makes it tunable
+// at runtime so the dones-rate EMA half-life can adapt to data volume
+// (e.g. small-batch smoke runs may want a faster α to surface signal
+// before warmup completes).
+#define RL_GATE_EMA_ALPHA_INDEX         638
 
 extern "C" __global__ void rl_gate_threshold_controller(
     float*       __restrict__ isv,
@@ -41,7 +47,7 @@ extern "C" __global__ void rl_gate_threshold_controller(
         if (dones[b] > 0.5f) done_count += 1.0f;
     }
     const float done_rate = done_count / (float)b_size;
-    const float alpha = 0.01f;
+    const float alpha = isv[RL_GATE_EMA_ALPHA_INDEX];
     const float prev_ema = isv[RL_GATE_DONES_EMA_INDEX];
     const float dones_ema = (prev_ema == 0.0f && done_rate > 0.0f)
         ? done_rate

crates/ml-alpha/cuda/rl_hindsight_inject.cu

@@ -27,6 +27,13 @@
 #define RL_HINDSIGHT_INJECT_COUNT_INDEX   551
 #define RL_REWARD_SCALE_INDEX             406
 
+/* Phase 3B-Y (2026-06-03): hindsight is conceptually paired with the surfer
+ * scaffold — both are training-scaffold biases on the gradient. Gate hindsight
+ * injection by slot 753 so that pure-pnl mode (scaffold_w = 0.0) also disables
+ * hindsight, eliminating the second of three contaminants identified by the
+ * Phase 3B-followup audit. */
+#define RL_SURFER_SCAFFOLD_WEIGHT_INDEX   753
+
 extern "C" __global__ void rl_hindsight_inject(
     const float* __restrict__ dones,              /* [B]             */
     const float* __restrict__ rewards_raw,        /* [B]             */
@@ -64,9 +71,16 @@ extern "C" __global__ void rl_hindsight_inject(
         float peak_pnl = (float)dir * (peak_mid[b] - entry_mid[b]);
 
         float threshold = isv[RL_HINDSIGHT_THRESHOLD_INDEX];
+        /* Phase 3B-Y: gate by surfer-scaffold weight (slot 753). When scaffold
+         * is fully faded (w = 0.0, pure-pnl mode), hindsight injection is also
+         * disabled — they are paired training scaffolds. */
+        float scaffold_w = isv[RL_SURFER_SCAFFOLD_WEIGHT_INDEX];
 
-        /* Peak PnL must exceed actual by the threshold factor AND be positive. */
-        if (peak_pnl > 0.0f && peak_pnl > actual_pnl * threshold) {
+        /* Peak PnL must exceed actual by the threshold factor AND be positive,
+         * AND the scaffold gate must be on. */
+        if (peak_pnl > 0.0f
+            && peak_pnl > actual_pnl * threshold
+            && scaffold_w > 0.5f) {
             wants_inject = 1;
         }
 

crates/ml-alpha/cuda/rl_inventory_beta_controller.cu

@@ -0,0 +1,57 @@
+// rl_inventory_beta_controller.cu — Layer 3: adaptive inventory penalty β.
+//
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Scales the inventory penalty `reward_shaped = reward_raw - β × |net_pos|`
+// so that at ~2σ inventory the penalty is ~1% of typical reward magnitude.
+//
+//   β_target = 0.01 × E[|reward|] / (2 × σ_inventory)
+//
+// Sentinel-zero bootstrap per `pearl_first_observation_bootstrap`: hold β
+// at 0 until BOTH reward magnitude EMA and inventory variance EMA have
+// real data. After bootstrap, Wiener-α blend with floor 0.4 per
+// `pearl_wiener_alpha_floor_for_nonstationary`.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: every threshold via ISV slot.
+
+#include <stdint.h>
+
+#define RL_INVENTORY_PENALTY_BETA_INDEX  674
+#define RL_INVENTORY_VARIANCE_EMA_INDEX  675
+#define RL_REWARD_MAGNITUDE_EMA_INDEX    614
+#define RL_WIENER_ALPHA_FLOOR_INDEX      659
+
+// 1% of typical reward magnitude at 2σ inventory — Avellaneda-Stoikov
+// canonical "noticeable but not dominant" calibration. Structural ratio.
+#define BETA_TARGET_FRAC_OF_REWARD 0.01f
+#define BETA_SIGMA_MULTIPLIER      2.0f
+
+extern "C" __global__ void rl_inventory_beta_controller(
+    float* __restrict__ isv
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    const float reward_mag = isv[RL_REWARD_MAGNITUDE_EMA_INDEX];
+    const float inv_var    = isv[RL_INVENTORY_VARIANCE_EMA_INDEX];
+
+    // Dead-signal hold: need real data on both inputs.
+    if (inv_var <= 0.0f || reward_mag <= 0.0f) return;
+
+    const float inv_std     = sqrtf(inv_var);
+    const float beta_target = BETA_TARGET_FRAC_OF_REWARD * reward_mag
+                            / (BETA_SIGMA_MULTIPLIER * inv_std);
+
+    const float prev    = isv[RL_INVENTORY_PENALTY_BETA_INDEX];
+    const float a_floor = isv[RL_WIENER_ALPHA_FLOOR_INDEX];
+
+    if (prev == 0.0f) {
+        // First-observation bootstrap.
+        isv[RL_INVENTORY_PENALTY_BETA_INDEX] = beta_target;
+    } else {
+        isv[RL_INVENTORY_PENALTY_BETA_INDEX] =
+            (1.0f - a_floor) * prev + a_floor * beta_target;
+    }
+}

crates/ml-alpha/cuda/rl_inventory_variance_update.cu

@@ -0,0 +1,59 @@
+// rl_inventory_variance_update.cu — Layer 3 (inventory penalty) input EMA.
+//
+// Tracks running variance of |net_position| across batches. Layer 3's β
+// controller scales the penalty so that at ~2σ inventory the penalty
+// equals ~1% of typical reward magnitude.
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Inputs:
+//   net_position_per_batch[b]  signed contracts (current_lots, i32)
+//
+// Output: ISV[RL_INVENTORY_VARIANCE_EMA_INDEX = 675]
+//
+// EMA over the batch variance of |net_position|; sentinel-zero bootstrap.
+// This is NOT a true Welford triple — we collapse the batch into a single
+// scalar (batch variance) then EMA across steps with a constant alpha.
+// The β controller treats this slot as σ² directly.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block, sums sequentially.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: Welford-EMA α is a structural
+// smoothing parameter, matching ema_update_per_step convention.
+
+#include <stdint.h>
+
+#define RL_INVENTORY_VARIANCE_EMA_INDEX 675
+#define WELFORD_ALPHA                   0.01f  // slower EMA than Kelly inputs
+
+extern "C" __global__ void rl_inventory_variance_update(
+    float*       __restrict__ isv,
+    const int*   __restrict__ net_position_per_batch,    // [b_size] signed contracts (i32)
+    int                       b_size
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    if (b_size <= 0) return;
+
+    // Compute batch mean + variance of |net_position|.
+    float sum    = 0.0f;
+    float sum_sq = 0.0f;
+    for (int b = 0; b < b_size; ++b) {
+        const int   lots = net_position_per_batch[b];
+        const float v    = (float)((lots < 0) ? -lots : lots);
+        sum    += v;
+        sum_sq += v * v;
+    }
+    const float n    = (float)b_size;
+    const float mean = sum / n;
+    const float var  = (sum_sq / n) - (mean * mean);
+    if (var < 0.0f) return;  // numerical safety: should not happen but defend
+
+    const float prev = isv[RL_INVENTORY_VARIANCE_EMA_INDEX];
+    if (prev == 0.0f) {
+        isv[RL_INVENTORY_VARIANCE_EMA_INDEX] = var;
+    } else {
+        isv[RL_INVENTORY_VARIANCE_EMA_INDEX] =
+            (1.0f - WELFORD_ALPHA) * prev + WELFORD_ALPHA * var;
+    }
+}

crates/ml-alpha/cuda/rl_iqn_action_tau_controller.cu

@@ -0,0 +1,67 @@
+// rl_iqn_action_tau_controller.cu — Layer 2: adaptive IQN action-selection τ.
+//
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Adapts the quantile used for IQN risk-averse action selection from the
+// observed session drawdown. Normal trading: τ = 0.5 (median ≈ expected-Q
+// behavior). Under drawdown: τ → τ_MIN (pessimistic, downside-aware).
+//
+//   τ_target = max(τ_min, 0.5 - sensitivity × drawdown_frac)
+//
+// Drawdown approximation: `drawdown_frac = max(0, -session_pnl) /
+// starting_capital`. Because the trainer resets session_pnl on each fold
+// boundary, this approximates "drawdown from session start". For the
+// strict "drawdown from session peak" formulation we'd need a peak-tracker
+// slot — deferred (see plan note); the current formulation is correct in
+// the dominant case where the agent is in a losing session and provides
+// the right pressure (more pessimistic action selection as losses
+// accumulate). In a strongly-winning session τ stays at 0.5.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: τ_min, sensitivity ISV-driven.
+//
+// Starting capital is the $35k single-contract ES baseline per
+// `project_ml_alpha_starting_capital`; structural constant exemption.
+
+#include <stdint.h>
+
+#define RL_SESSION_PNL_USD_INDEX                 662
+#define RL_IQN_ACTION_TAU_INDEX                  671
+#define RL_IQN_ACTION_TAU_MIN_INDEX              672
+#define RL_IQN_ACTION_TAU_DD_SENSITIVITY_INDEX   673
+#define RL_REGIME_TAIL_EVENT_RECENCY_INDEX       701
+#define RL_IQN_TAU_TAIL_BOOST_FACTOR_INDEX       711
+#define RL_IQN_TAU_TAIL_BOOST_N_WINDOW_INDEX     712
+
+#define DEFAULT_STARTING_CAPITAL_USD 35000.0f
+
+extern "C" __global__ void rl_iqn_action_tau_controller(
+    float* __restrict__ isv
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    const float session_pnl = isv[RL_SESSION_PNL_USD_INDEX];
+    // Approximate drawdown from session boundary as max(0, -session_pnl).
+    const float drawdown_usd  = fmaxf(0.0f, -session_pnl);
+    const float drawdown_frac = drawdown_usd / DEFAULT_STARTING_CAPITAL_USD;
+
+    const float tau_min     = isv[RL_IQN_ACTION_TAU_MIN_INDEX];
+    const float sensitivity = isv[RL_IQN_ACTION_TAU_DD_SENSITIVITY_INDEX];
+    float       tau_action  = 0.5f - sensitivity * drawdown_frac;
+    tau_action = fmaxf(tau_min, fminf(tau_action, 1.0f));
+
+    // Tail-recency τ_min boost (defense in depth, F5 / spec v3)
+    const float recency     = isv[RL_REGIME_TAIL_EVENT_RECENCY_INDEX];
+    const float tail_window = isv[RL_IQN_TAU_TAIL_BOOST_N_WINDOW_INDEX];
+    const float boost       = isv[RL_IQN_TAU_TAIL_BOOST_FACTOR_INDEX];
+
+    float tau_min_eff = tau_min;
+    if (recency < tail_window) {
+        tau_min_eff *= boost;
+    }
+    tau_action = fmaxf(tau_action, tau_min_eff);
+
+    isv[RL_IQN_ACTION_TAU_INDEX] = tau_action;
+}

crates/ml-alpha/cuda/rl_iqn_forward.cu

@@ -60,8 +60,34 @@ __device__ static uint32_t xorshift32_iqn(uint32_t* state) {
 //   Grid  = (B, N_TAU, 1)
 //   Block = (EMBED_DIM, 1, 1)  — one thread per embedding dimension.
 //
+// DETERMINISM (Phase 2.6, 2026-06-02): `prng_state` is now READ-ONLY
+// in this kernel. The previous version had a read-write race: all
+// N_TAU blocks per batch read `prng_state[batch]` at the head of the
+// kernel, and the (tau_idx == 0) block wrote back the advanced state
+// at the end — with NO inter-block barrier. Blocks with tau_idx > 0
+// running on a different SM could read the post-write value (if the
+// tau_idx == 0 block finished first) OR the pre-write value
+// (otherwise), depending on SM scheduling. Different runs picked
+// different orderings, producing run-dependent τ values for
+// tau_idx > 0 and hence run-dependent `iqn_q_values` even at step 0
+// (no upstream RL-loop divergence required). Diagnosed via Phase 2.6
+// `dump_backward_state_for_debug` Group H verdict (iqn_q_values
+// DIVERGE at step 0 idx 55, max|Δ|=4.5e-5) while Groups G/I/J stayed
+// EQUAL through steps 0/1 — see
+// `docs/superpowers/notes/2026-06-02-determinism-phase2.6-backward
+// -kernel-fix.md`.
+//
+// Fix: kernel now READS prng_state[batch] only (no writes); the
+// state advancement is performed by `rl_iqn_advance_prng_state`
+// in a separate single-thread-per-batch launch that runs AFTER
+// `rl_iqn_tau_cos_features` finishes via stream ordering — no race
+// possible. Per `feedback_no_atomicadd.md` + canonical Phase-2
+// PER-rebuild rule: "fixed accumulation order requires a real
+// barrier between stages, and kernel-launch ordering on a single
+// stream is the cleanest grid-wide barrier we have".
+//
 // Inputs:
-//   prng_state    [B]                       — per-batch xorshift32 seed (mutated)
+//   prng_state    [B]                       — per-batch xorshift32 seed (READ-ONLY)
 //   B                                       — batch size
 //   N_TAU                                   — number of quantile samples
 // Outputs:
@@ -69,9 +95,9 @@ __device__ static uint32_t xorshift32_iqn(uint32_t* state) {
 //   cos_features  [B*N_TAU, EMBED_DIM]     — cos((j+1) * pi * tau)
 // ─────────────────────────────────────────────────────────────────────
 extern "C" __global__ void rl_iqn_tau_cos_features(
-    uint32_t*    __restrict__ prng_state,     // [B]
-    int          B,
-    int          N_TAU,
+    const uint32_t* __restrict__ prng_state,  // [B] READ-ONLY (advanced by sibling kernel)
+    int             B,
+    int             N_TAU,
     float*       __restrict__ tau,            // [B, N_TAU]
     float*       __restrict__ cos_features    // [B*N_TAU, EMBED_DIM]
 ) {
@@ -98,13 +124,8 @@ extern "C" __global__ void rl_iqn_tau_cos_features(
 
         tau[batch * N_TAU + tau_idx] = u;
         s_tau_val = u;
-
-        if (tau_idx == 0) {
-            uint32_t adv = seed;
-            #pragma unroll
-            for (int w = 0; w < 8; ++w) xorshift32_iqn(&adv);
-            prng_state[batch] = adv;
-        }
+        // prng_state advancement moved to `rl_iqn_advance_prng_state`
+        // (see kernel below); no writes to prng_state in this kernel.
     }
     __syncthreads();
 
@@ -115,6 +136,51 @@ extern "C" __global__ void rl_iqn_tau_cos_features(
     cos_features[row * EMBED_DIM + j] = cosf((float)(j + 1) * PI_F * tau_val);
 }
 
+// ─────────────────────────────────────────────────────────────────────
+// rl_iqn_advance_prng_state:
+//   Companion to `rl_iqn_tau_cos_features` — advances the per-batch
+//   xorshift32 PRNG state by exactly 8 steps. Launched AFTER
+//   `rl_iqn_tau_cos_features` so the read-only sampling sees a stable
+//   value for prng_state[batch] across all (tau_idx) blocks, then
+//   this kernel applies a single deterministic update per batch.
+//
+// Determinism rationale: by separating "read state for tau sampling"
+// from "advance state for next call", we eliminate the read-write
+// race the previous monolithic kernel had. Both kernels run on the
+// same stream, so the launch ordering is a grid-wide barrier
+// (no __threadfence required).
+//
+// Grid  = (ceil(B/256), 1, 1)
+// Block = (256, 1, 1)        — one thread per batch element.
+//
+// Inputs:
+//   B                       — batch size
+// Outputs:
+//   prng_state [B]          — advanced 8 xorshift32 steps in place.
+//                              `0` seed bootstrap matches the
+//                              `rl_iqn_tau_cos_features` convention
+//                              `(batch + 1) * 2654435761u + 0xBEEFu`
+//                              so the first advance from the
+//                              cold-start sentinel is identical to
+//                              what the prior monolithic kernel
+//                              produced for tau_idx==0.
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void rl_iqn_advance_prng_state(
+    uint32_t*    __restrict__ prng_state,    // [B]
+    int          B
+) {
+    const int batch = blockIdx.x * blockDim.x + threadIdx.x;
+    if (batch >= B) return;
+
+    uint32_t seed = prng_state[batch];
+    if (seed == 0u) seed = (uint32_t)(batch + 1) * 2654435761u + 0xBEEFu;
+
+    uint32_t adv = seed;
+    #pragma unroll
+    for (int w = 0; w < 8; ++w) xorshift32_iqn(&adv);
+    prng_state[batch] = adv;
+}
+
 // ─────────────────────────────────────────────────────────────────────
 // rl_iqn_relu_hadamard:
 //   Stage 3: bias-add → ReLU → element-wise product with h_t.

crates/ml-alpha/cuda/rl_kelly_fraction_controller.cu

@@ -0,0 +1,102 @@
+// rl_kelly_fraction_controller.cu — Layer 4: half-Kelly position-size multiplier.
+//
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Half-Kelly (Thorp) from observed win_rate × R-multiple:
+//
+//   f_kelly = (p × b − q) / b      where p = win_rate, q = 1 − p,
+//                                  b = avg_win / avg_loss
+//   f       = clamp(safety × f_kelly, 0, 1)   where safety = 0.5 (half-Kelly)
+//
+// Warmup gate (`pearl_first_observation_bootstrap` + warmup discipline):
+// hold f at bootstrap = 1.0 until `cumulative_dones >= MIN_TRADES_FOR_RELEASE`
+// so the EMA inputs (win_rate, avg_win, avg_loss) have time to converge
+// past cold-start noise. After release, f tracks observed edge — if
+// edge is negative or zero, Kelly clamps to 0 = no commitment.
+//
+// Dead-signal guard: if avg_loss <= 0 (sentinel, no losses observed yet)
+// hold f at 1.0 — we don't have a denominator for the R-multiple.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block.
+// Per `feedback_cpu_is_read_only`: pure device kernel.
+// Per `feedback_isv_for_adaptive_bounds`: safety multiplier + warmup gate
+// are ISV-driven (slots 680, 681).
+
+#include <stdint.h>
+
+#define RL_KELLY_FRACTION_INDEX                676
+#define RL_WIN_RATE_EMA_INDEX                  677
+#define RL_AVG_WIN_USD_EMA_INDEX               678
+#define RL_AVG_LOSS_USD_EMA_INDEX              679
+#define RL_KELLY_SAFETY_FRAC_INDEX             680
+#define RL_KELLY_MIN_TRADES_FOR_RELEASE_INDEX  681
+#define RL_CUMULATIVE_DONES_INDEX              660
+#define RL_REGIME_DEAD_ZONE_FLAG_INDEX         696
+#define RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX 698
+#define RL_KELLY_EPS_RECOVERY_LIVE_INDEX       706
+// Fractional-Kelly trust floor (2026-05-31 B-3). Prevents trade-death
+// absorbing state during warmup; replaces the prior binary "f=1.0 during
+// warmup" gate that caused 53% sizing at every fold boundary.
+#define RL_KELLY_BOOTSTRAP_FLOOR_INDEX         720
+
+extern "C" __global__ void rl_kelly_fraction_controller(
+    float* __restrict__ isv
+) {
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    const float p        = isv[RL_WIN_RATE_EMA_INDEX];
+    const float avg_win  = isv[RL_AVG_WIN_USD_EMA_INDEX];
+    const float avg_loss = isv[RL_AVG_LOSS_USD_EMA_INDEX];
+    const float safety   = isv[RL_KELLY_SAFETY_FRAC_INDEX];  // typically 0.5
+
+    // ── Fractional-trust schedule (2026-05-31 B-3 fix). Math:
+    //    Hoeffding gives |p̂ − p*| ≤ √(ln(40)/(2n)) with 95% confidence.
+    //    At N_full = 200 trades: ε = √(1.844/200) ≈ 0.10 (10% Kelly precision).
+    //    Below N_full: trust(n) = max(f_floor, n/N_full) gradually opens.
+    //    f_floor=0.05 (5%) prevents Kelly trade-stream death — see
+    //    `pearl_kelly_trade_stream_death`. Replaces the prior binary gate
+    //    `if (n < N_min) kelly = 1.0` which was catastrophic at every
+    //    boundary (4xmxm eval[1]: trade_count=0 → kelly=1.0 → 53% sizing
+    //    → -$100M eval pnl).
+    const float n_trades = isv[RL_CUMULATIVE_DONES_INDEX];
+    const float n_full   = isv[RL_KELLY_MIN_TRADES_FOR_RELEASE_INDEX];
+    const float f_floor  = isv[RL_KELLY_BOOTSTRAP_FLOOR_INDEX];
+    const float trust    = (n_full > 0.0f)
+        ? fmaxf(f_floor, fminf(1.0f, n_trades / n_full))
+        : 1.0f;  // n_full=0 → trust=1 (gate disabled, for legacy configs)
+
+    // Dead-signal guards: need positive magnitudes for Kelly formula.
+    // After B-3 bootstrap (avg_win=avg_loss=1.0 in `with_controllers_bootstrapped`
+    // AND in `reset_session_state`), these branches only fire if a controller
+    // upstream zeroed them (shouldn't happen). Trust × safety provides a small
+    // positive position to keep trades flowing for the trade-stream warmup.
+    if (avg_loss <= 0.0f || avg_win <= 0.0f) {
+        isv[RL_KELLY_FRACTION_INDEX] = fmaxf(0.0f, fminf(trust * safety, 1.0f));
+        return;
+    }
+
+    const float b       = avg_win / avg_loss;
+    const float q       = 1.0f - p;
+    const float f_kelly = (p * b - q) / b;
+    // f_safe = max(f_floor·safety, f_kelly · trust · safety) — trust schedule
+    // gates aggressive Kelly during warmup; floor prevents trade-stream death.
+    const float f_raw   = f_kelly * trust * safety;
+    const float f_min   = f_floor * safety;
+    float       f       = fmaxf(f_min, f_raw);
+    f = fmaxf(0.0f, fminf(f, 1.0f));
+    isv[RL_KELLY_FRACTION_INDEX] = f;
+
+    // Kelly resurrection (Theorem 1): override analytic kelly if DEAD_ZONE_FLAG fires.
+    //
+    // Two safety checks:
+    //   1. DEAD_ZONE_TIMEOUT_FLAG: if dead-zone has persisted > MAX_DURATION steps,
+    //      stop trying to resurrect (let kelly stay at 0; halt the bleed).
+    //      The trainer monitors TIMEOUT_FLAG as a halt-training signal.
+    //   2. Otherwise: kelly_f overridden with ε_recovery_live (computed by regime_observer).
+    const int dead_zone = (int)isv[RL_REGIME_DEAD_ZONE_FLAG_INDEX];
+    const int timeout   = (int)isv[RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX];
+    if (dead_zone && !timeout) {
+        isv[RL_KELLY_FRACTION_INDEX] = isv[RL_KELLY_EPS_RECOVERY_LIVE_INDEX];
+    }
+}

crates/ml-alpha/cuda/rl_lr_from_mapped_pinned.cu

@@ -1,134 +0,0 @@
-// rl_lr_from_mapped_pinned.cu — GPU-side LR controller that reads loss
-// observations from mapped-pinned device pointers instead of host-
-// supplied scalar arguments. This eliminates the host-side loss readback
-// between the reward graph and training graph, enabling mega-graph
-// capture of the entire per-step pipeline.
-//
-// The mapped-pinned buffers (ss_q_loss_mapped, ss_pi_loss_mapped,
-// ss_v_loss_sum_mapped) have stable device pointers. The GPU writes
-// loss values during backward kernels; this kernel reads them from the
-// same physical memory via the device-side pointer. The reads are
-// coherent because this kernel launches AFTER the backward kernels on
-// the same stream (stream ordering guarantees visibility).
-//
-// Internally delegates to the same plateau_decay_head logic as
-// rl_lr_controller.cu. The only difference is the loss observation
-// source: pointer dereference instead of scalar argument.
-
-#define RL_LR_BCE_INDEX 412
-#define RL_LR_Q_INDEX   413
-#define RL_LR_PI_INDEX  414
-#define RL_LR_V_INDEX   415
-#define RL_LR_AUX_INDEX 416
-
-#define RL_LR_BOOTSTRAP_INDEX        462
-#define RL_LR_MIN_INDEX              463
-#define RL_LR_MAX_INDEX              464
-#define RL_LR_LOSS_EMA_ALPHA_INDEX   465
-#define RL_LR_DECAY_FACTOR_INDEX     466
-
-#define RL_IMPROVEMENT_THRESHOLD_INDEX 455
-#define RL_PLATEAU_PATIENCE_INDEX      456
-#define RL_LR_WARMUP_STEPS_INDEX       461
-
-__device__ __forceinline__ void plateau_decay_head(
-    float* isv,
-    int    lr_idx,
-    float  observed_loss,
-    int    loss_ema_slot,
-    int    best_slot,
-    int    counter_slot,
-    int    warmup_slot
-) {
-    const float lr_prev      = isv[lr_idx];
-    const float lr_bootstrap = isv[RL_LR_BOOTSTRAP_INDEX];
-
-    if (lr_prev == 0.0f) {
-        isv[lr_idx] = lr_bootstrap;
-        return;
-    }
-
-    if (observed_loss == 0.0f) return;
-    if (loss_ema_slot < 0) return;
-
-    const float loss_ema_prev  = isv[loss_ema_slot];
-    const float loss_ema_alpha = isv[RL_LR_LOSS_EMA_ALPHA_INDEX];
-    float loss_ema_new;
-    if (loss_ema_prev == 0.0f) {
-        loss_ema_new = observed_loss;
-    } else {
-        loss_ema_new = (1.0f - loss_ema_alpha) * loss_ema_prev
-                     + loss_ema_alpha * observed_loss;
-    }
-    isv[loss_ema_slot] = loss_ema_new;
-
-    const float warmup_prev   = isv[warmup_slot];
-    const float warmup_target = isv[RL_LR_WARMUP_STEPS_INDEX];
-    if (warmup_prev < warmup_target) {
-        isv[best_slot]    = loss_ema_new;
-        isv[counter_slot] = 0.0f;
-        isv[warmup_slot]  = warmup_prev + 1.0f;
-        return;
-    }
-
-    const float improvement_threshold = isv[RL_IMPROVEMENT_THRESHOLD_INDEX];
-    const float plateau_patience      = isv[RL_PLATEAU_PATIENCE_INDEX];
-    const float best_prev = isv[best_slot];
-
-    if (loss_ema_new < best_prev * improvement_threshold) {
-        isv[best_slot]    = loss_ema_new;
-        isv[counter_slot] = 0.0f;
-        return;
-    }
-
-    const float counter_next = isv[counter_slot] + 1.0f;
-    if (counter_next >= plateau_patience) {
-        const float lr_min       = isv[RL_LR_MIN_INDEX];
-        const float decay_factor = isv[RL_LR_DECAY_FACTOR_INDEX];
-        const float lr_new = fmaxf(lr_min, lr_prev * decay_factor);
-        isv[lr_idx]       = lr_new;
-        isv[counter_slot] = 0.0f;
-    } else {
-        isv[counter_slot] = counter_next;
-    }
-}
-
-extern "C" __global__ void rl_lr_from_mapped_pinned(
-    float*       __restrict__ isv,
-    const float* __restrict__ q_loss_ptr,     // mapped-pinned dev_ptr (1 float)
-    const float* __restrict__ pi_loss_ptr,    // mapped-pinned dev_ptr (1 float)
-    const float* __restrict__ v_loss_sum_ptr, // mapped-pinned dev_ptr (1 float)
-    int   b_size,                              // batch size for V loss normalization
-    int   q_loss_ema_slot,
-    int   q_best_slot,
-    int   q_counter_slot,
-    int   q_warmup_slot,
-    int   pi_loss_ema_slot,
-    int   pi_best_slot,
-    int   pi_counter_slot,
-    int   pi_warmup_slot,
-    int   v_loss_ema_slot,
-    int   v_best_slot,
-    int   v_counter_slot,
-    int   v_warmup_slot
-) {
-    if (threadIdx.x != 0 || blockIdx.x != 0) return;
-
-    // Read losses from mapped-pinned device pointers. These are the
-    // same physical pages the backward kernels wrote to — coherent
-    // because this kernel is stream-ordered after them.
-    const float observed_loss_q  = *q_loss_ptr;
-    const float observed_loss_pi = *pi_loss_ptr;
-    // V loss is stored as a sum across the batch; normalize to per-sample.
-    const float observed_loss_v  = (b_size > 0) ? (*v_loss_sum_ptr / (float)b_size) : 0.0f;
-
-    // BCE and AUX: perception-owned heads, pass slot=-1 to skip.
-    plateau_decay_head(isv, RL_LR_BCE_INDEX, 0.0f, -1, -1, -1, -1);
-    plateau_decay_head(isv, RL_LR_Q_INDEX, observed_loss_q,
-                       q_loss_ema_slot, q_best_slot, q_counter_slot, q_warmup_slot);
-    plateau_decay_head(isv, RL_LR_PI_INDEX, observed_loss_pi,
-                       pi_loss_ema_slot, pi_best_slot, pi_counter_slot, pi_warmup_slot);
-    plateau_decay_head(isv, RL_LR_V_INDEX, observed_loss_v,
-                       v_loss_ema_slot, v_best_slot, v_counter_slot, v_warmup_slot);
-    plateau_decay_head(isv, RL_LR_AUX_INDEX, 0.0f, -1, -1, -1, -1);
-}

crates/ml-alpha/cuda/rl_per_alpha_controller.cu

@@ -42,8 +42,10 @@
 // sampling is perfectly proportional to priority.
 
 #define RL_PER_ALPHA_INDEX 405
-#define PER_ALPHA_MIN       0.3f
-#define PER_ALPHA_MAX       1.0f
+// PER α MIN/MAX clamp bounds are now ISV-driven per the 2026-05-30
+// clamp-bound extension. Runtime-tunable + visible in diag.
+#define RL_PER_ALPHA_MIN_INDEX  647
+#define RL_PER_ALPHA_MAX_INDEX  648
 // Kurtosis of a standard normal = 3.0 ("excess kurtosis 0" with the
 // alternative convention). Used as the breakpoint above which we start
 // raising α.
@@ -52,6 +54,8 @@
 #define RL_KURT_GAUSSIAN_INDEX    471
 #define RL_KURT_NOISE_FLOOR_INDEX 472
 #define RL_KURT_LIFT_SCALE_INDEX  459
+// Schulman tolerance from the shared global slot.
+#define RL_SCHULMAN_TOLERANCE_INDEX        468
 // Noise-floor gate: if the streaming kurtosis estimator emits a value
 // below this magnitude, treat it as "no signal" (sentinel-zero proxy)
 // and hold α at the prior value. Without this, on the first few steps
@@ -62,7 +66,23 @@
 // pattern on the other controllers (per
 // pearl_multiplicative_controllers_need_bounded_step_and_noise_floor).
 // (KURT_NOISE_FLOOR — was 1.0f #define — now isv[RL_KURT_NOISE_FLOOR_INDEX])
-#define WIENER_ALPHA_FLOOR  0.4f
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX  659
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// noise floor augmented with Welford-derived adaptive component (replaces
+// reliance on the ISV-driven RL_KURT_NOISE_FLOOR_INDEX absolute floor alone).
+// Asymmetric Schulman semantics: α RISES on a single above-band kurtosis
+// observation (heavy tails = safety signal, sharpen PER fast); α FALLS only
+// after N consecutive below-band observations (light tails = patient drift).
+// Replaces the regime where the controller stuck at MIN 0.4 because every
+// step's kurtosis read landed just above the absolute floor but well below
+// the band — the Wiener blend dragged α down even on single observations.
+#define RL_TD_KURT_VAR_COUNT_INDEX         604
+#define RL_TD_KURT_VAR_M2_INDEX            606
+#define RL_TD_KURT_BELOW_COUNT_INDEX       607
+#define NOISE_FLOOR_STD_MULTIPLIER         2.0f  // floor ≥ 2σ of observed kurtosis
+#define WIDEN_PATIENCE_CONSECUTIVE         3.0f  // α descent requires N below-band steps
 
 // ─────────────────────────────────────────────────────────────────────
 // rl_per_alpha_controller:
@@ -97,12 +117,23 @@ extern "C" __global__ void rl_per_alpha_controller(
 
     const float prev = isv[RL_PER_ALPHA_INDEX];
 
-    // Noise-floor gate: kurtosis below KURT_NOISE_FLOOR is dominated
-    // by streaming-estimator startup noise (per-step batch-mean
+    // Noise-floor gate: kurtosis below the adaptive noise floor is
+    // dominated by streaming-estimator startup noise (per-step batch-mean
     // differences before tails accumulate). Hold α at prev to avoid
     // dragging toward PER_ALPHA_MIN on cold-start.
+    //
+    // Adaptive component (spec 2026-05-30): floor scales with observed
+    // kurtosis std. Replaces reliance on the absolute ISV floor alone.
+    // Welford sample variance = M² / (count − 1) when count > 1.
     const float td_kurtosis_ema = isv[input_slot];
-    if (td_kurtosis_ema > 0.0f && td_kurtosis_ema < isv[RL_KURT_NOISE_FLOOR_INDEX]) {
+    const float kurt_count = isv[RL_TD_KURT_VAR_COUNT_INDEX];
+    const float kurt_var = (kurt_count > 1.0f)
+        ? isv[RL_TD_KURT_VAR_M2_INDEX] / (kurt_count - 1.0f)
+        : 0.0f;
+    const float kurt_std = sqrtf(kurt_var);
+    const float adaptive_noise_floor = fmaxf(isv[RL_KURT_NOISE_FLOOR_INDEX],
+                                              kurt_std * NOISE_FLOOR_STD_MULTIPLIER);
+    if (td_kurtosis_ema > 0.0f && td_kurtosis_ema < adaptive_noise_floor) {
         // Real signal present but below the noise floor — hold prev.
         // (Strict sentinel zero handled by the prev==0 bootstrap path
         // below, which derives target from the current EMA so the
@@ -120,10 +151,12 @@ extern "C" __global__ void rl_per_alpha_controller(
     // The 0.4-0.6 baseline keeps the steady-state output near PER's
     // canonical 0.6 (when input EMA stabilises at kurt=10) while
     // leaving headroom to lift toward 1.0 under heavy tails.
+    const float per_alpha_min = isv[RL_PER_ALPHA_MIN_INDEX];
+    const float per_alpha_max = isv[RL_PER_ALPHA_MAX_INDEX];
     const float kurt_excess = fmaxf(0.0f, td_kurtosis_ema - isv[RL_KURT_GAUSSIAN_INDEX]);
     const float kurt_lift_scale = isv[RL_KURT_LIFT_SCALE_INDEX];
     float       target      = 0.4f + 0.2f * (kurt_excess / kurt_lift_scale);
-    target = fmaxf(PER_ALPHA_MIN, fminf(target, PER_ALPHA_MAX));
+    target = fmaxf(per_alpha_min, fminf(target, per_alpha_max));
 
     // Bootstrap on sentinel 0.0 per pearl_first_observation_bootstrap:
     // first emit replaces directly with the computed target. At
@@ -138,9 +171,29 @@ extern "C" __global__ void rl_per_alpha_controller(
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a   = fmaxf(alpha_step, WIENER_ALPHA_FLOOR);
+    const float a   = fmaxf(alpha_step, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       out = (1.0f - a) * prev + a * target;
 
-    out = fmaxf(PER_ALPHA_MIN, fminf(out, PER_ALPHA_MAX));
+    out = fmaxf(per_alpha_min, fminf(out, per_alpha_max));
+
+    // Asymmetric Schulman patience on the DESCENT direction (spec 2026-05-30):
+    // PER α rises on a single above-band kurtosis observation (heavy tails
+    // = act fast to concentrate sampling on informative tails). PER α
+    // falls only after N consecutive below-band observations — a single
+    // light-tailed step must not drag α toward MIN.
+    const float kurt_gaussian = isv[RL_KURT_GAUSSIAN_INDEX];
+    const float tolerance     = isv[RL_SCHULMAN_TOLERANCE_INDEX];
+    if (out < prev && td_kurtosis_ema < kurt_gaussian / tolerance) {
+        const float new_count = isv[RL_TD_KURT_BELOW_COUNT_INDEX] + 1.0f;
+        isv[RL_TD_KURT_BELOW_COUNT_INDEX] = new_count;
+        if (new_count < WIDEN_PATIENCE_CONSECUTIVE) {
+            // Hold at prev until patience accumulates.
+            isv[RL_PER_ALPHA_INDEX] = prev;
+            return;
+        }
+    } else {
+        isv[RL_TD_KURT_BELOW_COUNT_INDEX] = 0.0f;
+    }
+
     isv[RL_PER_ALPHA_INDEX] = out;
 }

crates/ml-alpha/cuda/rl_per_push_flush.cu

@@ -1,23 +1,25 @@
 /**
- * rl_per_push_flush.cu — Two-kernel coordinated coalesced replay write.
+ * rl_per_push_flush.cu — Coordinated coalesced replay write.
  *
- * Split from the original single-kernel volatile-spin design into two
- * kernels with stream-ordered dependency (graph-safe):
+ * Second kernel in the split rl_per_push pipeline. After rl_per_push_ring has
+ * written data to the n-step ring and set flush_flags[b] for completed n-step
+ * transitions, this kernel coordinates slot allocation and performs the actual
+ * coalesced write to the replay buffer.
  *
- *   Kernel 1: rl_per_flush_prefix_sum
- *     Grid=(1), Block=(1). Single thread computes exclusive prefix-sum of
- *     flush_flags, advances write_head and replay_len, writes per-batch
- *     offsets + base into write_offsets[0..b_size+1].
+ * Architecture:
+ *   - Grid=(b_size, 1, 1), Block=(128, 1, 1). One block per batch element.
+ *   - Block 0 runs the prefix-sum to assign write slots (single-threaded, O(B)).
+ *   - All other blocks spin on a volatile global-memory ready flag (no atomics).
+ *   - Once ready, each flushing block does a coalesced 128-thread copy of h_t
+ *     and h_tp1, then thread 0 computes the n-step return and writes scalars +
+ *     priority + resets the ring count.
  *
- *   Kernel 2: rl_per_flush_write
- *     Grid=(b_size), Block=(128). Each block reads its pre-computed offset
- *     from write_offsets, then does the coalesced h_t/h_tp1 copy and
- *     scalar write. No spin — the prefix-sum kernel completed before this
- *     launch (stream ordering).
- *
- * No atomicAdd — slot assignment is deterministic serial scan.
- * No volatile spin — correctness from stream ordering / graph node deps.
+ * Coordination: block-0 prefix-sum + volatile ready flag.
+ * No atomicAdd — slot assignment is deterministic serial scan (feedback_no_atomicadd).
  * Pre-compiled cubin only (feedback_no_nvrtc).
+ *
+ * Launch: CUDA_HOME=/usr/local/cuda nvcc -cubin -arch sm_86 -O3 \
+ *         --generate-line-info rl_per_push_flush.cu -o rl_per_push_flush.cubin
  */
 
 #define HIDDEN_DIM       128
@@ -28,89 +30,105 @@
 #define RL_GAMMA_INDEX   400
 #define RL_N_STEP_INDEX  403
 
-/* =====================================================================
- * Kernel 1: prefix-sum + write_head advance.
- *
- * Grid=(1,1,1), Block=(1,1,1). Single thread.
- *
- * Reads flush_flags[0..b_size], computes exclusive prefix-sum into
- * write_offsets[0..b_size], stores base write_head at write_offsets[b_size],
- * and advances the replay buffer's write_head + replay_len.
- * ===================================================================== */
-extern "C" __global__ void rl_per_flush_prefix_sum(
-    const int* __restrict__ flush_flags,     /* [B] */
-    int* __restrict__ write_offsets,          /* [B+1] output: offsets + base */
-    unsigned int* __restrict__ write_head,    /* [1] */
-    unsigned int* __restrict__ replay_len,    /* [1] */
-    int b_size,
-    int capacity
-)
-{
-    unsigned int base = write_head[0];
+extern "C" __global__ void rl_per_push_flush(
+    /* ── Flush coordination ── */
+    const int* __restrict__ flush_flags,              /* [B] from ring kernel: 1=flush, 0=skip */
+    int* __restrict__ write_offsets,                  /* [B+2] output: per-batch offsets, base, ready flag */
 
-    /* Exclusive prefix-sum */
-    int total = 0;
-    for (int i = 0; i < b_size; ++i) {
-        write_offsets[i] = total;
-        total += flush_flags[i];
-    }
-
-    /* Advance write head and replay length */
-    if (total > 0) {
-        write_head[0] = (base + (unsigned int)total) % (unsigned int)capacity;
-        unsigned int len = replay_len[0] + (unsigned int)total;
-        if (len > (unsigned int)capacity) len = (unsigned int)capacity;
-        replay_len[0] = len;
-    }
-
-    /* Store base write head for the write kernel */
-    write_offsets[b_size] = (int)base;
-}
-
-/* =====================================================================
- * Kernel 2: coalesced replay write.
- *
- * Grid=(b_size,1,1), Block=(128,1,1). One block per batch element.
- *
- * Reads pre-computed offset from write_offsets (populated by kernel 1).
- * No spin — stream ordering guarantees kernel 1 completed before this.
- * ===================================================================== */
-extern "C" __global__ void rl_per_flush_write(
-    const int* __restrict__ flush_flags,              /* [B] */
-    const int* __restrict__ write_offsets,             /* [B+1] */
-
-    /* N-step ring (read source) */
-    const float* __restrict__ nstep_scalars,          /* [B * N_STEP_MAX * 3] */
+    /* ── N-step ring (read source) ── */
+    const float* __restrict__ nstep_scalars,          /* [B * N_STEP_MAX * 3]: (r_scaled, r_raw, done) per ring slot */
     const float* __restrict__ nstep_h_t,              /* [B * N_STEP_MAX * HIDDEN_DIM] */
     const unsigned int* __restrict__ nstep_write_idx, /* [B] ring write cursor */
     const unsigned int* __restrict__ nstep_count,     /* [B] items in ring */
 
-    /* Current step data (for h_tp1) */
+    /* ── Current step data (for h_tp1) ── */
     const float* __restrict__ h_tp1_current,          /* [B * HIDDEN_DIM] */
     const float* __restrict__ log_pi_old,             /* [B] */
     const int*   __restrict__ actions,                /* [B] */
     const float* __restrict__ isv,                    /* ISV array */
 
-    /* Replay storage (write destination) */
+    /* ── Replay storage (write destination) ── */
     float* __restrict__ replay_h_t,                   /* [capacity * HIDDEN_DIM] */
     float* __restrict__ replay_h_tp1,                 /* [capacity * HIDDEN_DIM] */
     float* __restrict__ replay_scalars,               /* [capacity * SCALARS_PER_TRANSITION] */
     float* __restrict__ priority_tree,                /* [2 * capacity] (leaf layer at offset capacity) */
-    float* __restrict__ max_priority,                 /* [1] running max priority */
+    unsigned int* __restrict__ write_head,            /* [1] circular write cursor */
+    unsigned int* __restrict__ replay_len,            /* [1] current buffer occupancy */
+    float* __restrict__ max_priority,                 /* [1] running max priority for new inserts */
 
-    /* N-step count reset (written on flush) */
-    unsigned int* __restrict__ nstep_count_out,       /* [B] */
+    /* ── N-step count reset (written on flush) ── */
+    unsigned int* __restrict__ nstep_count_out,       /* [B] — set to 0 for flushed batches */
 
     int b_size,
     int capacity
 )
 {
+    /* ====================================================================
+     * PHASE 1: Block 0 coordination (thread 0 only).
+     *
+     * Computes prefix-sum of flush_flags to assign contiguous write slots,
+     * advances write_head and replay_len, stores base for other blocks,
+     * and signals ready via volatile write.
+     * ==================================================================== */
+    if (blockIdx.x == 0 && threadIdx.x == 0) {
+        unsigned int base = write_head[0];
+
+        /* Exclusive prefix-sum: write_offsets[i] = number of flushes before batch i */
+        int total = 0;
+        for (int i = 0; i < b_size; ++i) {
+            write_offsets[i] = total;
+            total += flush_flags[i];
+        }
+
+        /* Advance write head and replay length */
+        if (total > 0) {
+            write_head[0] = (base + (unsigned int)total) % (unsigned int)capacity;
+            unsigned int len = replay_len[0] + (unsigned int)total;
+            if (len > (unsigned int)capacity) len = (unsigned int)capacity;
+            replay_len[0] = len;
+        }
+
+        /* Store base write head for other blocks at slot [b_size] */
+        write_offsets[b_size] = (int)base;
+
+        /* Fence: ensure all writes above are globally visible before signaling */
+        __threadfence();
+
+        /* Signal ready at slot [b_size + 1] */
+        write_offsets[b_size + 1] = 1;
+        __threadfence();
+    }
+
+    /* ====================================================================
+     * PHASE 2: All blocks wait for ready signal.
+     *
+     * Non-block-0 blocks spin on a volatile read of the ready flag.
+     * Block 0 already wrote it, so it proceeds immediately.
+     * ==================================================================== */
+    if (threadIdx.x == 0 && blockIdx.x != 0) {
+        volatile int* ready = (volatile int*)&write_offsets[b_size + 1];
+        while (*ready == 0) {
+            /* spin — volatile load, no atomic */
+        }
+    }
+    __syncthreads();
+
+    /* ====================================================================
+     * PHASE 3: Coalesced replay write (128 threads per block).
+     *
+     * Each flushing block writes:
+     *   - h_t[HIDDEN_DIM]: from oldest ring entry (coalesced, all 128 threads)
+     *   - h_tp1[HIDDEN_DIM]: from current step (coalesced, all 128 threads)
+     *   - scalars[7]: n-step return + metadata (thread 0 only)
+     *   - priority: max_priority into leaf layer (thread 0 only)
+     *   - reset: nstep_count_out[b] = 0 (thread 0 only)
+     * ==================================================================== */
     const int b = blockIdx.x;
 
     /* Early exit: nothing to flush for this batch */
     if (flush_flags[b] == 0) return;
 
-    /* Compute target replay slot from pre-computed offsets */
+    /* Compute target replay slot */
     const unsigned int base = (unsigned int)write_offsets[b_size];
     const unsigned int my_offset = (unsigned int)write_offsets[b];
     const unsigned int my_slot = (base + my_offset) % (unsigned int)capacity;

crates/ml-alpha/cuda/rl_per_sample.cu

@@ -1,11 +1,11 @@
 /* =====================================================================
  * rl_per_sample.cu — GPU-resident PER: proportional sampling via sum-tree
  *
- * Grid=(b_size), Block=(128). One block per sample.
+ * Grid=(b_size), Block=(1). One thread per sample.
  *
- * Thread 0 does the tree walk + scalar unpack. All 128 threads cooperate
- * on the coalesced h_t and h_tp1 gathers (128 floats = HIDDEN_DIM per
- * sample, one float per thread, single 512-byte coalesced transaction).
+ * Each thread samples a leaf from the priority sum-tree using stratified
+ * sampling (segment per thread) with xorshift32 PRNG, then gathers the
+ * transition data from replay storage.
  *
  * ISV reads: none (alpha used only at priority-update time)
  * ===================================================================== */
@@ -44,87 +44,75 @@ extern "C" __global__ void rl_per_sample(
     int capacity
 )
 {
-    const int b = blockIdx.x;
-    const int tid = threadIdx.x;
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
     if (b >= b_size) return;
 
-    /* ── Shared memory for broadcasting the sampled leaf index ────────── */
-    __shared__ int s_safe_leaf;
+    const unsigned int len = replay_len[0];
+    const float total_priority = priority_tree[1]; /* root */
 
-    /* ── Thread 0: tree walk + scalar reads ──────────────────────────── */
-    if (tid == 0) {
-        const unsigned int len = replay_len[0];
-        const float total_priority = priority_tree[1]; /* root */
-
-        /* Guard: empty or zero-priority replay */
-        if (total_priority < 1e-9f || len == 0) {
-            s_safe_leaf = -1; /* sentinel: zero-fill outputs */
-        } else {
-            /* Seed PRNG if cold */
-            if (prng_state[b] == 0) {
-                prng_state[b] = (unsigned int)(b + 1) * 2654435761u;
-            }
-
-            /* Stratified sampling: draw u in [b*segment, (b+1)*segment) */
-            const float segment = total_priority / (float)b_size;
-            unsigned int rng = xorshift32(&prng_state[b]);
-            const float u_frac = (float)(rng & 0x00FFFFFFu) / (float)0x01000000u;
-            float u = ((float)b + u_frac) * segment;
-
-            /* Clamp to avoid floating-point overshoot */
-            if (u >= total_priority) u = total_priority - 1e-6f;
-            if (u < 0.0f) u = 0.0f;
-
-            /* Walk tree top-down */
-            int idx = 1;
-            while (idx < capacity) {
-                const int left = 2 * idx;
-                const float left_val = priority_tree[left];
-                if (u <= left_val) {
-                    idx = left;
-                } else {
-                    u -= left_val;
-                    idx = left + 1;
-                }
-            }
-            const int leaf = idx - capacity;
-
-            /* Clamp leaf to valid range */
-            const int safe_leaf = (leaf >= 0 && leaf < (int)len) ? leaf : 0;
-            s_safe_leaf = safe_leaf;
-            sample_indices[b] = (unsigned int)safe_leaf;
-
-            /* Unpack scalars (thread 0 only — small data, not worth parallelising) */
-            const int sc_base = safe_leaf * SCALARS_PER_TRANSITION;
-            sampled_actions[b]        = (int)replay_scalars[sc_base + 0];
-            sampled_rewards[b]        = replay_scalars[sc_base + 1];
-            sampled_dones[b]          = replay_scalars[sc_base + 3];
-            sampled_log_pi_old[b]     = replay_scalars[sc_base + 4];
-            sampled_n_step_gammas[b]  = replay_scalars[sc_base + 5];
-        }
-    }
-    __syncthreads();
-
-    const int safe_leaf = s_safe_leaf;
-
-    if (safe_leaf < 0) {
-        /* Empty replay — zero-fill h_t and h_tp1 (coalesced, all 128 threads) */
-        sampled_h_t[b * HIDDEN_DIM + tid] = 0.0f;
-        sampled_h_tp1[b * HIDDEN_DIM + tid] = 0.0f;
-        if (tid == 0) {
-            sampled_rewards[b] = 0.0f;
-            sampled_dones[b] = 0.0f;
-            sampled_log_pi_old[b] = 0.0f;
-            sampled_n_step_gammas[b] = 0.0f;
-            sampled_actions[b] = 0;
-            sample_indices[b] = 0;
+    /* Guard: empty or zero-priority replay */
+    if (total_priority < 1e-9f || len == 0) {
+        for (int i = 0; i < HIDDEN_DIM; ++i) {
+            sampled_h_t[b * HIDDEN_DIM + i] = 0.0f;
+            sampled_h_tp1[b * HIDDEN_DIM + i] = 0.0f;
         }
+        sampled_rewards[b] = 0.0f;
+        sampled_dones[b] = 0.0f;
+        sampled_log_pi_old[b] = 0.0f;
+        sampled_n_step_gammas[b] = 0.0f;
+        sampled_actions[b] = 0;
+        sample_indices[b] = 0;
         return;
     }
 
-    /* ── Coalesced h_t gather (128 threads, 1 float each) ────────────── */
-    sampled_h_t[b * HIDDEN_DIM + tid] = replay_h_t[safe_leaf * HIDDEN_DIM + tid];
+    /* ── Seed PRNG if cold ────────────────────────────────────────────── */
+    if (prng_state[b] == 0) {
+        prng_state[b] = (unsigned int)(b + 1) * 2654435761u;
+    }
 
-    /* ── Coalesced h_tp1 gather (128 threads, 1 float each) ──────────── */
-    sampled_h_tp1[b * HIDDEN_DIM + tid] = replay_h_tp1[safe_leaf * HIDDEN_DIM + tid];
+    /* ── Stratified sampling: draw u in [b*segment, (b+1)*segment) ────── */
+    const float segment = total_priority / (float)b_size;
+    unsigned int rng = xorshift32(&prng_state[b]);
+    const float u_frac = (float)(rng & 0x00FFFFFFu) / (float)0x01000000u; /* [0, 1) */
+    float u = ((float)b + u_frac) * segment;
+
+    /* Clamp to avoid floating-point overshoot */
+    if (u >= total_priority) u = total_priority - 1e-6f;
+    if (u < 0.0f) u = 0.0f;
+
+    /* ── Walk tree top-down ───────────────────────────────────────────── */
+    int idx = 1;
+    while (idx < capacity) {
+        const int left = 2 * idx;
+        const float left_val = priority_tree[left];
+        if (u <= left_val) {
+            idx = left;
+        } else {
+            u -= left_val;
+            idx = left + 1;
+        }
+    }
+    const int leaf = idx - capacity;
+
+    /* Clamp leaf to valid range */
+    const int safe_leaf = (leaf >= 0 && leaf < (int)len) ? leaf : 0;
+    sample_indices[b] = (unsigned int)safe_leaf;
+
+    /* ── Gather h_t ──────────────────────────────────────────────────── */
+    for (int i = 0; i < HIDDEN_DIM; ++i) {
+        sampled_h_t[b * HIDDEN_DIM + i] = replay_h_t[safe_leaf * HIDDEN_DIM + i];
+    }
+
+    /* ── Gather h_tp1 ────────────────────────────────────────────────── */
+    for (int i = 0; i < HIDDEN_DIM; ++i) {
+        sampled_h_tp1[b * HIDDEN_DIM + i] = replay_h_tp1[safe_leaf * HIDDEN_DIM + i];
+    }
+
+    /* ── Unpack scalars ──────────────────────────────────────────────── */
+    const int sc_base = safe_leaf * SCALARS_PER_TRANSITION;
+    sampled_actions[b]        = (int)replay_scalars[sc_base + 0];
+    sampled_rewards[b]        = replay_scalars[sc_base + 1]; /* n-step scaled return */
+    sampled_dones[b]          = replay_scalars[sc_base + 3];
+    sampled_log_pi_old[b]     = replay_scalars[sc_base + 4];
+    sampled_n_step_gammas[b]  = replay_scalars[sc_base + 5];
 }

crates/ml-alpha/cuda/rl_per_tree_rebuild.cu

@@ -1,30 +1,86 @@
 /* =====================================================================
- * rl_per_tree_rebuild.cu — GPU-resident PER: per-level sum-tree rebuild
+ * rl_per_tree_rebuild.cu — GPU-resident PER: bottom-up sum-tree rebuild
  *
- * One kernel invocation per tree level. The host launches log2(capacity)
- * times, from bottom (level 0 = parents of leaves) to top (root).
- * Stream ordering between launches provides the device-wide barrier that
- * the previous __threadfence() approach lacked — each level's writes are
- * fully complete before the next level reads them.
+ * Grid=(1), Block=(1024). Single-block deterministic rebuild.
  *
- * Graph-safe: each level is a separate kernel node in the CUDA graph.
- * The graph engine respects stream-order dependencies between nodes.
+ * Rebuilds the entire sum-tree from leaf priorities (at indices
+ * [capacity..2*capacity)) up to the root (index 1). All levels are
+ * processed within ONE block: __syncthreads() between levels is a
+ * proper barrier guaranteeing every thread in the block sees every
+ * other thread's writes from the previous level.
+ *
+ * Determinism rationale (Phase 2 §2.F fix — Option C):
+ *   The previous Grid=(128) launch used __threadfence() between levels.
+ *   __threadfence() is a memory-ordering primitive, NOT a grid-wide
+ *   barrier — it orders THIS thread's writes globally but does not
+ *   wait for OTHER blocks' writes to be visible.  Under the previous
+ *   geometry, block N could read level-L nodes while block M's
+ *   level-L writes were still in flight, producing different
+ *   addition orderings across same-seed runs.  Same-seed runs of the
+ *   determinism diagnostic at b=128 saw root priority diverge
+ *   ~592.7 vs ~695.7 at step 2 (Phase 2 sub-investigation dumps).
+ *
+ *   By collapsing to a single block, we lose grid-level parallelism
+ *   but gain bit-deterministic execution: __syncthreads() is a hard
+ *   intra-block barrier, and every internal node is the deterministic
+ *   sum of its two specific children written in a definite order
+ *   (sequential grid-stride within one block, fixed thread→node
+ *   mapping via i = tid + k*blockDim.x).
+ *
+ *   Speed cost: capacity=32768 → ~65k floating-point adds total, 15
+ *   levels = 15 syncs.  On RTX 3050 the kernel runs ~30-80 μs which
+ *   is a ~10× slowdown vs the parallel version but well within the
+ *   per-step budget (the step itself is ~30-50 ms at b=128).
+ *
+ * Launch: Grid=(1,1,1), Block=(1024,1,1).  Block size 1024 is the
+ *   CUDA hard maximum; works on all foxhunt GPUs (sm_86 / sm_89 /
+ *   sm_90).  If capacity grows past 2^21 in the future, switch to
+ *   cooperative_groups::grid().sync() for a multi-block deterministic
+ *   path.
  *
  * No atomicAdd — each internal node is written by exactly one thread.
+ * No __threadfence() — __syncthreads() is the only inter-level barrier.
  * ===================================================================== */
 
-extern "C" __global__ void rl_per_tree_rebuild_level(
+extern "C" __global__ void rl_per_tree_rebuild(
     float* __restrict__ priority_tree, /* [2 * capacity] */
-    int start,                         /* first node index at this level */
-    int nodes_at_level                 /* number of nodes to process at this level */
+    int capacity
 )
 {
-    const int tid_global = blockIdx.x * blockDim.x + threadIdx.x;
-    const int total_threads = gridDim.x * blockDim.x;
+    /* Single block, single-block-stride loop per level.  blockIdx.x is
+     * guaranteed 0 by the launch geometry, but guard anyway so a
+     * future caller passing Grid>(1,1,1) is a silent no-op rather than
+     * a corrupted tree. */
+    if (blockIdx.x != 0) return;
 
-    /* Grid-stride loop: each thread processes one or more nodes */
-    for (int i = tid_global; i < nodes_at_level; i += total_threads) {
-        const int node = start + i;
-        priority_tree[node] = priority_tree[2 * node] + priority_tree[2 * node + 1];
+    const int tid = threadIdx.x;
+    const int block_size = blockDim.x;
+
+    /* Bottom-up: level 0 = parents of leaves, last level = root.
+     * At level L, there are (capacity >> (L+1)) internal nodes,
+     * with indices [capacity >> (L+1) .. capacity >> L).            */
+    int nodes_at_level = capacity >> 1; /* level 0: cap/2 nodes */
+    int start = nodes_at_level;         /* first node index at this level */
+
+    while (nodes_at_level >= 1) {
+        /* Each thread processes multiple nodes via block-stride loop.
+         * Mapping `i = tid + k*block_size` is FIXED across runs:
+         * thread t always writes nodes (start + t), (start + t + B),
+         * (start + t + 2B), ... ensuring a deterministic write order.
+         */
+        for (int i = tid; i < nodes_at_level; i += block_size) {
+            const int node = start + i;
+            priority_tree[node] = priority_tree[2 * node]
+                                + priority_tree[2 * node + 1];
+        }
+
+        /* Intra-block barrier — proper synchronisation, unlike the
+         * previous __threadfence() which did NOT wait for other
+         * blocks' writes. */
+        __syncthreads();
+
+        /* Move up one level */
+        nodes_at_level >>= 1;
+        start >>= 1;
     }
 }

crates/ml-alpha/cuda/rl_pi_grad_blend.cu

@@ -0,0 +1,48 @@
+// rl_pi_grad_blend.cu — Phase 3D-C (2026-06-03): PPO surrogate × Q-distill
+// gradient blend operator.
+//
+// Replaces the pre-Q-distill zero-fill of `ss_pi_grad_logits_d` with a
+// conditional scale/zero step that lets the PPO clipped-surrogate
+// gradient flow into π alongside the Q-distill term:
+//
+//     ENABLED (slot RL_PPO_SURROGATE_ENABLED_INDEX > 0.5):
+//       pi_grad[i] *= weight (slot RL_PPO_SURROGATE_WEIGHT_INDEX)
+//     DISABLED:
+//       pi_grad[i]  = 0.0    (legacy zero-then-distill path)
+//
+// Q-distill then ADDS (`pi_grad_logits[i] += ...`) on top, producing:
+//   pi_grad[i] = weight * grad_PPO[i] + grad_Q_distill[i]
+//
+// Why this is needed: per Goodhart-Skalse 2024 (Causes of Misalignment),
+// the four-stage Q→π attenuation chain (V → Bellman target → softmax(Q/τ)
+// → KL distill) cannot transmit small persistent fees back to π. Cao et
+// al. 2026 (arXiv:2603.29086) showed restoring a direct policy-gradient
+// channel (weight 1e-3 to 1e-2) cuts turnover 96% across TD3 / PPO / SAC
+// when paired with quadratic impact costs.
+//
+// Per `feedback_no_atomicadd`: element-wise, one thread per logit.
+// Per `feedback_no_nvrtc`: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+#define RL_PPO_SURROGATE_WEIGHT_INDEX   797
+#define RL_PPO_SURROGATE_ENABLED_INDEX  798
+
+extern "C" __global__ void rl_pi_grad_blend(
+    float*       __restrict__ pi_grad_logits, // [B × N_ACTIONS] IN/OUT
+    const float* __restrict__ isv,            // ISV bus (RO)
+    int                       b_size,
+    int                       n_actions
+) {
+    const int i = blockIdx.x * blockDim.x + threadIdx.x;
+    const int total = b_size * n_actions;
+    if (i >= total) return;
+
+    const float enabled = isv[RL_PPO_SURROGATE_ENABLED_INDEX];
+    if (enabled > 0.5f) {
+        const float w = isv[RL_PPO_SURROGATE_WEIGHT_INDEX];
+        pi_grad_logits[i] *= w;
+    } else {
+        pi_grad_logits[i] = 0.0f;
+    }
+}

crates/ml-alpha/cuda/rl_popart_normalize.cu

@@ -9,9 +9,10 @@
 // Grid=(1), Block=(min(b_size, 256)).
 //
 // Two-pass design:
-//   Pass 1: warp-shuffle + shared-mem tree-reduce to compute batch sum
-//            and sum-of-squares.
+//   Pass 1: warp-shuffle + shared-mem tree-reduce to compute batch sum,
+//            sum-of-squares, and per-account max |r| (F4 envelope).
 //   Pass 2: thread 0 computes batch mean/var, updates ISV via Welford-EMA,
+//            applies max-magnitude envelope floor on sigma,
 //            broadcasts new mean+sigma to all threads via shared mem.
 //   Pass 3: each thread normalizes its reward(s) in place.
 //
@@ -27,6 +28,21 @@
 #define POPART_MEAN_OLD_INDEX   557
 #define POPART_ALPHA_INDEX      558
 
+// F4: per-account max-magnitude envelope (Theorem 6, spec v3)
+#define RL_POPART_MAX_ABS_REWARD_EMA_INDEX 714
+#define RL_POPART_MAX_DECAY_ALPHA_INDEX    715
+
+// B-8 (2026-06-01): pre-envelope-floor Welford σ. Diag emits as
+// `popart.sigma_welford` for σ shock attribution under B-7. Mirror of
+// Rust const `RL_POPART_SIGMA_WELFORD_INDEX` in `isv_slots.rs`.
+#define RL_POPART_SIGMA_WELFORD_INDEX      725
+
+// Phase 3B-Y (2026-06-03): PopArt normalize gate. 0.0 = DISABLED (skip the
+// final whitening loop but keep running stats updating). 1.0 = ENABLED
+// (legacy van Hasselt 2016 whitening). Mirror of Rust const
+// `RL_POPART_NORMALIZE_ENABLED_INDEX` in `isv_slots.rs`.
+#define RL_POPART_NORMALIZE_ENABLED_INDEX 793
+
 #define BLOCK_SIZE 256
 
 // Warp-level sum reduction via shuffle-down.
@@ -36,6 +52,14 @@ __device__ __forceinline__ float warp_reduce_sum(float val) {
     return val;
 }
 
+// Warp-level max reduction via shuffle-down.
+__device__ __forceinline__ float warp_reduce_max(float val) {
+    for (int offset = 16; offset > 0; offset >>= 1) {
+        val = fmaxf(val, __shfl_down_sync(0xFFFFFFFF, val, offset));
+    }
+    return val;
+}
+
 extern "C" __global__ void rl_popart_normalize(
     float* __restrict__ rewards,  // [B] IN/OUT
     float* __restrict__ isv,
@@ -48,33 +72,40 @@ extern "C" __global__ void rl_popart_normalize(
     const int tid = threadIdx.x;
     const int block_dim = blockDim.x;
 
-    // Shared memory: 2 banks for tree-reduce + 2 floats for broadcast.
-    extern __shared__ float sdata[];  // [block_dim * 2 + 2]
-    float* s_sum    = sdata;                 // [block_dim]
-    float* s_sum_sq = sdata + block_dim;     // [block_dim]
-    // Broadcast slots at the end:
-    // sdata[block_dim * 2 + 0] = new_mean
-    // sdata[block_dim * 2 + 1] = new_sigma
+    // Shared memory: 3 banks for tree-reduce + 2 floats for broadcast.
+    // Layout:
+    //   s_sum[]     at sdata + 0              [block_dim floats]
+    //   s_sum_sq[]  at sdata + block_dim      [block_dim floats]
+    //   s_max_abs[] at sdata + block_dim * 2  [block_dim floats]  (F4)
+    //   Broadcast   at sdata + block_dim * 3  [2 floats: new_mean, new_sigma]
+    extern __shared__ float sdata[];  // [block_dim * 3 + 2]
+    float* s_sum     = sdata;                      // [block_dim]
+    float* s_sum_sq  = sdata + block_dim;          // [block_dim]
+    float* s_max_abs = sdata + block_dim * 2;      // [block_dim]  F4
 
-    // ── Pass 1: grid-stride accumulation of sum and sum-of-squares ──
-    float local_sum = 0.0f;
+    // ── Pass 1: grid-stride accumulation of sum, sum-of-squares, max |r| ──
+    float local_sum    = 0.0f;
     float local_sum_sq = 0.0f;
+    float local_max_abs = 0.0f;  // neutral element (|r| >= 0)
     for (int i = tid; i < b_size; i += block_dim) {
         float r = rewards[i];
-        local_sum += r;
+        local_sum    += r;
         local_sum_sq += r * r;
+        local_max_abs = fmaxf(local_max_abs, fabsf(r));  // F4
     }
 
     // ── Warp shuffle reduction within each warp ──
-    float warp_sum = warp_reduce_sum(local_sum);
+    float warp_sum    = warp_reduce_sum(local_sum);
     float warp_sum_sq = warp_reduce_sum(local_sum_sq);
+    float warp_max    = warp_reduce_max(local_max_abs);  // F4
 
     // Lane 0 of each warp writes to shared memory.
     int warp_id = tid / 32;
     int lane_id = tid % 32;
     if (lane_id == 0) {
-        s_sum[warp_id] = warp_sum;
-        s_sum_sq[warp_id] = warp_sum_sq;
+        s_sum[warp_id]     = warp_sum;
+        s_sum_sq[warp_id]  = warp_sum_sq;
+        s_max_abs[warp_id] = warp_max;  // F4
     }
     __syncthreads();
 
@@ -83,8 +114,10 @@ extern "C" __global__ void rl_popart_normalize(
     if (tid < 32) {
         float v_sum = (tid < n_warps) ? s_sum[tid] : 0.0f;
         float v_ssq = (tid < n_warps) ? s_sum_sq[tid] : 0.0f;
+        float v_max = (tid < n_warps) ? s_max_abs[tid] : 0.0f;  // F4
         v_sum = warp_reduce_sum(v_sum);
         v_ssq = warp_reduce_sum(v_ssq);
+        v_max = warp_reduce_max(v_max);  // F4
 
         if (tid == 0) {
             // ── Batch statistics ──
@@ -118,13 +151,35 @@ extern "C" __global__ void rl_popart_normalize(
 
             float new_sigma = sqrtf(fmaxf(new_var, 1e-6f));
 
+            // B-8 (2026-06-01): publish Welford-only σ BEFORE the F4 envelope
+            // floor below. Diag emits this as `popart.sigma_welford` so σ shocks
+            // can be attributed to either Welford drift OR envelope spike.
+            // Pure observability — does not perturb computation.
+            isv[RL_POPART_SIGMA_WELFORD_INDEX] = new_sigma;
+
+            // ── F4: per-account max-magnitude envelope detector (Theorem 6) ──
+            // Fast-up, slow-decay EMA on per-step max |r|. Floors popart sigma
+            // so single-account tail events are not diluted by the batch mean.
+            const float max_r_this_step = v_max;
+            const float decay_alpha = isv[RL_POPART_MAX_DECAY_ALPHA_INDEX];
+            float max_r_ema = isv[RL_POPART_MAX_ABS_REWARD_EMA_INDEX];
+            if (max_r_this_step > max_r_ema) {
+                max_r_ema = max_r_this_step;  // fast-up
+            } else {
+                max_r_ema = (1.0f - decay_alpha) * max_r_ema + decay_alpha * max_r_this_step;  // slow decay
+            }
+            isv[RL_POPART_MAX_ABS_REWARD_EMA_INDEX] = max_r_ema;
+
+            new_sigma = fmaxf(new_sigma, max_r_ema);  // floor: σ_effective = max(σ_existing, max_r_ema)
+
             isv[POPART_MEAN_INDEX]  = new_mean;
             isv[POPART_VAR_INDEX]   = new_var;
             isv[POPART_SIGMA_INDEX] = new_sigma;
 
             // Broadcast to all threads via shared mem.
-            sdata[block_dim * 2 + 0] = new_mean;
-            sdata[block_dim * 2 + 1] = new_sigma;
+            // CRITICAL (Issue β): broadcast slots at block_dim * 3, not block_dim * 2.
+            sdata[block_dim * 3 + 0] = new_mean;
+            sdata[block_dim * 3 + 1] = new_sigma;
 
             __threadfence_system();
         }
@@ -132,11 +187,18 @@ extern "C" __global__ void rl_popart_normalize(
     __syncthreads();
 
     // ── Pass 3: normalize rewards in place ──
-    float mean  = sdata[block_dim * 2 + 0];
-    float sigma = sdata[block_dim * 2 + 1];
-    float inv_sigma = 1.0f / sigma;  // sigma >= sqrt(1e-6) > 0
+    // CRITICAL (Issue β): read broadcast slots at block_dim * 3.
+    // Phase 3B-Y (2026-06-03): gated by slot 793 (RL_POPART_NORMALIZE_ENABLED_INDEX).
+    // Running stats above (mean/var/sigma + envelope EMA) still update so that
+    // re-enabling the gate produces sensible values without a session restart.
+    const float popart_enabled = isv[RL_POPART_NORMALIZE_ENABLED_INDEX];
+    if (popart_enabled > 0.5f) {
+        float mean  = sdata[block_dim * 3 + 0];
+        float sigma = sdata[block_dim * 3 + 1];
+        float inv_sigma = 1.0f / sigma;  // sigma >= sqrt(1e-6) > 0
 
-    for (int i = tid; i < b_size; i += block_dim) {
-        rewards[i] = (rewards[i] - mean) * inv_sigma;
+        for (int i = tid; i < b_size; i += block_dim) {
+            rewards[i] = (rewards[i] - mean) * inv_sigma;
+        }
     }
 }

crates/ml-alpha/cuda/rl_popart_v_correct.cu

@@ -18,10 +18,16 @@
 
 #include <cuda_runtime.h>
 
-#define POPART_MEAN_INDEX       553
-#define POPART_SIGMA_INDEX      555
-#define POPART_SIGMA_OLD_INDEX  556
-#define POPART_MEAN_OLD_INDEX   557
+#define POPART_MEAN_INDEX                553
+#define POPART_SIGMA_INDEX              555
+#define POPART_SIGMA_OLD_INDEX          556
+#define POPART_MEAN_OLD_INDEX           557
+// Phase 3B-Y companion gate: when PopArt normalization is disabled
+// (slot 793 = 0), V-correction MUST also be skipped. The running
+// mean/sigma stats still update against raw reward magnitudes, so
+// the correction formula would scale v_pred against an out-of-band
+// scale that no longer matches the V regression target.
+#define RL_POPART_NORMALIZE_ENABLED_INDEX 793
 
 extern "C" __global__ void rl_popart_v_correct(
     float* __restrict__ v_pred,     // [B] IN/OUT
@@ -32,6 +38,11 @@ extern "C" __global__ void rl_popart_v_correct(
     int b = blockIdx.x * blockDim.x + threadIdx.x;
     if (b >= b_size) return;
 
+    // Phase 3B-Y: skip correction when popart normalization is off.
+    // Reward stream is in raw pnl-units; V is trained against the raw
+    // returns directly; the correction would introduce a unit mismatch.
+    if (isv[RL_POPART_NORMALIZE_ENABLED_INDEX] <= 0.5f) return;
+
     float sigma_old = isv[POPART_SIGMA_OLD_INDEX];
     float sigma_new = isv[POPART_SIGMA_INDEX];
     float mean_old  = isv[POPART_MEAN_OLD_INDEX];

crates/ml-alpha/cuda/rl_ppo_clip_controller.cu

@@ -42,16 +42,36 @@
 // when ratios run away).
 
 #define RL_PPO_CLIP_INDEX   402
-#define EPS_MIN             0.05f
-#define EPS_MAX             0.5f
+// ε MIN/MAX are now ISV-driven per the 2026-05-30 clamp-bound extension —
+// the prior hardcoded `[0.05, 0.5]` calibration was a fixed-regime choice
+// that contributed to fold 0/1 saturation when Phase 4.5 narrowed the KL
+// signal distribution. ISV-residence makes the bound runtime-tunable
+// (visible in diag JSONL, re-seedable without recompile).
+#define RL_PPO_CLIP_EPS_MIN_INDEX         640
+#define RL_PPO_CLIP_EPS_MAX_INDEX         641
 // ISV-driven bootstrap + KL target per `feedback_isv_for_adaptive_bounds`.
 #define RL_EPS_BOOTSTRAP_INDEX            474
 #define RL_KL_TARGET_INDEX                454
 // Schulman pattern parameters — global slots shared by 4 controllers.
 #define RL_SCHULMAN_TOLERANCE_INDEX       468
 #define RL_SCHULMAN_ADJUST_RATE_INDEX     469
-#define KL_NOISE_FLOOR_FRAC               0.01f
-#define WIENER_ALPHA_FLOOR                0.4f
+// Wiener-α floor — shared across 9 controllers per
+// `pearl_wiener_alpha_floor_for_nonstationary`. ISV-resident at slot 659
+// so all consumers stay aligned without per-file `#define` drift.
+#define RL_WIENER_ALPHA_FLOOR_INDEX       659
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// noise floor derives from observed kl_pi_ema variance via Welford triples,
+// asymmetric Schulman widening requires N consecutive below-band observations.
+// Replaces hardcoded KL_NOISE_FLOOR_FRAC=0.01f which was the root cause of
+// the fold 0/1 saturation (ε locked at MAX 0.50 within 50 steps because the
+// 1%-of-target floor was 100× too low for the post-Phase-4.5 KL regime).
+#define RL_KL_PI_VAR_COUNT_INDEX           588
+#define RL_KL_PI_VAR_M2_INDEX              590
+#define RL_KL_PI_BELOW_COUNT_INDEX         591
+#define NOISE_FLOOR_TARGET_FRAC            0.5f  // floor ≥ 50% of target
+#define NOISE_FLOOR_STD_MULTIPLIER         2.0f  // floor ≥ 2σ of observed signal
+#define WIDEN_PATIENCE_CONSECUTIVE         3.0f  // widen requires N below-band steps
 
 
 // ─────────────────────────────────────────────────────────────────────
@@ -93,26 +113,49 @@ extern "C" __global__ void rl_ppo_clip_controller(
 
     // ISV-driven KL target (was hardcoded #define).
     const float kl_target = isv[RL_KL_TARGET_INDEX];
-    const float kl_noise_floor = kl_target * KL_NOISE_FLOOR_FRAC;
 
-    // Noise-floor gate: KL below kl_noise_floor is dominated by
-    // numerical noise, not real policy divergence. Hold ε unchanged.
+    // Adaptive noise floor — signal-driven per
+    // `pearl_zscore_normalization_for_magnitude_asymmetric_signals` and
+    // `feedback_adaptive_not_tuned`. Floor must scale with observed signal
+    // magnitude AND have an absolute minimum tied to the target so a
+    // momentarily-noisy signal can't trigger spurious adjustments.
+    // Welford sample variance = M² / (count − 1) when count > 1.
+    const float kl_count = isv[RL_KL_PI_VAR_COUNT_INDEX];
+    const float kl_var = (kl_count > 1.0f)
+        ? isv[RL_KL_PI_VAR_M2_INDEX] / (kl_count - 1.0f)
+        : 0.0f;
+    const float kl_std = sqrtf(kl_var);
+    const float kl_noise_floor = fmaxf(kl_target * NOISE_FLOOR_TARGET_FRAC,
+                                        kl_std * NOISE_FLOOR_STD_MULTIPLIER);
+
+    // Noise-floor gate: KL below the adaptive floor is dominated by
+    // numerical noise OR signal stays naturally below target under the
+    // current architecture (e.g., Phase 4.5 reduces KL by ~50×). Hold ε.
     if (kl_ema < kl_noise_floor) return;
 
-    // Bounded multiplicative adjustment (Schulman-style adaptive KL).
-    // Schulman params from ISV — shared with target_tau, rollout_steps.
+    // Asymmetric Schulman (spec 2026-05-30 Section "Approach C, folded in"):
+    // tightening fires on a single above-band observation — real policy
+    // divergence is a safety signal we act on fast. Widening requires
+    // N consecutive below-band observations so a single noisy step can't
+    // drive ε past bootstrap. Below-band counter is per-controller in ISV.
     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
     float ratio;
     if (kl_ema > kl_target * tolerance) {
-        ratio = 1.0f / adjust_rate;
+        ratio = 1.0f / adjust_rate;                       // tighten — single observation
+        isv[RL_KL_PI_BELOW_COUNT_INDEX] = 0.0f;           // reset patience
     } else if (kl_ema < kl_target / tolerance) {
-        ratio = adjust_rate;
+        const float new_count = isv[RL_KL_PI_BELOW_COUNT_INDEX] + 1.0f;
+        isv[RL_KL_PI_BELOW_COUNT_INDEX] = new_count;
+        ratio = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? adjust_rate : 1.0f;
     } else {
+        isv[RL_KL_PI_BELOW_COUNT_INDEX] = 0.0f;           // in-band → reset
         ratio = 1.0f;
     }
+    const float eps_min = isv[RL_PPO_CLIP_EPS_MIN_INDEX];
+    const float eps_max = isv[RL_PPO_CLIP_EPS_MAX_INDEX];
     float eps_target = eps_prev * ratio;
-    eps_target = fmaxf(EPS_MIN, fminf(eps_target, EPS_MAX));
+    eps_target = fmaxf(eps_min, fminf(eps_target, eps_max));
 
     // First-observation replace-directly per
     // `pearl_first_observation_bootstrap`. See rl_target_tau_controller
@@ -125,9 +168,9 @@ extern "C" __global__ void rl_ppo_clip_controller(
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a       = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+    const float a       = fmaxf(alpha, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       eps_new = (1.0f - a) * eps_prev + a * eps_target;
 
-    eps_new = fmaxf(EPS_MIN, fminf(eps_new, EPS_MAX));
+    eps_new = fmaxf(eps_min, fminf(eps_new, eps_max));
     isv[RL_PPO_CLIP_INDEX] = eps_new;
 }

crates/ml-alpha/cuda/rl_ppo_diagnostic_stats_reduce.cu

@@ -0,0 +1,117 @@
+// rl_ppo_diagnostic_stats_reduce.cu — B-10 G3+G4: PPO advantage
+// normalization + surrogate decomposition observability. Consumes 5
+// per-batch scratch arrays written by `ppo_clipped_surrogate.cu` (which
+// gains 5 new pointer params alongside the existing `loss_per_batch[B]`
+// write) and emits 8 ISV slots:
+//
+//   735 RL_PPO_A_NORM_ABS_MAX_INDEX     — max |A_norm|       across B
+//   736 RL_PPO_A_NORM_ABS_MEAN_INDEX    — mean |A_norm|      across B
+//   737 RL_PPO_A_UNNORM_ABS_MAX_INDEX   — max |A_unnorm|     across B
+//   738 RL_PPO_A_UNNORM_ABS_MEAN_INDEX  — mean |A_unnorm|    across B
+//   739 RL_PPO_A_SIGMA_USED_INDEX       — sqrt(isv[612]) — the per-batch
+//                                         std actually applied as divisor
+//                                         in `rl_advantage_normalize.cu`
+//                                         (Schulman 2017 canonical
+//                                         per-batch standardization).
+//   740 RL_PPO_RATIO_DEV_ABS_MEAN_INDEX — mean |ratio - 1|   across B
+//   741 RL_PPO_RATIO_CLIP_RATE_INDEX    — fraction outside [1-ε, 1+ε]
+//                                         (sum of 0/1 flags / B)
+//   742 RL_PPO_L_SURROGATE_INDEX        — mean clipped surrogate
+//                                         (without entropy bonus)
+//
+// Pattern lifted from `rl_bellman_target_saturation_reduce.cu`: single
+// block, grid-stride loop, separate `__shared__` arrays per reduction.
+// Per `pearl_no_atomicadd`: no atomicAdd anywhere. Per
+// `feedback_no_partial_refactor`: the new scratches in
+// `ppo_clipped_surrogate.cu` are written alongside `loss_per_batch`
+// (untouched); `ppo_loss_reduce_b.cu` and `ppo_log_ratio_abs_max_b.cu`
+// continue to operate on their existing inputs.
+//
+// Caller launches with block_dim = next_pow2(B).min(256), grid = (1,1,1),
+// shared bytes = 7 * block_dim * sizeof(float).
+
+#include <cuda_runtime.h>
+#include <math_constants.h>
+
+#define RL_ADV_VAR_PRE_NORM_INDEX            612
+#define RL_PPO_A_NORM_ABS_MAX_INDEX          735
+#define RL_PPO_A_NORM_ABS_MEAN_INDEX         736
+#define RL_PPO_A_UNNORM_ABS_MAX_INDEX        737
+#define RL_PPO_A_UNNORM_ABS_MEAN_INDEX       738
+#define RL_PPO_A_SIGMA_USED_INDEX            739
+#define RL_PPO_RATIO_DEV_ABS_MEAN_INDEX      740
+#define RL_PPO_RATIO_CLIP_RATE_INDEX         741
+#define RL_PPO_L_SURROGATE_INDEX             742
+
+extern "C" __global__ void rl_ppo_diagnostic_stats_reduce(
+    float*       __restrict__ isv,
+    const float* __restrict__ a_norm_per_batch,     // [B] |A_norm|
+    const float* __restrict__ ratio_dev_per_batch,  // [B] |ratio - 1|
+    const float* __restrict__ ratio_clipped_pb,     // [B] {0.0, 1.0}
+    const float* __restrict__ surrogate_per_batch,  // [B] clipped surrogate
+    int                       B
+) {
+    // 5 reductions × block_dim floats. Separate arrays to avoid any
+    // cross-talk that could perturb determinism (per spec §3.4 + §4 V3).
+    // σ_used is a per-step scalar (read once at end from slot 612);
+    // |A_unnorm| stats are reconstructed from |A_norm| × σ_used in the
+    // final write — no per-batch unnorm scratch needed.
+    extern __shared__ float smem[];
+    float* s_an_max = smem;
+    float* s_an_sum = smem +     blockDim.x;
+    float* s_rd_sum = smem + 2 * blockDim.x;
+    float* s_rc_sum = smem + 3 * blockDim.x;
+    float* s_su_sum = smem + 4 * blockDim.x;
+    const int tid = threadIdx.x;
+
+    // Grid-stride per-thread folds.
+    float l_an_max = 0.0f, l_an_sum = 0.0f;
+    float l_rd_sum = 0.0f, l_rc_sum = 0.0f, l_su_sum = 0.0f;
+    for (int b = tid; b < B; b += blockDim.x) {
+        const float an = a_norm_per_batch[b];
+        l_an_max  = fmaxf(l_an_max, an);
+        l_an_sum += an;
+        l_rd_sum += ratio_dev_per_batch[b];
+        l_rc_sum += ratio_clipped_pb[b];
+        l_su_sum += surrogate_per_batch[b];
+    }
+    s_an_max[tid] = l_an_max;
+    s_an_sum[tid] = l_an_sum;
+    s_rd_sum[tid] = l_rd_sum;
+    s_rc_sum[tid] = l_rc_sum;
+    s_su_sum[tid] = l_su_sum;
+    __syncthreads();
+
+    // Power-of-2 tree reduce. blockDim.x is guaranteed power of 2 by caller.
+    for (int stride = blockDim.x / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_an_max[tid]  = fmaxf(s_an_max[tid], s_an_max[tid + stride]);
+            s_an_sum[tid] += s_an_sum[tid + stride];
+            s_rd_sum[tid] += s_rd_sum[tid + stride];
+            s_rc_sum[tid] += s_rc_sum[tid + stride];
+            s_su_sum[tid] += s_su_sum[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float denom = (float)B;
+        const float var_pre_norm = isv[RL_ADV_VAR_PRE_NORM_INDEX];
+        // σ_used = sqrt(var_pre_norm). Guard against tiny negative
+        // residuals from float ε.
+        const float sigma_used   = sqrtf(fmaxf(var_pre_norm, 0.0f));
+        const float a_norm_max   = s_an_max[0];
+        const float a_norm_mean  = s_an_sum[0] / denom;
+        isv[RL_PPO_A_NORM_ABS_MAX_INDEX]     = a_norm_max;
+        isv[RL_PPO_A_NORM_ABS_MEAN_INDEX]    = a_norm_mean;
+        // |A_unnorm| = |A_norm| × σ_used (σ_used is constant across batch
+        // by construction in rl_advantage_normalize); reconstruction
+        // preserves max/mean structure without a per-batch scratch.
+        isv[RL_PPO_A_UNNORM_ABS_MAX_INDEX]   = a_norm_max  * sigma_used;
+        isv[RL_PPO_A_UNNORM_ABS_MEAN_INDEX]  = a_norm_mean * sigma_used;
+        isv[RL_PPO_A_SIGMA_USED_INDEX]       = sigma_used;
+        isv[RL_PPO_RATIO_DEV_ABS_MEAN_INDEX] = s_rd_sum[0] / denom;
+        isv[RL_PPO_RATIO_CLIP_RATE_INDEX]    = s_rc_sum[0] / denom;
+        isv[RL_PPO_L_SURROGATE_INDEX]        = s_su_sum[0] / denom;
+    }
+}

crates/ml-alpha/cuda/rl_ppo_ratio_clamp_controller.cu

@@ -53,9 +53,21 @@
 // Default 10.0 — clamp_max = (1+ε) × this. Seeded by rl_isv_write
 // at init. Tuning lower tightens the importance-ratio bound.
 #define RL_PPO_CLAMP_MARGIN_INDEX          460
-#define PPO_RATIO_CLAMP_MIN_OUT             2.0f
-#define PPO_RATIO_CLAMP_MAX_OUT          1000.0f
-#define WIENER_ALPHA_FLOOR                  0.4f
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// the MIN_OUT floor derives from observed log-ratio variance (Welford
+// triple at slots 630/631/632) rather than the static `2.0f` baseline.
+// The MAX ceiling is ISV-resident at slot 629 so it can be tuned at
+// runtime. The hardcoded `2.0f` survives as an architectural minimum
+// per the spec's "physics-constant" exemption ("don't degenerate to
+// vanilla policy gradient when σ_ratio is tiny").
+#define RL_PPO_RATIO_CLAMP_MAX_ADAPTIVE_INDEX  629
+#define RL_PPO_RATIO_VAR_COUNT_INDEX           630
+#define RL_PPO_RATIO_VAR_M2_INDEX              632
+#define RL_WIENER_ALPHA_FLOOR_INDEX            659
+#define PPO_RATIO_MIN_ABSOLUTE              2.0f    // architectural exemption: vanilla-PG safeguard
+#define PPO_RATIO_MIN_STD_SCALE             3.0f    // adaptive min = max(2.0, 1 + 3σ)
+#define PPO_RATIO_MAX_OVER_MIN_FACTOR       5.0f    // adaptive max ≥ 5× adaptive min
 
 // ─────────────────────────────────────────────────────────────────────
 // rl_ppo_ratio_clamp_controller:
@@ -98,9 +110,25 @@ extern "C" __global__ void rl_ppo_ratio_clamp_controller(
     const float clamp_margin = isv[RL_PPO_CLAMP_MARGIN_INDEX];
     float       target = (1.0f + eps) * clamp_margin;
 
+    // ── Adaptive MIN/MAX from observed log-ratio variance ───────────
+    // Welford sample variance = M² / (count − 1) when count > 1.
+    // Adaptive min: max(2.0, 1 + 3σ_ratio). The 2.0 floor is the
+    // architectural-minimum exemption ("don't degenerate to vanilla
+    // policy gradient") — kept as a #define per the spec. The 3σ scale
+    // gives the clamp window roughly the same coverage of healthy
+    // policy updates as the prior static 2.0 baseline did pre-Phase 4.5.
+    const float ratio_count = isv[RL_PPO_RATIO_VAR_COUNT_INDEX];
+    const float ratio_var = (ratio_count > 1.0f)
+        ? isv[RL_PPO_RATIO_VAR_M2_INDEX] / (ratio_count - 1.0f)
+        : 0.0f;
+    const float ratio_std = sqrtf(ratio_var);
+    const float adaptive_min = fmaxf(PPO_RATIO_MIN_ABSOLUTE,
+                                      1.0f + ratio_std * PPO_RATIO_MIN_STD_SCALE);
+    const float adaptive_max = fmaxf(adaptive_min * PPO_RATIO_MAX_OVER_MIN_FACTOR,
+                                      isv[RL_PPO_RATIO_CLAMP_MAX_ADAPTIVE_INDEX]);
+
     // Permanent floor / ceiling per pearl_blend_formulas_must_have_permanent_floor.
-    target = fmaxf(PPO_RATIO_CLAMP_MIN_OUT,
-                   fminf(target, PPO_RATIO_CLAMP_MAX_OUT));
+    target = fmaxf(adaptive_min, fminf(target, adaptive_max));
 
     // First-observation replace-directly per pearl_first_observation_bootstrap.
     // prev == PPO_RATIO_CLAMP_BOOTSTRAP means "we just bootstrapped last
@@ -113,10 +141,9 @@ extern "C" __global__ void rl_ppo_ratio_clamp_controller(
     }
 
     // Wiener-α blend with floor.
-    const float a   = fmaxf(alpha_step, WIENER_ALPHA_FLOOR);
+    const float a   = fmaxf(alpha_step, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       out = (1.0f - a) * prev + a * target;
 
-    out = fmaxf(PPO_RATIO_CLAMP_MIN_OUT,
-                fminf(out, PPO_RATIO_CLAMP_MAX_OUT));
+    out = fmaxf(adaptive_min, fminf(out, adaptive_max));
     isv[RL_PPO_RATIO_CLAMP_MAX_INDEX] = out;
 }

crates/ml-alpha/cuda/rl_q_distill_lambda_controller.cu

@@ -23,11 +23,27 @@
 #define RL_Q_DISTILL_KL_EMA_INDEX            488
 #define RL_Q_DISTILL_KL_TARGET_INDEX         491
 
-#define MIN_LAMBDA                           0.05f
-#define MAX_LAMBDA                           1.0f
-#define KL_TOLERANCE                         3.0f
-#define LAMBDA_RAMP_RATE                     1.2f
-#define LAMBDA_DECAY_RATE                    0.998f
+// Adaptive controller floors (spec 2026-05-30 Special case Q):
+// hardcoded `MIN_LAMBDA = 0.05f` floor replaced with adaptive bound
+// derived from Welford variance on q_distill_kl_ema. Phase 4.5 reduces
+// KL signal magnitudes which this controller consumes; the "below target"
+// path fires continuously, decaying λ to MIN. Adaptive bound
+// `max(0.001, sqrt(var) × 0.05)` lets λ decay to a level proportional to
+// the actual signal noise rather than the hardcoded 0.05 floor.
+#define RL_Q_DISTILL_KL_VAR_COUNT_INDEX        618
+#define RL_Q_DISTILL_KL_VAR_M2_INDEX           620
+#define RL_Q_DISTILL_LAMBDA_MIN_ADAPTIVE_INDEX 639
+
+// MAX_LAMBDA, KL_TOLERANCE, LAMBDA_RAMP_RATE, LAMBDA_DECAY_RATE are now
+// ISV-driven per the 2026-05-30 clamp-bound extension. ADAPTIVE_MIN_*
+// remain hardcoded — they're new constants from the noise-floor design
+// itself per spec exemption ("not clamp bounds, new pattern constants").
+#define RL_Q_DISTILL_LAMBDA_MAX_INDEX        650
+#define RL_Q_DISTILL_KL_TOLERANCE_INDEX      651
+#define RL_Q_DISTILL_LAMBDA_RAMP_RATE_INDEX  652
+#define RL_Q_DISTILL_LAMBDA_DECAY_RATE_INDEX 653
+#define ADAPTIVE_MIN_ABSOLUTE                0.001f
+#define ADAPTIVE_MIN_STD_SCALE               0.05f
 
 extern "C" __global__ void rl_q_distill_lambda_controller(
     float* __restrict__ isv
@@ -40,13 +56,32 @@ extern "C" __global__ void rl_q_distill_lambda_controller(
 
     if (kl_observed <= 0.0f || kl_target <= 0.0f || lambda <= 0.0f) return;
 
-    const float upper = kl_target * KL_TOLERANCE;
-    const float lower = kl_target / KL_TOLERANCE;
+    // Adaptive MIN bound (spec 2026-05-30 Special case Q): replaces
+    // hardcoded `MIN_LAMBDA = 0.05f`. Welford sample variance =
+    // M² / (count − 1) when count > 1. Adaptive min scales with signal
+    // std so λ can decay proportional to actual KL noise rather than
+    // pegging at an arbitrary 0.05 floor.
+    const float kl_var_count = isv[RL_Q_DISTILL_KL_VAR_COUNT_INDEX];
+    const float kl_var = (kl_var_count > 1.0f)
+        ? isv[RL_Q_DISTILL_KL_VAR_M2_INDEX] / (kl_var_count - 1.0f)
+        : 0.0f;
+    const float kl_std = sqrtf(kl_var);
+    const float adaptive_min = fmaxf(ADAPTIVE_MIN_ABSOLUTE,
+                                      kl_std * ADAPTIVE_MIN_STD_SCALE);
+    isv[RL_Q_DISTILL_LAMBDA_MIN_ADAPTIVE_INDEX] = adaptive_min;
+
+    const float max_lambda        = isv[RL_Q_DISTILL_LAMBDA_MAX_INDEX];
+    const float kl_tolerance      = isv[RL_Q_DISTILL_KL_TOLERANCE_INDEX];
+    const float lambda_ramp_rate  = isv[RL_Q_DISTILL_LAMBDA_RAMP_RATE_INDEX];
+    const float lambda_decay_rate = isv[RL_Q_DISTILL_LAMBDA_DECAY_RATE_INDEX];
+
+    const float upper = kl_target * kl_tolerance;
+    const float lower = kl_target / kl_tolerance;
 
     if (kl_observed > upper) {
-        lambda = fminf(MAX_LAMBDA, lambda * LAMBDA_RAMP_RATE);
+        lambda = fminf(max_lambda, lambda * lambda_ramp_rate);
     } else if (kl_observed < lower) {
-        lambda = fmaxf(MIN_LAMBDA, lambda * LAMBDA_DECAY_RATE);
+        lambda = fmaxf(adaptive_min, lambda * lambda_decay_rate);
     }
 
     isv[RL_Q_DISTILL_LAMBDA_INDEX] = lambda;

crates/ml-alpha/cuda/rl_q_distribution_stats.cu

@@ -0,0 +1,217 @@
+// rl_q_distribution_stats.cu — B-10 G1: Q-distribution informativeness
+// diagnostic. Detects C51 Q-collapse (target → one-hot at center atom
+// under EWMA-narrowed atom support) via Q output STRUCTURE rather than
+// loss magnitude. A bit-flat `l_q ≈ 0.002` is a known false-positive of
+// adaptive-support categorical DQN (per literature 2026-06-01 perplexity:
+// "near-zero categorical cross-entropy under adaptive support is a known
+// Q-collapse symptom"), so we measure Q's information content directly:
+//
+//   * `q_dist_entropy_mean` — mean over (b, a) of −Σ_z p log p (where p
+//     is softmax over Q_N_ATOMS atoms for that action). Near 0 ⇒ Q
+//     concentrates on one atom (could be informative or collapsed-at-edge).
+//     Near ln(Q_N_ATOMS) ≈ 3.045 ⇒ near-uniform Q (information-free).
+//
+//   * `q_value_range_mean` — mean over b of (max_a E_Q(s,a) − min_a E_Q(s,a)).
+//     E_Q is the expected return Σ_z p · atom_value[z]. Range near 0 ⇒
+//     Q has no preference among actions.
+//
+//   * `q_value_abs_max` — per-step max over (b, a) of |E_Q|. Surfaces
+//     whether Q's expected values are scale-consistent with realized
+//     returns or have drifted.
+//
+// Two-kernel pattern per `pearl_no_atomicadd` (no atomicAdd anywhere)
+// and per the B-9 saturation-reduce precedent:
+//   1. `rl_q_distribution_per_batch` — grid (B, 1, 1), block (Q_N_ATOMS, 1, 1).
+//      Each block processes one batch element across all N_ACTIONS actions
+//      sequentially; computes per-action softmax + entropy + E_Q in shared
+//      mem; writes per-batch entropy_mean / range / abs_max to 3 [B]
+//      scratch arrays.
+//   2. `rl_q_distribution_reduce` — single-block tree-reduce over the [B]
+//      scratch arrays; writes ISV slots 730 / 731 / 732.
+//
+// Inputs (online Q logits ONLY — target Q is not consumed by Q-Thompson
+// or Q→π distill, so its informativeness is irrelevant to the cascade
+// we're diagnosing):
+//   q_logits        [B × N_ACTIONS × Q_N_ATOMS] — raw atom logits.
+//   atom_supports   [Q_N_ATOMS]                 — atom value array
+//                                                 (V_MIN + i·Δz, ISV-driven).
+//   B                int                         — batch size.
+//
+// Outputs (per-batch scratch consumed by reducer below):
+//   entropy_per_batch    [B]
+//   range_per_batch      [B]
+//   abs_max_per_batch    [B]
+//
+// Per `feedback_cpu_is_read_only`: no HtoD, no host compute. Per
+// `feedback_no_nvrtc`: pre-compiled cubin. Per
+// `feedback_no_htod_htoh_only_mapped_pinned`: device-only reads/writes.
+
+#include <cuda_runtime.h>
+#include <math_constants.h>
+
+#define Q_N_ATOMS                              21
+#define N_ACTIONS                              11
+
+#define RL_Q_DIST_ENTROPY_MEAN_INDEX           730
+#define RL_Q_VALUE_RANGE_MEAN_INDEX            731
+#define RL_Q_VALUE_ABS_MAX_INDEX               732
+
+// ─────────────────────────────────────────────────────────────────────
+// Per-batch kernel: grid (B, 1, 1), block (Q_N_ATOMS, 1, 1).
+// Each block processes ONE batch element by iterating over all
+// N_ACTIONS actions sequentially (cheap — N_ACTIONS=11). For each
+// action, compute softmax over Q_N_ATOMS atoms (parallel across the
+// 21 threads), then entropy and expected value E_Q. Track running
+// max_a E_Q, min_a E_Q, max_a |E_Q|, and Σ_a entropy in shared mem.
+// Thread 0 writes the 3 per-batch outputs at the end.
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void rl_q_distribution_per_batch(
+    const float* __restrict__ q_logits,           // [B × N_ACTIONS × Q_N_ATOMS]
+    const float* __restrict__ atom_supports,      // [Q_N_ATOMS]
+    int                       B,
+    float*       __restrict__ entropy_per_batch,  // [B]
+    float*       __restrict__ range_per_batch,    // [B]
+    float*       __restrict__ abs_max_per_batch   // [B]
+) {
+    const int batch = blockIdx.x;
+    const int atom  = threadIdx.x;
+    if (batch >= B || atom >= Q_N_ATOMS) return;
+
+    // Shared mem for per-action softmax computation. Same layout as
+    // `bellman_target_projection.cu` (single per-action reduction).
+    __shared__ float s_logits[Q_N_ATOMS];
+    __shared__ float s_softmax[Q_N_ATOMS];
+    __shared__ float s_max;
+    __shared__ float s_sumexp;
+
+    // Per-action accumulators on thread 0; per-block aggregates.
+    __shared__ float s_e_q[N_ACTIONS];
+    __shared__ float s_entropy_sum;
+
+    // Atom value cached once for this block (read-only, all threads).
+    __shared__ float s_atom_value[Q_N_ATOMS];
+    s_atom_value[atom] = atom_supports[atom];
+    if (atom == 0) {
+        s_entropy_sum = 0.0f;
+    }
+    __syncthreads();
+
+    // Iterate over all actions for this batch element.
+    for (int a = 0; a < N_ACTIONS; ++a) {
+        // ── 1. Load logits for (batch, a) into shared mem ─────────────
+        const long long base = (long long)batch * N_ACTIONS * Q_N_ATOMS
+                             + (long long)a   * Q_N_ATOMS;
+        s_logits[atom] = q_logits[base + atom];
+        __syncthreads();
+
+        // ── 2. Softmax over atoms (numerically-stable max-subtract) ───
+        if (atom == 0) {
+            float m = s_logits[0];
+            #pragma unroll
+            for (int z = 1; z < Q_N_ATOMS; ++z) m = fmaxf(m, s_logits[z]);
+            s_max = m;
+        }
+        __syncthreads();
+
+        const float e = expf(s_logits[atom] - s_max);
+        s_softmax[atom] = e;
+        __syncthreads();
+
+        if (atom == 0) {
+            float sum = 0.0f;
+            #pragma unroll
+            for (int z = 0; z < Q_N_ATOMS; ++z) sum += s_softmax[z];
+            s_sumexp = sum;
+        }
+        __syncthreads();
+
+        const float p = s_softmax[atom] / s_sumexp;
+
+        // ── 3. Reduce to E_Q and entropy on thread 0 ──────────────────
+        if (atom == 0) {
+            float e_q = 0.0f;
+            float ent = 0.0f;
+            #pragma unroll
+            for (int z = 0; z < Q_N_ATOMS; ++z) {
+                const float pz = s_softmax[z] / s_sumexp;
+                e_q += pz * s_atom_value[z];
+                // entropy: -p log p; safe for p>0 since softmax is positive.
+                if (pz > 1e-30f) {
+                    ent -= pz * logf(pz);
+                }
+            }
+            s_e_q[a]       = e_q;
+            s_entropy_sum += ent;
+        }
+        __syncthreads();
+    }
+
+    // ── 4. Per-batch aggregates: thread 0 writes scratch ──────────────
+    if (atom == 0) {
+        float max_q   = s_e_q[0];
+        float min_q   = s_e_q[0];
+        float abs_max = fabsf(s_e_q[0]);
+        #pragma unroll
+        for (int a = 1; a < N_ACTIONS; ++a) {
+            const float q = s_e_q[a];
+            max_q   = fmaxf(max_q, q);
+            min_q   = fminf(min_q, q);
+            abs_max = fmaxf(abs_max, fabsf(q));
+        }
+        // Per-batch entropy averaged across actions (so 0..ln(Q_N_ATOMS)
+        // range is preserved; the cross-batch reducer averages across B).
+        entropy_per_batch[batch] = s_entropy_sum / (float)N_ACTIONS;
+        range_per_batch[batch]   = max_q - min_q;
+        abs_max_per_batch[batch] = abs_max;
+    }
+}
+
+// ─────────────────────────────────────────────────────────────────────
+// Cross-batch reducer: single block, grid-stride loop. Writes the 3
+// per-step diag values to ISV. Pattern lifted from
+// `rl_bellman_target_saturation_reduce.cu`.
+//
+// Caller passes block_dim = next_pow2(B).min(256), grid = (1, 1, 1),
+// shared bytes = 3 * block_dim * sizeof(float).
+// ─────────────────────────────────────────────────────────────────────
+extern "C" __global__ void rl_q_distribution_reduce(
+    float*       __restrict__ isv,
+    const float* __restrict__ entropy_per_batch,
+    const float* __restrict__ range_per_batch,
+    const float* __restrict__ abs_max_per_batch,
+    int                       B
+) {
+    extern __shared__ float smem[];
+    float* s_ent_sum = smem;
+    float* s_rng_sum = smem +     blockDim.x;
+    float* s_abs_max = smem + 2 * blockDim.x;
+    const int tid = threadIdx.x;
+
+    float l_ent = 0.0f, l_rng = 0.0f;
+    float l_abs = -CUDART_INF_F;
+    for (int b = tid; b < B; b += blockDim.x) {
+        l_ent += entropy_per_batch[b];
+        l_rng += range_per_batch[b];
+        l_abs  = fmaxf(l_abs, abs_max_per_batch[b]);
+    }
+    s_ent_sum[tid] = l_ent;
+    s_rng_sum[tid] = l_rng;
+    s_abs_max[tid] = l_abs;
+    __syncthreads();
+
+    for (int stride = blockDim.x / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_ent_sum[tid] += s_ent_sum[tid + stride];
+            s_rng_sum[tid] += s_rng_sum[tid + stride];
+            s_abs_max[tid]  = fmaxf(s_abs_max[tid], s_abs_max[tid + stride]);
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float denom = (float)B;
+        isv[RL_Q_DIST_ENTROPY_MEAN_INDEX] = s_ent_sum[0] / denom;
+        isv[RL_Q_VALUE_RANGE_MEAN_INDEX]  = s_rng_sum[0] / denom;
+        isv[RL_Q_VALUE_ABS_MAX_INDEX]     = s_abs_max[0];
+    }
+}

crates/ml-alpha/cuda/rl_q_pi_distill_grad.cu

@@ -16,6 +16,12 @@
 
 #define N_ACTIONS                            11
 #define Q_N_ATOMS                            21
+// Action enum mirrors crates/ml-alpha/src/rl/common.rs (Action enum).
+// Used by the Phase 7a F2-diag per-batch reduction at end-of-kernel
+// (no-op-set baseline = max E_Q over {Hold, TrailTighten, TrailLoosen}).
+#define ACTION_HOLD                          2
+#define ACTION_TRAIL_TIGHTEN                 7
+#define ACTION_TRAIL_LOOSEN                  8
 #define RL_Q_DISTILL_LAMBDA_INDEX            486
 #define RL_Q_DISTILL_TEMPERATURE_INDEX       487
 #define RL_Q_DISTILL_KL_EMA_INDEX            488
@@ -24,6 +30,23 @@
 #define RL_SAC_ALPHA_INDEX                   581
 #define RL_SAC_ENTROPY_TARGET_INDEX          582
 #define RL_ACTION_ENTROPY_EMA_INDEX           583
+// Phase 7a F2 (2026-06-04) — Q-centered distill target gates.
+// Mirrored from crates/ml-alpha/src/rl/isv_slots.rs. The diag block
+// below reads these to compute the no-op-set baseline regardless of
+// whether the F2 mechanism is wired up to alter the gradient — pure
+// observability (Task 1.5 is diag-only; the F2 hinge in pi_target is
+// a separate task).
+#define RL_F2_DISTILL_CENTERED_ENABLED_INDEX 817
+#define RL_F2_DISTILL_NOOP_SET_MODE_INDEX    818
+// B-10 (2026-06-01) G2 — Q→π distill effectiveness observability.
+// Read-only emits from the existing batch-0 diagnostic block below; no
+// controller perturbation (RL_Q_DISTILL_LAMBDA_INDEX 486 and
+// RL_Q_DISTILL_TEMPERATURE_INDEX 487 writes are untouched). When π_target
+// = softmax(E_Q / τ) is near-uniform (entropy → ln(N_ACTIONS)), the
+// distill term is pure max-entropy regularization regardless of τ —
+// confirmed by 2026-06-01 perplexity research on Q→policy distillation.
+#define RL_Q_DISTILL_TARGET_ENTROPY_MEAN_INDEX  733
+#define RL_Q_DISTILL_PI_ENTROPY_DIFF_INDEX      734
 #define AGREE_EMA_ALPHA                      0.05f
 #define SAC_STEP_RAMP                        0.01f
 #define SAC_STEP_DECAY                       0.0001f
@@ -36,6 +59,15 @@ extern "C" __global__ void rl_q_pi_distill_grad(
     const float* __restrict__ atom_supports,   // [Q_N_ATOMS]
     float*       __restrict__ isv,             // ISV bus (RW)
     float*       __restrict__ pi_grad_logits,  // [B × N_ACTIONS] WRITE (buffer pre-zeroed)
+    // Phase 7a F2-diag (2026-06-04) — per-batch scratch buffers
+    // populated by the single-thread reduction at the END of the
+    // kernel. All length [B]; populated by the `a == 0` thread of each
+    // block (one block per batch → no cross-block write race). Trainer
+    // aggregates host-side at diag emit. NO atomicAdd anywhere.
+    float*       __restrict__ f2_diag_baseline_per_b,      // baseline per batch
+    float*       __restrict__ f2_diag_adv_max_per_b,       // max hinged per batch
+    float*       __restrict__ f2_diag_hinge_zero_per_b,    // fraction-zeroed per batch
+    int*         __restrict__ f2_diag_target_argmax_per_b, // argmax π_target per batch
     int                       B
 ) {
     const int b = blockIdx.x;
@@ -66,19 +98,74 @@ extern "C" __global__ void rl_q_pi_distill_grad(
     s_eq[a] = (sum_exp > 1e-9f) ? (e_q / sum_exp) : 0.0f;
     __syncthreads();
 
-    // ── Step 2: π_target = softmax(E_Q / τ) ─────────────────────
+    // ── Step 2: π_target ─────────────────────────────────────────
+    // Phase 7a F2 (2026-06-04): if RL_F2_DISTILL_CENTERED_ENABLED_INDEX
+    // > 0.5, compute the Q-centered hinged-advantage target
+    //   π_target(a) ∝ softmax( max(0, E_Q(a) − baseline) / τ )
+    // where baseline = max E_Q over the no-op set selected by
+    // RL_F2_DISTILL_NOOP_SET_MODE_INDEX (mode 0 = {Hold, TrailTighten,
+    // TrailLoosen}, mode 1 = {Hold} only). Else fall back to legacy
+    // softmax(E_Q/τ) target for bit-equality with HEAD 0463e44e0.
+    //
+    // Per spec docs/superpowers/specs/2026-06-04-bellman-target-foundation-reshape.md
+    // §3.2 + §4.2: the hinge zeroes Open mass when E_Q(Open) ≤ baseline
+    // (preserves surfer-style patience), and gives positive mass when
+    // E_Q(Open) > baseline (preserves surfer-style commit on detected
+    // edge). Composes with band mask (band touches sampled actions; F2
+    // touches Q-distill target — disjoint pipelines).
     __shared__ float s_pi_target[N_ACTIONS];
     if (a == 0) {
-        float max_eq = s_eq[0];
-        for (int i = 1; i < N_ACTIONS; ++i) max_eq = fmaxf(max_eq, s_eq[i]);
+        const float f2_enabled = isv[RL_F2_DISTILL_CENTERED_ENABLED_INDEX];
         const float tau_safe = fmaxf(tau, 1e-3f);
-        float total = 0.0f;
-        for (int i = 0; i < N_ACTIONS; ++i) {
-            s_pi_target[i] = expf((s_eq[i] - max_eq) / tau_safe);
-            total += s_pi_target[i];
+
+        if (f2_enabled > 0.5f) {
+            // F2 hinged-advantage target.
+            const float mode = isv[RL_F2_DISTILL_NOOP_SET_MODE_INDEX];
+
+            // Compute baseline = max E_Q over no-op set.
+            float baseline;
+            if (mode > 0.5f && mode <= 1.5f) {
+                // Mode 1: Hold-only baseline.
+                baseline = s_eq[ACTION_HOLD];
+            } else {
+                // Mode 0 (default): static set {Hold, TrailTighten, TrailLoosen}.
+                baseline = fmaxf(s_eq[ACTION_HOLD],
+                                  fmaxf(s_eq[ACTION_TRAIL_TIGHTEN],
+                                        s_eq[ACTION_TRAIL_LOOSEN]));
+            }
+
+            // hinged[a] = max(0, E_Q(a) − baseline).
+            // softmax over hinged values, scaled by 1/τ.
+            // Numerical stability: hinged ≥ 0 by construction, so the
+            // max hinged value is a finite, non-negative number. We
+            // subtract it before exp to keep magnitudes bounded.
+            float max_hinge = 0.0f;
+            for (int i = 0; i < N_ACTIONS; ++i) {
+                const float h = fmaxf(0.0f, s_eq[i] - baseline);
+                if (h > max_hinge) max_hinge = h;
+            }
+            float total = 0.0f;
+            for (int i = 0; i < N_ACTIONS; ++i) {
+                const float h = fmaxf(0.0f, s_eq[i] - baseline);
+                s_pi_target[i] = expf((h - max_hinge) / tau_safe);
+                total += s_pi_target[i];
+            }
+            const float inv = (total > 1e-9f) ? (1.0f / total)
+                                              : (1.0f / (float)N_ACTIONS);
+            for (int i = 0; i < N_ACTIONS; ++i) s_pi_target[i] *= inv;
+        } else {
+            // Legacy path (pre-F2, bit-equality with HEAD 0463e44e0).
+            float max_eq = s_eq[0];
+            for (int i = 1; i < N_ACTIONS; ++i) max_eq = fmaxf(max_eq, s_eq[i]);
+            float total = 0.0f;
+            for (int i = 0; i < N_ACTIONS; ++i) {
+                s_pi_target[i] = expf((s_eq[i] - max_eq) / tau_safe);
+                total += s_pi_target[i];
+            }
+            const float inv = (total > 1e-9f) ? (1.0f / total)
+                                              : (1.0f / (float)N_ACTIONS);
+            for (int i = 0; i < N_ACTIONS; ++i) s_pi_target[i] *= inv;
         }
-        const float inv = (total > 1e-9f) ? (1.0f / total) : (1.0f / (float)N_ACTIONS);
-        for (int i = 0; i < N_ACTIONS; ++i) s_pi_target[i] *= inv;
     }
     __syncthreads();
 
@@ -116,16 +203,56 @@ extern "C" __global__ void rl_q_pi_distill_grad(
     // Distillation: push π toward Q_target's ranking
     const float grad_distill = lambda * (pi_a - s_pi_target[a]);
 
-    // SAC entropy: push π toward higher entropy
-    // ∂(-H)/∂logit_a = π(a) × (log π(a) + 1 + H)
-    // We want to MAXIMIZE H, so gradient = -∂(-H)/∂logit = -π(a)×(log π(a) + 1 + H)
-    const float grad_entropy = -alpha * pi_a * (log_pi_a + 1.0f + s_entropy);
+    // SAC entropy: push π toward higher entropy.
+    // Loss term: L_α = -α · H(π), so ∂L_α/∂logit_a = -α · ∂H/∂logit_a.
+    // Derivation: H(π) = -Σ_i π_i log π_i, and ∂π_i/∂logit_a = π_i (δ_{i,a} - π_a). Then:
+    //   ∂H/∂logit_a = -Σ_i (∂π_i/∂logit_a)(log π_i + 1)
+    //              = -Σ_i π_i (δ_{i,a} - π_a)(log π_i + 1)
+    //              = -π_a (log π_a + 1) + π_a Σ_i π_i (log π_i + 1)
+    //              = -π_a (log π_a + 1) + π_a (-H + 1)
+    //              = -π_a (log π_a + H)
+    // Hence the gradient-descent update on L_α uses
+    //   ∂L_α/∂logit_a = -α · ∂H/∂logit_a = α · π_a · (log π_a + H)
+    // and the WRITE here is the *negative* update step (the kernel
+    // accumulates the entropy-bonus *into* `pi_grad_logits` for the
+    // optimizer's descent step, which means we MUST write
+    // -α · π_a · (log π_a + H) so that the optimizer subtracts the bonus
+    // direction).
+    //
+    // Phase 5 (2026-06-04) fix: previous formula had a spurious `+ 1.0f`
+    // term — the literature form `(log π + 1 + H)` is the entropy of the
+    // softmax *output* w.r.t. the softmax *input* (the "log-trick"
+    // identity), NOT the entropy gradient. The bug made the per-action
+    // entropy gradient 3× too aggressive on dominant actions and 2-3×
+    // too weak on low-prob actions — verified analytically against
+    // closed-form symbolic differentiation.
+    const float grad_entropy = -alpha * pi_a * (log_pi_a + s_entropy);
 
     const int pi_idx = b * N_ACTIONS + a;
     pi_grad_logits[pi_idx] += (grad_distill + grad_entropy) / (float)B;
 
     // ── Step 5: diagnostics + SAC α auto-tune (block 0 only) ────
     if (b == 0 && a == 0) {
+        // B-10 G2: emit Q-distill target entropy + (target − π) entropy diff.
+        // Reads existing s_pi_target / s_pi_new (computed for batch 0 above).
+        // Pure observability — batch-0 sample is consistent with this
+        // kernel's existing diagnostic pattern (KL/qpa/SAC-α emits below
+        // are also batch-0 only). At b=1024 with stationary-step data
+        // batch 0 is representative; spec name `_MEAN` is the cluster-side
+        // semantic, the kernel emit is the per-step sample. Local names
+        // are `h_t_b10` / `h_p_b10` to avoid the existing `h_target` /
+        // SAC-α scope conflict below.
+        float h_t_b10 = 0.0f, h_p_b10 = 0.0f;
+        #pragma unroll
+        for (int i = 0; i < N_ACTIONS; ++i) {
+            const float pt = s_pi_target[i];
+            const float pn = s_pi_new[i];
+            if (pt > 1e-12f) h_t_b10 -= pt * logf(pt);
+            if (pn > 1e-12f) h_p_b10 -= pn * logf(pn);
+        }
+        isv[RL_Q_DISTILL_TARGET_ENTROPY_MEAN_INDEX] = h_t_b10;
+        isv[RL_Q_DISTILL_PI_ENTROPY_DIFF_INDEX]     = h_t_b10 - h_p_b10;
+
         // KL EMA for distillation controller
         float kl = 0.0f;
         for (int i = 0; i < N_ACTIONS; ++i) {
@@ -181,4 +308,57 @@ extern "C" __global__ void rl_q_pi_distill_grad(
         float new_tau = tau * expf(step * h_error);
         isv[RL_Q_DISTILL_TEMPERATURE_INDEX] = fmaxf(TAU_DISTILL_MIN, fminf(new_tau, TAU_DISTILL_MAX));
     }
+
+    // ── Phase 7a F2-diag: per-batch mechanism counters ───────────
+    // Only thread a == 0 writes (single-thread reduction inside the
+    // block — uses the s_eq + s_pi_target shared memory already
+    // computed above; no race, no atomicAdd). The trainer reduces
+    // these [B]-sized buffers host-side at diag emit.
+    //
+    // The baseline is computed for diag observability REGARDLESS of
+    // whether the F2 hinge is wired into pi_target (Task 1.5 is diag-
+    // only). Mode selects which action subset forms the no-op set:
+    //   mode 1 → {Hold}
+    //   mode 0 or other (default) → {Hold, TrailTighten, TrailLoosen}
+    if (a == 0) {
+        const int batch = (int)blockIdx.x;
+        if (batch < B) {
+            const float mode_diag = isv[RL_F2_DISTILL_NOOP_SET_MODE_INDEX];
+            float baseline_diag;
+            if (mode_diag > 0.5f && mode_diag <= 1.5f) {
+                baseline_diag = s_eq[ACTION_HOLD];
+            } else {
+                baseline_diag = fmaxf(s_eq[ACTION_HOLD],
+                                       fmaxf(s_eq[ACTION_TRAIL_TIGHTEN],
+                                             s_eq[ACTION_TRAIL_LOOSEN]));
+            }
+            f2_diag_baseline_per_b[batch] = baseline_diag;
+
+            // max hinged advantage across actions for this batch +
+            // count of actions where the hinge clamped to zero.
+            float adv_max = 0.0f;
+            int   n_zero  = 0;
+            for (int i = 0; i < N_ACTIONS; ++i) {
+                const float h = fmaxf(0.0f, s_eq[i] - baseline_diag);
+                if (h > adv_max) adv_max = h;
+                if (h <= 0.0f) ++n_zero;
+            }
+            f2_diag_adv_max_per_b[batch]    = adv_max;
+            f2_diag_hinge_zero_per_b[batch] =
+                (float)n_zero / (float)N_ACTIONS;
+
+            // argmax of s_pi_target — already computed by Step 2 above
+            // (legacy softmax(E_Q/τ); when the F2 hinge is wired this
+            // becomes softmax(max(0, E_Q − baseline)/τ)).
+            int   t_arg = 0;
+            float t_max = s_pi_target[0];
+            for (int i = 1; i < N_ACTIONS; ++i) {
+                if (s_pi_target[i] > t_max) {
+                    t_max = s_pi_target[i];
+                    t_arg = i;
+                }
+            }
+            f2_diag_target_argmax_per_b[batch] = t_arg;
+        }
+    }
 }

crates/ml-alpha/cuda/rl_regime_flat_count.cu

@@ -0,0 +1,32 @@
+// rl_regime_flat_count.cu — block-reduce per-account flat count.
+//
+// Spec: docs/superpowers/specs/2026-05-31-regime-observer-design.md v3
+//
+// Counts how many of `b_size` accounts have `lots[b] == 0` (i.e. are flat).
+// Output: single int written to `flat_count_out[0]`.
+//
+// Per feedback_no_atomicadd: shared-mem block reduction, no atomics.
+// Caller must launch with Block=(BLOCK_X,1,1) and smem = BLOCK_X*sizeof(int).
+// The tree-reduce loop requires BLOCK_X to be a power of two.
+
+#define BLOCK_X 256  // must match the launch block size and be a power of 2
+
+extern "C" __global__ void rl_regime_flat_count(
+    const int* __restrict__ lots,
+    int* __restrict__ flat_count_out,
+    int b_size
+) {
+    extern __shared__ int s_count[];
+    const int tid = threadIdx.x;
+    int sum = 0;
+    for (int b = tid; b < b_size; b += blockDim.x) {
+        sum += (lots[b] == 0) ? 1 : 0;
+    }
+    s_count[tid] = sum;
+    __syncthreads();
+    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
+        if (tid < s) s_count[tid] += s_count[tid + s];
+        __syncthreads();
+    }
+    if (tid == 0) flat_count_out[0] = s_count[0];
+}

crates/ml-alpha/cuda/rl_regime_observer.cu

@@ -0,0 +1,119 @@
+// rl_regime_observer.cu — unified state-machine for risk-stack controllers.
+//
+// Spec: docs/superpowers/specs/2026-05-31-regime-observer-design.md v3
+// Pearls:
+//   - [[pearl_kelly_trade_stream_death]] — empirical motivation
+//   - [[pearl_dead_signal_resurrection_discipline]] — meta-principle
+//
+// Per feedback_no_atomicadd: single-thread single-block, no atomics.
+// Per feedback_cpu_is_read_only: pure device kernel.
+// Per feedback_nvidia_grade_perf_for_kernels: no host branches in capture.
+//
+// Launch: Grid=(1,1,1), Block=(1,1,1), smem=0.
+
+// ─── ISV slot indices (mirror Rust constants from isv_slots.rs) ─────
+#define RL_KELLY_FRACTION_INDEX                  676
+#define RL_COOLDOWN_REMAINING_STEPS_INDEX        668
+#define RL_SESSION_PNL_WORST_INDEX               684
+
+#define RL_REGIME_DEAD_ZONE_FLAG_INDEX           696
+#define RL_REGIME_DEAD_ZONE_DURATION_INDEX       697
+#define RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX   698
+#define RL_REGIME_RECOVERY_FACTOR_INDEX          699
+#define RL_REGIME_SESSION_PNL_VARIANCE_EMA_INDEX 700
+#define RL_REGIME_TAIL_EVENT_RECENCY_INDEX       701
+#define RL_REGIME_SESSION_PNL_VAR_M2_INDEX       702
+#define RL_REGIME_SESSION_PNL_VAR_MEAN_INDEX     703
+#define RL_REGIME_SESSION_PNL_VAR_COUNT_INDEX    704
+#define RL_REGIME_PREV_WORST_PNL_INDEX           705
+#define RL_KELLY_EPS_RECOVERY_LIVE_INDEX         706
+#define RL_KELLY_EPS_RECOVERY_MIN_INDEX          707
+#define RL_KELLY_EPS_RECOVERY_MAX_INDEX          708
+#define RL_KELLY_EPS_RECOVERY_N_RECOVERY_INDEX   709
+#define RL_REGIME_DEAD_ZONE_MAX_DURATION_INDEX   710
+#define RL_REGIME_TAIL_SIGMA_THRESHOLD_INDEX     713
+
+extern "C" __global__ void rl_regime_observer(
+    float* __restrict__ isv,
+    const int* __restrict__ flat_count_d,
+    int b_size
+) {
+    if (threadIdx.x != 0 || blockIdx.x != 0) return;
+
+    // ─── Phase 1: dead-zone detection ──────────────────────
+    // kelly==0.0f: analytic Kelly clamp writes exactly 0.0 when fraction ≤ 0
+    //   (see rl_kelly_fraction_controller). Exact equality is the intended test.
+    // cooldown==0.0f: integer-valued step counter stored as float; exact 0 is
+    //   the only safe comparison point.
+    const float kelly        = isv[RL_KELLY_FRACTION_INDEX];           // prior-step value
+    const float cooldown     = isv[RL_COOLDOWN_REMAINING_STEPS_INDEX];
+    const int   flat_count   = flat_count_d[0];
+
+    const int dead_zone = (kelly == 0.0f)
+                       && (flat_count == b_size)
+                       && (cooldown == 0.0f) ? 1 : 0;
+
+    isv[RL_REGIME_DEAD_ZONE_FLAG_INDEX] = (float)dead_zone;
+
+    // Duration counter
+    float duration = isv[RL_REGIME_DEAD_ZONE_DURATION_INDEX];
+    if (dead_zone) duration += 1.0f; else duration = 0.0f;
+    isv[RL_REGIME_DEAD_ZONE_DURATION_INDEX] = duration;
+
+    // Safety net: timeout flag fires if dead-zone persists past MAX_DURATION
+    const float max_dur = isv[RL_REGIME_DEAD_ZONE_MAX_DURATION_INDEX];
+    const int timeout = (duration > max_dur) ? 1 : 0;
+    isv[RL_REGIME_DEAD_ZONE_TIMEOUT_FLAG_INDEX] = (float)timeout;
+
+    // ─── Phase 2: session_pnl_change Welford variance ──────
+    const float worst_now  = isv[RL_SESSION_PNL_WORST_INDEX];
+    const float worst_prev = isv[RL_REGIME_PREV_WORST_PNL_INDEX];
+    const float dx         = worst_now - worst_prev;
+    isv[RL_REGIME_PREV_WORST_PNL_INDEX] = worst_now;
+
+    float mean   = isv[RL_REGIME_SESSION_PNL_VAR_MEAN_INDEX];
+    float m2     = isv[RL_REGIME_SESSION_PNL_VAR_M2_INDEX];
+    float count  = isv[RL_REGIME_SESSION_PNL_VAR_COUNT_INDEX];
+
+    // Skip update on bootstrap (both zero)
+    if (worst_now != 0.0f || worst_prev != 0.0f) {
+        count += 1.0f;
+        const float delta  = dx - mean;
+        mean += delta / count;
+        const float delta2 = dx - mean;
+        m2 += delta * delta2;
+        isv[RL_REGIME_SESSION_PNL_VAR_MEAN_INDEX]  = mean;
+        isv[RL_REGIME_SESSION_PNL_VAR_M2_INDEX]    = m2;
+        isv[RL_REGIME_SESSION_PNL_VAR_COUNT_INDEX] = count;
+        const float variance = (count > 1.0f) ? (m2 / (count - 1.0f)) : 0.0f;
+        isv[RL_REGIME_SESSION_PNL_VARIANCE_EMA_INDEX] = variance;
+    }
+
+    // ─── Phase 3: tail-event detection (3σ threshold) ──────
+    // `count` is intentionally reused below from Phase 2 (in-register value
+    // post-conditional-increment); no re-read from ISV needed.
+    const float var       = isv[RL_REGIME_SESSION_PNL_VARIANCE_EMA_INDEX];
+    const float sigma_thr = isv[RL_REGIME_TAIL_SIGMA_THRESHOLD_INDEX];
+    const float sigma     = sqrtf(var);
+
+    // Require count >= 10 before tail detection. Statistical floor — Welford
+    // sample variance is undefined for N<2 and noisy for N<10; exempt from
+    // ISV-promotion per "physics/math constants" rule.
+    const int sufficient_count = (count >= 10.0f) ? 1 : 0;
+    const int is_tail = sufficient_count && (sigma > 0.0f) && (fabsf(dx) > sigma_thr * sigma);
+
+    float recency = isv[RL_REGIME_TAIL_EVENT_RECENCY_INDEX];
+    if (is_tail) recency = 0.0f; else recency += 1.0f;
+    isv[RL_REGIME_TAIL_EVENT_RECENCY_INDEX] = recency;
+
+    // ─── Phase 4: emit recovery_factor and eps_recovery_live (issue #9, drift-free) ──
+    const float n_recovery = isv[RL_KELLY_EPS_RECOVERY_N_RECOVERY_INDEX];
+    const float eps_min    = isv[RL_KELLY_EPS_RECOVERY_MIN_INDEX];
+    const float eps_max    = isv[RL_KELLY_EPS_RECOVERY_MAX_INDEX];
+
+    const float recovery_factor = fminf(1.0f, recency / fmaxf(n_recovery, 1.0f));
+    const float eps_live        = eps_min + (eps_max - eps_min) * recovery_factor;
+
+    isv[RL_REGIME_RECOVERY_FACTOR_INDEX]      = recovery_factor;
+    isv[RL_KELLY_EPS_RECOVERY_LIVE_INDEX]     = eps_live;
+}

crates/ml-alpha/cuda/rl_reward_clamp_controller.cu

@@ -88,25 +88,34 @@
 #define RL_NEG_SCALED_REWARD_MAX_INDEX            489
 #define RL_NEG_SCALED_REWARD_MAX_EMA_INDEX        490
 
-#define MIN_WIN                  1.0f
-#define MIN_RATIO                1.0f      // no inverted asymmetry (loss never < win)
-#define MAX_RATIO                3.0f      // no worse than original loss-aversion
-#define V_BOUND_FLOOR            1.0f      // |V_MIN| and V_MAX both ≥ 1.0
-#define V_BOUND_EWMA_ALPHA       0.001f    // slow — half-life ~700 steps
-#define WIENER_ALPHA_FLOOR       0.4f
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// every prior `#define` clamp-bound constant becomes ISV-driven so it can
+// be tuned at runtime via re-seed instead of recompile. Defaults preserve
+// the historic behaviour exactly.
+#define RL_REWARD_CLAMP_V_BOUND_FLOOR_INDEX          633
+#define RL_REWARD_CLAMP_V_BOUND_EWMA_ALPHA_INDEX     634
+#define RL_REWARD_CLAMP_MIN_WIN_INDEX                635
+#define RL_REWARD_CLAMP_MIN_RATIO_INDEX              636
+#define RL_REWARD_CLAMP_MAX_RATIO_INDEX              637
+#define RL_REWARD_CLAMP_MIN_MARGIN_INDEX             654
+#define RL_REWARD_CLAMP_MAX_MARGIN_INDEX             655
+#define RL_REWARD_CLAMP_MARGIN_TOLERANCE_INDEX       656
+#define RL_REWARD_CLAMP_MARGIN_ADJUST_RATE_INDEX     657
+#define RL_REWARD_CLAMP_CLIP_RATE_EMA_ALPHA_INDEX    658
+#define RL_WIENER_ALPHA_FLOOR_INDEX                  659
 
-// MARGIN Schulman bounded-step bounds + adjust rate per
-// `pearl_multiplicative_controllers_need_bounded_step_and_noise_floor`.
-// TOLERANCE=1.5 → dead-zone is [target/1.5, target×1.5] = [0.033, 0.075];
-// ADJUST_RATE=1.2 → MARGIN moves by ≤20% per controller call (one per
-// trainer step). Bounds [MIN_MARGIN=1.0, MAX_MARGIN=5.0] — MIN preserves
-// the initial passthrough behaviour; MAX × (mean pos_max_ema≈3-5) →
-// WIN_eff up to ~15-25 which is well within MAX_WIN=50 ceiling.
-#define MIN_MARGIN               1.0f
-#define MAX_MARGIN               5.0f
-#define MARGIN_TOLERANCE         1.5f
-#define MARGIN_ADJUST_RATE       1.2f
-#define CLIP_RATE_EMA_ALPHA      0.05f
+// pos_max_ema cold-start redesign (2026-05-31 B-2 spec). Growth cap is
+// ISV-driven (was `#define POS_MAX_EMA_MAX_GROWTH_PER_STEP 1.5f`) per
+// `feedback_isv_for_adaptive_bounds`. Two slots:
+//   718: base cap value (√1.5 ≈ 1.225 nets ~1.5×/step under twice-per-step invocation)
+//   719: adaptive CV-gain (0 = disabled; >0 enables Welford-CV-driven cap relaxation)
+#define RL_POS_MAX_EMA_GROWTH_CAP_BASE_INDEX    718
+#define RL_POS_MAX_EMA_GROWTH_CAP_CV_GAIN_INDEX 719
+// Welford triplet for RL_REWARD_MAGNITUDE_EMA_INDEX (used to compute signal CV
+// for adaptive layer). Slots from rl_signal_variance_update wiring.
+#define RL_REWARD_MAG_VAR_COUNT_INDEX  615
+#define RL_REWARD_MAG_VAR_MEAN_INDEX   616
+#define RL_REWARD_MAG_VAR_M2_INDEX     617
 
 extern "C" __global__ void rl_reward_clamp_controller(
     float* __restrict__ isv,
@@ -114,6 +123,21 @@ extern "C" __global__ void rl_reward_clamp_controller(
 ) {
     if (threadIdx.x != 0 || blockIdx.x != 0) return;
 
+    // ── ISV-driven design constants (spec 2026-05-30) ──
+    // Loaded once at the top of the kernel so they're consistent across
+    // all sub-controllers (EMA → MARGIN → RATIO → C51 span) within this
+    // step. Default values preserve historic behaviour exactly.
+    const float v_bound_floor       = isv[RL_REWARD_CLAMP_V_BOUND_FLOOR_INDEX];
+    const float v_bound_ewma_alpha  = isv[RL_REWARD_CLAMP_V_BOUND_EWMA_ALPHA_INDEX];
+    const float min_ratio_isv       = isv[RL_REWARD_CLAMP_MIN_RATIO_INDEX];
+    const float max_ratio_isv       = isv[RL_REWARD_CLAMP_MAX_RATIO_INDEX];
+    const float min_margin_isv      = isv[RL_REWARD_CLAMP_MIN_MARGIN_INDEX];
+    const float max_margin_isv      = isv[RL_REWARD_CLAMP_MAX_MARGIN_INDEX];
+    const float margin_tolerance    = isv[RL_REWARD_CLAMP_MARGIN_TOLERANCE_INDEX];
+    const float margin_adjust_rate  = isv[RL_REWARD_CLAMP_MARGIN_ADJUST_RATE_INDEX];
+    const float clip_rate_ema_alpha = isv[RL_REWARD_CLAMP_CLIP_RATE_EMA_ALPHA_INDEX];
+    const float wiener_floor        = isv[RL_WIENER_ALPHA_FLOOR_INDEX];
+
     const float pos_max = isv[RL_POS_SCALED_REWARD_MAX_INDEX];
     const float ema_prev = isv[RL_POS_SCALED_REWARD_MAX_EMA_INDEX];
 
@@ -131,14 +155,41 @@ extern "C" __global__ void rl_reward_clamp_controller(
     // Fix: pos_max=0 means "no signal this step," not "win magnitude
     // is zero." Skip EMA updates during dry spells; the EMA retains
     // the last winning-period estimate until the next observation.
+    // ── Adaptive growth cap (2026-05-31 B-2 spec, ISV-driven per
+    //    feedback_isv_for_adaptive_bounds). When cv_gain=0, falls back to
+    //    fixed base. Non-zero cv_gain enables Welford-CV-driven relaxation:
+    //      stable regime (CV→0): growth_cap = base (tight)
+    //      volatile regime (CV→1): growth_cap = base + cv_gain (loose)
+    const float growth_base    = isv[RL_POS_MAX_EMA_GROWTH_CAP_BASE_INDEX];
+    const float growth_cv_gain = isv[RL_POS_MAX_EMA_GROWTH_CAP_CV_GAIN_INDEX];
+    float growth_cap = growth_base;
+    if (growth_cv_gain > 0.0f) {
+        const float wf_count = isv[RL_REWARD_MAG_VAR_COUNT_INDEX];
+        if (wf_count > 1.0f) {
+            const float wf_m2   = isv[RL_REWARD_MAG_VAR_M2_INDEX];
+            const float wf_mean = isv[RL_REWARD_MAG_VAR_MEAN_INDEX];
+            const float wf_var  = wf_m2 / (wf_count - 1.0f);
+            const float wf_cv   = (wf_mean > 1e-6f) ? sqrtf(wf_var) / wf_mean : 0.0f;
+            growth_cap = growth_base + growth_cv_gain * fminf(wf_cv, 1.0f);
+        }
+    }
+
+    // ── Single uniform update rule (2026-05-31 B-2 spec §3.3). The
+    //    first-observation branch `if (ema_prev == 0.0f) ema_new = pos_max;`
+    //    was REMOVED — it let a single cold-start fat-tail observation seed
+    //    pos_max_ema at unbounded magnitude (jnct8 step 5: pos_ema=879
+    //    directly from first positive reward). EMA slots are now bootstrapped
+    //    to MIN_WIN=1.0 in `with_controllers_bootstrapped`, so ema_prev is
+    //    never 0 at run start. Cold-start adaptation is geometric at
+    //    growth_cap per invocation (~1.5×/step under twice-per-step invocation
+    //    → ~30 steps to reach 11500× initial = saturates any realistic
+    //    magnitude). Dry-spell skip preserved via the outer pos_max>0 check.
     float ema_new = ema_prev;
     if (pos_max > 0.0f) {
-        if (ema_prev == 0.0f) {
-            ema_new = pos_max;  // first-observation bootstrap
-        } else {
-            const float a = fmaxf(alpha, WIENER_ALPHA_FLOOR);
-            ema_new = (1.0f - a) * ema_prev + a * pos_max;
-        }
+        const float a = fmaxf(alpha, wiener_floor);
+        const float ema_raw = (1.0f - a) * ema_prev + a * pos_max;
+        const float max_grow = ema_prev * growth_cap;
+        ema_new = fminf(ema_raw, max_grow);
         isv[RL_POS_SCALED_REWARD_MAX_EMA_INDEX] = ema_new;
     }
     // If ema_prev was 0 AND pos_max was 0 → ema_new still 0 here →
@@ -171,8 +222,8 @@ extern "C" __global__ void rl_reward_clamp_controller(
         if (clip_rate_prev == 0.0f) {
             clip_rate_new = clip_indicator;  // bootstrap
         } else {
-            clip_rate_new = (1.0f - CLIP_RATE_EMA_ALPHA) * clip_rate_prev
-                          + CLIP_RATE_EMA_ALPHA * clip_indicator;
+            clip_rate_new = (1.0f - clip_rate_ema_alpha) * clip_rate_prev
+                          + clip_rate_ema_alpha * clip_indicator;
         }
         isv[RL_REWARD_CLAMP_CLIP_RATE_EMA_INDEX] = clip_rate_new;
     }
@@ -184,12 +235,12 @@ extern "C" __global__ void rl_reward_clamp_controller(
     float margin = isv[RL_REWARD_CLAMP_MARGIN_INDEX];
     if (pos_max > 0.0f) {
         const float clip_target = isv[RL_REWARD_CLAMP_CLIP_RATE_TARGET_INDEX];
-        const float upper = clip_target * MARGIN_TOLERANCE;
-        const float lower = clip_target / MARGIN_TOLERANCE;
+        const float upper = clip_target * margin_tolerance;
+        const float lower = clip_target / margin_tolerance;
         if (clip_rate_new > upper) {
-            margin = fminf(MAX_MARGIN, margin * MARGIN_ADJUST_RATE);
+            margin = fminf(max_margin_isv, margin * margin_adjust_rate);
         } else if (clip_rate_new < lower) {
-            margin = fmaxf(MIN_MARGIN, margin / MARGIN_ADJUST_RATE);
+            margin = fmaxf(min_margin_isv, margin / margin_adjust_rate);
         }
         isv[RL_REWARD_CLAMP_MARGIN_INDEX] = margin;
     }
@@ -203,40 +254,57 @@ extern "C" __global__ void rl_reward_clamp_controller(
     // RATIO = clamp(MIN=1.0, neg_ema/pos_ema, MAX=3.0). Floor 1.0
     // prevents inverted asymmetry; ceiling 3.0 preserves original
     // loss-aversion as the worst case.
+    // Single uniform update (B-2 spec §3.3 — same as pos_max_ema above).
+    // neg_prev is bootstrapped to cold_start=1.0; no first-observation special case.
+    // Same growth_cap (computed above) applies — neg-side cascade is mirror-image
+    // of pos-side, same protection needed.
     const float neg_max  = isv[RL_NEG_SCALED_REWARD_MAX_INDEX];
     const float neg_prev = isv[RL_NEG_SCALED_REWARD_MAX_EMA_INDEX];
     float       neg_new  = neg_prev;
     if (neg_max > 0.0f) {
-        if (neg_prev == 0.0f) {
-            neg_new = neg_max;
-        } else {
-            const float a = fmaxf(alpha, WIENER_ALPHA_FLOOR);
-            neg_new = (1.0f - a) * neg_prev + a * neg_max;
-        }
+        const float a = fmaxf(alpha, wiener_floor);
+        const float neg_raw = (1.0f - a) * neg_prev + a * neg_max;
+        const float neg_max_grow = neg_prev * growth_cap;
+        neg_new = fminf(neg_raw, neg_max_grow);
         isv[RL_NEG_SCALED_REWARD_MAX_EMA_INDEX] = neg_new;
     }
     // Adaptive RATIO. Defer if EMAs not warmed up yet — keep
     // statically-seeded RATIO=3.0 until both EMAs are non-zero.
     if (ema_new > 0.0f && neg_new > 0.0f) {
         const float ratio_target = neg_new / ema_new;
-        const float ratio_clamped = fmaxf(MIN_RATIO,
-                                          fminf(MAX_RATIO, ratio_target));
+        const float ratio_clamped = fmaxf(min_ratio_isv,
+                                          fminf(max_ratio_isv, ratio_target));
         isv[RL_REWARD_CLAMP_RATIO_INDEX] = ratio_clamped;
     }
 
-    // Step 4 (G.2): WIN / LOSS clamp bounds remain STRUCTURAL — the
-    // G.2 feedback loop required BOTH clamp widening AND span widening.
-    // With clamp frozen here, only the atom span adapts (Step 5 below).
-    // Suppress unused warnings on diagnostic-only state.
-    (void) margin;
-
-    // Adaptive LOSS clamp from observed neg/pos ratio. WIN stays
-    // structural at 1.0; LOSS adapts to actual loss magnitude to
-    // give Q accurate resolution without over-allocating to rare tails.
-    if (ema_new > 0.0f && neg_new > 0.0f) {
-        const float observed_ratio = neg_new / ema_new;
-        const float adaptive_loss = fmaxf(1.0f, fminf(observed_ratio * 1.1f, 3.0f));
-        isv[RL_REWARD_CLAMP_LOSS_INDEX] = adaptive_loss;
+    // ── Step 4: Adaptive WIN / LOSS clamp writeback. ──────────────
+    //
+    // History: a 2026-05-24 G.2 patch froze the clamp bounds at the
+    // trainer-seeded WIN=1.0, LOSS=3.0 over concern that simultaneously
+    // adapting clamps + atom span could form a positive feedback loop.
+    //
+    // Empirical refutation (alpha-rl-gwmkf step 4083, 2026-05-30):
+    // with R-multiple 43 trade distributions (avg_win $7062, avg_loss
+    // $163) the frozen WIN=1.0 caused clip_rate_ema = 0.9999 —
+    // essentially every win gets clamped, V regression sees identical
+    // targets for +$500 wins and +$42k wins, and PPO advantage loses
+    // magnitude signal. Diagnosis: starved policy gradient.
+    //
+    // Safety argument: the MARGIN controller above already saturates
+    // at MAX_MARGIN_ISV (bounded ≤ 5.0). pos_max_ema is bounded by
+    // `reward_scale × raw_PnL`, both finite. So WIN ≤ MAX_MARGIN ×
+    // MAX_REWARD_SCALE × MAX_RAW_PNL is structurally bounded.
+    //
+    // Atom span (Step 5) follows the new WIN via slow EWMA (α=0.001,
+    // half-life ~700 steps), so resolution adjusts gradually as the
+    // reward distribution evolves rather than whipsawing.
+    if (ema_new > 0.0f) {
+        const float min_win_isv = isv[RL_REWARD_CLAMP_MIN_WIN_INDEX];
+        const float win_new     = fmaxf(min_win_isv, margin * ema_new);
+        const float ratio       = isv[RL_REWARD_CLAMP_RATIO_INDEX];
+        const float loss_new    = fmaxf(min_win_isv, win_new * ratio);
+        isv[RL_REWARD_CLAMP_WIN_INDEX]  = win_new;
+        isv[RL_REWARD_CLAMP_LOSS_INDEX] = loss_new;
     }
 
     // ── Step 5: C51 atom span adaptation from observed reward EMAs. ──
@@ -264,20 +332,20 @@ extern "C" __global__ void rl_reward_clamp_controller(
     const float loss_bound = isv[RL_REWARD_CLAMP_LOSS_INDEX];  // 3.0
     {
         const float v_max_prev = isv[RL_C51_V_MAX_INDEX];
-        const float v_max_target = fmaxf(V_BOUND_FLOOR, win_bound);
+        const float v_max_target = fmaxf(v_bound_floor, win_bound);
         const float v_max_new = (v_max_prev == 0.0f)
             ? v_max_target
-            : (1.0f - V_BOUND_EWMA_ALPHA) * v_max_prev
-              + V_BOUND_EWMA_ALPHA * v_max_target;
-        isv[RL_C51_V_MAX_INDEX] = fmaxf(V_BOUND_FLOOR, v_max_new);
+            : (1.0f - v_bound_ewma_alpha) * v_max_prev
+              + v_bound_ewma_alpha * v_max_target;
+        isv[RL_C51_V_MAX_INDEX] = fmaxf(v_bound_floor, v_max_new);
     }
     {
         const float v_min_prev = isv[RL_C51_V_MIN_INDEX];
-        const float v_min_target = fminf(-V_BOUND_FLOOR, -loss_bound);
+        const float v_min_target = fminf(-v_bound_floor, -loss_bound);
         const float v_min_new = (v_min_prev == 0.0f)
             ? v_min_target
-            : (1.0f - V_BOUND_EWMA_ALPHA) * v_min_prev
-              + V_BOUND_EWMA_ALPHA * v_min_target;
-        isv[RL_C51_V_MIN_INDEX] = fminf(-V_BOUND_FLOOR, v_min_new);
+            : (1.0f - v_bound_ewma_alpha) * v_min_prev
+              + v_bound_ewma_alpha * v_min_target;
+        isv[RL_C51_V_MIN_INDEX] = fminf(-v_bound_floor, v_min_new);
     }
 }

crates/ml-alpha/cuda/rl_reward_scale_controller.cu

@@ -48,7 +48,30 @@
 // Floor for the mean_abs_pnl_ema denominator to guard against div-by-zero
 // when the EMA hasn't accumulated any closed trades yet.
 #define EPS_PNL                 1e-3f
-#define WIENER_ALPHA_FLOOR      0.4f
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX  659
+
+// Adaptive controller floors (spec 2026-05-30 Special case R):
+// asymmetric rate limit on DECREASE (new ≥ prev / 1.05) + bootstrap-fraction
+// floor until N=100 trades have closed. Together these prevent the
+// catastrophic 1.0 → 0.004 crash in 100 steps observed in fold 0 (where a
+// single large pnl signal — pre-trade — would crater the scale before any
+// closed-trade signal could anchor it).
+//
+// Trade-count signal: RL_TRADE_DUR_VAR_COUNT_INDEX (608) is the Welford
+// count over per-batch trade durations — incremented once per closed trade.
+// Reusing it as the trade-count signal avoids a parallel counter.
+//
+// Emit: RL_REWARD_MAGNITUDE_EMA_INDEX (614) mirrors the input EMA so the
+// downstream Welford kernel can track variance for noise-floor derivation
+// elsewhere in the controller cascade. Single-source-of-truth: this
+// controller's input IS the pnl magnitude EMA; slot 614 is the public
+// emit-slot consumed by the Welford-variance kernel.
+#define RL_TRADE_DUR_VAR_COUNT_INDEX        608
+#define RL_REWARD_MAGNITUDE_EMA_INDEX       614
+#define BOOTSTRAP_FRACTION_FLOOR            0.1f
+#define MIN_TRADES_FOR_RELEASE              100.0f
+#define ASYM_DECREASE_RATE                  1.05f
 
 // ─────────────────────────────────────────────────────────────────────
 // rl_reward_scale_controller:
@@ -105,6 +128,15 @@ extern "C" __global__ void rl_reward_scale_controller(
     // noise.
     const float mean_abs_pnl_ema = isv[input_slot];
     if (mean_abs_pnl_ema == 0.0f) return;
+
+    // Emit per-batch pnl magnitude EMA to the public slot so the Welford
+    // variance kernel and any other downstream consumer can track it
+    // without re-reading the input slot through indirect plumbing.
+    // Single-source-of-truth: this controller's input IS the pnl magnitude
+    // EMA — slot 614 mirrors it as the public emit (spec 2026-05-30
+    // Special case R bullet (c)).
+    isv[RL_REWARD_MAGNITUDE_EMA_INDEX] = mean_abs_pnl_ema;
+
     // target_scale = 1.0 / max(mean_abs_pnl_ema, EPS_PNL).
     // Larger typical PnL → smaller scale (reward is divided down toward ±1).
     // Smaller typical PnL → larger scale (reward is amplified toward ±1).
@@ -113,6 +145,20 @@ extern "C" __global__ void rl_reward_scale_controller(
     const float scale_min = isv[RL_REWARD_SCALE_MIN_INDEX];
     target = fmaxf(scale_min, fminf(target, REWARD_SCALE_MAX));
 
+    // Bootstrap-fraction floor (spec 2026-05-30 Special case R bullet (b)):
+    // until N=MIN_TRADES_FOR_RELEASE trades have closed, the scale cannot
+    // drop below 10% of bootstrap. The trade count comes from the Welford
+    // trade-duration counter (incremented once per closed trade). This
+    // protects against the early-training spiral where a single large
+    // mean_abs_pnl pre-trade signal cratered the scale before any closed-
+    // trade ground truth could anchor it (fold 0 crash 1.0 → 0.004 in 100
+    // steps).
+    const float trade_count = isv[RL_TRADE_DUR_VAR_COUNT_INDEX];
+    const float boot        = isv[RL_REWARD_SCALE_BOOTSTRAP_INDEX];
+    const float boot_floor  = (trade_count < MIN_TRADES_FOR_RELEASE)
+        ? boot * BOOTSTRAP_FRACTION_FLOOR
+        : scale_min;
+
     // First-observation replace-directly per
     // `pearl_first_observation_bootstrap`. With prev=1.0 (bootstrap)
     // and a target far from 1.0 on the first real PnL signal, the
@@ -121,13 +167,25 @@ extern "C" __global__ void rl_reward_scale_controller(
     // feeds V regression at magnitude 500× the atom support's
     // ±1 expectation. Replacing directly with target eliminates
     // this cold-start contamination.
-    if (prev == isv[RL_REWARD_SCALE_BOOTSTRAP_INDEX]) {
-        isv[RL_REWARD_SCALE_INDEX] = target;
+    //
+    // Asymmetric DECREASE rate limit (spec 2026-05-30 bullet (a)): even
+    // on the first-observation path, cap per-step decrease at 5%
+    // (new ≥ prev / 1.05) so a tiny initial target can't crater scale
+    // before downstream signal accumulates. The existing 2% per-step
+    // symmetric clamp below remains for subsequent steps (stricter than
+    // 5%, so it stays load-bearing on the slow path).
+    if (prev == boot) {
+        float first = target;
+        if (first < prev) {
+            first = fmaxf(first, prev / ASYM_DECREASE_RATE);
+        }
+        first = fmaxf(boot_floor, fminf(first, REWARD_SCALE_MAX));
+        isv[RL_REWARD_SCALE_INDEX] = first;
         return;
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a   = fmaxf(alpha_step, WIENER_ALPHA_FLOOR);
+    const float a   = fmaxf(alpha_step, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       out = (1.0f - a) * prev + a * target;
 
     // Per-step movement clamp: scale moves at most ±2% from previous.
@@ -139,6 +197,16 @@ extern "C" __global__ void rl_reward_scale_controller(
     const float min_move = prev * 0.98f;
     out = fmaxf(min_move, fminf(out, max_move));
 
-    out = fmaxf(scale_min, fminf(out, REWARD_SCALE_MAX));
+    // Asymmetric DECREASE rate limit (spec 2026-05-30 bullet (a)):
+    // belt-and-braces — the symmetric 2% clamp above is stricter than
+    // the 5% asymmetric cap on the slow path, but the explicit
+    // asymmetric clamp here documents the controller invariant
+    // (decreases cannot exceed 5% per step) and survives any future
+    // relaxation of the 2% symmetric clamp.
+    if (out < prev) {
+        out = fmaxf(out, prev / ASYM_DECREASE_RATE);
+    }
+
+    out = fmaxf(boot_floor, fminf(out, REWARD_SCALE_MAX));
     isv[RL_REWARD_SCALE_INDEX] = out;
 }

crates/ml-alpha/cuda/rl_rollout_steps_controller.cu

@@ -46,16 +46,33 @@
 // past the clip band.
 
 #define RL_N_ROLLOUT_STEPS_INDEX           404
-#define ROLLOUT_MIN                        256.0f
-#define ROLLOUT_MAX                        8192.0f
+// ROLLOUT MIN/MAX clamp bounds are now ISV-driven per the 2026-05-30
+// clamp-bound extension. Runtime-tunable + visible in diag.
+#define RL_ROLLOUT_MIN_INDEX               643
+#define RL_ROLLOUT_MAX_INDEX               644
 // ISV-driven bootstrap + target.
 #define RL_ROLLOUT_BOOTSTRAP_INDEX         475
 #define RL_ADV_VAR_RATIO_TARGET_INDEX      449
 // Schulman params from shared global slots (same as ppo_clip, target_tau).
 #define RL_SCHULMAN_TOLERANCE_INDEX        468
 #define RL_SCHULMAN_ADJUST_RATE_INDEX      469
-#define ADV_VAR_RATIO_NOISE_FLOOR_FRAC     0.01f
-#define WIENER_ALPHA_FLOOR                 0.4f
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX        659
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// noise floor derives from observed advantage-variance signal via Welford
+// triples, asymmetric Schulman widening requires N consecutive below-band
+// observations. Replaces hardcoded ADV_VAR_RATIO_NOISE_FLOOR_FRAC=0.01f
+// (calibrated against the pre-Phase-4.5 advantage regime; under Phase 4.5
+// post-norm advantage variance is definitionally near-zero, so the
+// controller is also rewired to consume RL_ADV_VAR_PRE_NORM_INDEX=612 —
+// the pre-normalization variance emitted by rl_advantage_normalize.cu).
+#define RL_ADV_VAR_VAR_COUNT_INDEX         596
+#define RL_ADV_VAR_VAR_M2_INDEX             598
+#define RL_ADV_VAR_BELOW_COUNT_INDEX        599
+#define NOISE_FLOOR_TARGET_FRAC             0.5f  // floor ≥ 50% of target
+#define NOISE_FLOOR_STD_MULTIPLIER          2.0f  // floor ≥ 2σ of observed signal
+#define WIDEN_PATIENCE_CONSECUTIVE          3.0f  // widen requires N below-band steps
 
 // ─────────────────────────────────────────────────────────────────────
 // rl_rollout_steps_controller:
@@ -103,31 +120,43 @@ extern "C" __global__ void rl_rollout_steps_controller(
     // RL_ADV_VAR_RATIO_TARGET_INDEX (seeded at trainer init).
     const float adv_var_target = isv[RL_ADV_VAR_RATIO_TARGET_INDEX];
 
-    // Noise-floor gate: input below target × NOISE_FLOOR_FRAC is
-    // dominated by numerical noise — hold rollout unchanged.
-    // Mirrors the ppo_clip / target_tau controllers' design after the
-    // alpha-rl-mjzfk multiplicative-blow-up incident.
-    const float adv_var_noise_floor =
-        adv_var_target * ADV_VAR_RATIO_NOISE_FLOOR_FRAC;
+    // Adaptive noise floor — signal-driven per
+    // `pearl_zscore_normalization_for_magnitude_asymmetric_signals` and
+    // `feedback_adaptive_not_tuned`. Welford sample variance =
+    // M² / (count − 1) when count > 1.
+    const float adv_count = isv[RL_ADV_VAR_VAR_COUNT_INDEX];
+    const float adv_var = (adv_count > 1.0f)
+        ? isv[RL_ADV_VAR_VAR_M2_INDEX] / (adv_count - 1.0f)
+        : 0.0f;
+    const float adv_std = sqrtf(adv_var);
+    const float adv_var_noise_floor = fmaxf(adv_var_target * NOISE_FLOOR_TARGET_FRAC,
+                                             adv_std * NOISE_FLOOR_STD_MULTIPLIER);
     if (advantage_var_over_abs_mean < adv_var_noise_floor) return;
 
-    // Bounded multiplicative adjustment (Schulman-style adaptive).
-    // At most ADV_VAR_RATIO_ADJUST_RATE × shift per step regardless of
-    // how far input is from target. After several consecutive
-    // out-of-band observations the output drifts smoothly toward
-    // MIN/MAX, but a single observation can't slam it there.
+    // Asymmetric Schulman (spec 2026-05-30 Section "Approach C, folded in"):
+    // widening rollout fires on a single above-band observation — noisy
+    // advantages are a safety signal we act on fast (collect more samples
+    // before updating). Shrinking rollout requires N consecutive below-band
+    // observations so a single quiet step can't push the buffer too small.
+    // Below-band counter is per-controller in ISV.
     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
     float scale;
     if (advantage_var_over_abs_mean > adv_var_target * tolerance) {
-        scale = adjust_rate;
+        scale = adjust_rate;                              // widen — single observation
+        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = 0.0f;         // reset patience
     } else if (advantage_var_over_abs_mean < adv_var_target / tolerance) {
-        scale = 1.0f / adjust_rate;
+        const float new_count = isv[RL_ADV_VAR_BELOW_COUNT_INDEX] + 1.0f;
+        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = new_count;
+        scale = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? (1.0f / adjust_rate) : 1.0f;
     } else {
+        isv[RL_ADV_VAR_BELOW_COUNT_INDEX] = 0.0f;         // in-band → reset
         scale = 1.0f;
     }
+    const float rollout_min = isv[RL_ROLLOUT_MIN_INDEX];
+    const float rollout_max = isv[RL_ROLLOUT_MAX_INDEX];
     float target = prev * scale;
-    target = fmaxf(ROLLOUT_MIN, fminf(target, ROLLOUT_MAX));
+    target = fmaxf(rollout_min, fminf(target, rollout_max));
 
     // First-observation replace-directly per
     // `pearl_first_observation_bootstrap`.
@@ -137,9 +166,9 @@ extern "C" __global__ void rl_rollout_steps_controller(
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a   = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+    const float a   = fmaxf(alpha, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       out = (1.0f - a) * prev + a * target;
 
-    out = fmaxf(ROLLOUT_MIN, fminf(out, ROLLOUT_MAX));
+    out = fmaxf(rollout_min, fminf(out, rollout_max));
     isv[RL_N_ROLLOUT_STEPS_INDEX] = out;
 }

crates/ml-alpha/cuda/rl_signal_variance_update.cu

@@ -0,0 +1,73 @@
+// rl_signal_variance_update.cu — Welford online variance for controller inputs (2026-05-30).
+//
+// Per `feedback_adaptive_not_tuned`, `feedback_isv_for_adaptive_bounds`,
+// `pearl_controller_anchors_isv_driven`: every adaptive controller's noise
+// floor / target / threshold must derive from observed signal statistics,
+// not from hardcoded constants. This kernel maintains a running mean and
+// M² (sum of squared deviations from mean) for each controller-input EMA,
+// using Welford's online algorithm for numerical stability with float32.
+//
+// Welford recurrence (numerically stable, single-pass):
+//   n_new   = n_prev + 1
+//   delta   = x - mean_prev
+//   mean    = mean_prev + delta / n_new
+//   delta2  = x - mean             // recomputed against NEW mean
+//   m2      = m2_prev + delta * delta2
+//
+// Sample variance = m2 / (n - 1)   when n > 1; undefined when n ≤ 1.
+//
+// Per `pearl_first_observation_bootstrap`: skip the update when input ==
+// sentinel 0.0. The first non-zero observation initializes mean directly
+// (delta against mean_prev=0 produces mean = x for n=1; delta against the
+// new mean is 0; m2 stays 0; subsequent observations build real variance).
+//
+// Per `feedback_cpu_is_read_only`: pure device kernel. ISV is the contract
+// surface; no host computation, no host control. Caller threads ISV bus
+// pointer + four slot indices (input + count/mean/M² triple). Caller is
+// responsible for launching once per controller input per step (usually
+// via fused-kernel orchestration).
+//
+// Per `feedback_no_atomicadd`, `feedback_nvidia_grade_perf_for_kernels`:
+// single-thread block. Each Welford triple is owned by exactly one input
+// slot, accessed sequentially across steps — no concurrent writers, no
+// reduction, no atomic.
+//
+// Launch config:
+//   grid  = (1, 1, 1)
+//   block = (1, 1, 1)
+//   smem  = 0
+//   stream = main RL stream (sequenced after EMA producers and before
+//            controllers consume the variance)
+
+extern "C" __global__ void rl_signal_variance_update(
+    float* __restrict__ isv,
+    int input_slot,
+    int count_slot,
+    int mean_slot,
+    int m2_slot
+) {
+    // Single-thread guard. Block shape is (1,1,1) by contract but defend
+    // against a mis-configured launcher.
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    // Sentinel-zero skip per pearl_first_observation_bootstrap.
+    // Producers (EMA kernels) hold their slot at 0.0 until the first
+    // real observation. Welford should NOT count those zero reads as
+    // genuine observations of "the signal is zero".
+    const float x = isv[input_slot];
+    if (x == 0.0f) return;
+
+    // Welford online update.
+    const float n_prev    = isv[count_slot];
+    const float n_new     = n_prev + 1.0f;
+    const float mean_prev = isv[mean_slot];
+    const float delta     = x - mean_prev;
+    const float mean_new  = mean_prev + delta / n_new;
+    const float delta2    = x - mean_new;   // against new mean — load-bearing for stability
+    const float m2_new    = isv[m2_slot] + delta * delta2;
+
+    isv[count_slot] = n_new;
+    isv[mean_slot]  = mean_new;
+    isv[m2_slot]    = m2_new;
+}

crates/ml-alpha/cuda/rl_state_action_mask.cu

@@ -0,0 +1,152 @@
+// rl_state_action_mask.cu — Phase 7b F5 state-conditional action availability mask.
+//
+// Modeled directly on `rl_band_mask.cu`'s lattice (Grid=(B), Block=(1, 1, 1),
+// single thread per block, ISV-gated, reads `pos_state`).
+//
+// Unlike the band mask (which OVERRIDES `actions_d` post-sampling), F5
+// applies a HARD PRE-SAMPLE LOGIT MASK: it writes `-INFINITY` into
+// `pi_logits[b][a]` for state-illegal actions, so that downstream
+// `softmax(pi_logits)` produces EXACTLY 0 probability on masked actions
+// (F5-G1 demands exactly 0, not "low"). The `rl_pi_action_kernel` then
+// reads the masked logits and cannot sample those actions.
+//
+// Mathematical composition with F2 (rl_q_pi_distill_grad):
+//   F2 computes π_target from unmasked E_Q values; F5 masks π_θ by
+//   forcing pi_logits[masked]=-INF before softmax. The distill gradient
+//   for masked actions becomes (π_θ - π_target) = (0 - π_target_masked),
+//   which drives π_target_masked toward zero on those actions — the
+//   gradient naturally encodes the constraint.
+//
+// State-conditional rules (per spec §3.5):
+//
+//   * When position_lots == 0 (FLAT):
+//       mask {Hold=2, FlatFromLong=3, FlatFromShort=4, TrailTighten=7,
+//             TrailLoosen=8, HalfFlatLong=9, HalfFlatShort=10}
+//       leaving only {ShortLarge=0, ShortSmall=1, LongSmall=5, LongLarge=6}
+//       → agent MUST open a position.
+//
+//   * When position_lots > 0 (LONG):
+//       mask all short-side actions: {ShortLarge=0, ShortSmall=1,
+//             FlatFromShort=4, HalfFlatShort=10}.
+//       Same-side opens (LongSmall=5/LongLarge=6) remain available — they
+//       resolve to pyramid adds in `actions_to_market_targets.cu`.
+//
+//   * When position_lots < 0 (SHORT):
+//       symmetric: mask {LongSmall=5, LongLarge=6, FlatFromLong=3,
+//             HalfFlatLong=9}.
+//
+//   * When any active unit has trail_distance ≥ unit_initial_r *
+//     RL_TRAIL_MAX_INITIAL_R_RATIO * (1 - eps):
+//       mask TrailLoosen (8) — at the per-unit cap it is a mechanical
+//       no-op in `rl_trail_mutate.cu` (Phase 5 clamp).
+//
+// Master gate at `RL_F5_STATE_MASK_ENABLED_INDEX` (slot 823). Bootstrap
+// 0.0 (OFF) → kernel returns immediately, preserving bit-equality with
+// Phase 7a HEAD. Operator flips to 1.0 to engage Phase 7b.
+//
+// Per `feedback_no_atomicadd` (no atomics — single-thread-per-block),
+// `feedback_cpu_is_read_only` (pure device-side), `pearl_band_mask` /
+// `pearl_state_conditional_action_mask` (structural twin to the band).
+
+#include <stdint.h>
+#include <math.h>
+
+#define N_ACTIONS                                  11
+#define MAX_UNITS                                   4
+
+// Action enum (must match crates/ml-alpha/src/rl/common.rs).
+#define ACTION_SHORT_LARGE                          0
+#define ACTION_SHORT_SMALL                          1
+#define ACTION_HOLD                                 2
+#define ACTION_FLAT_FROM_LONG                       3
+#define ACTION_FLAT_FROM_SHORT                      4
+#define ACTION_LONG_SMALL                           5
+#define ACTION_LONG_LARGE                           6
+#define ACTION_TRAIL_TIGHTEN                        7
+#define ACTION_TRAIL_LOOSEN                         8
+#define ACTION_HALF_FLAT_LONG                       9
+#define ACTION_HALF_FLAT_SHORT                     10
+
+#define RL_TRAIL_MAX_INITIAL_R_RATIO_INDEX        814
+#define RL_F5_STATE_MASK_ENABLED_INDEX            823
+
+extern "C" __global__ void rl_state_action_mask(
+    float*               __restrict__ pi_logits,           // [B × N_ACTIONS] IN/OUT
+    const unsigned char* __restrict__ pos_state,           // [B × pos_bytes]
+    const float*         __restrict__ unit_trail_distance, // [B × MAX_UNITS]
+    const float*         __restrict__ unit_initial_r,      // [B × MAX_UNITS]
+    const unsigned char* __restrict__ unit_active,         // [B × MAX_UNITS]
+    const float*         __restrict__ isv,
+    int                                b_size,
+    int                                pos_bytes
+) {
+    const int b = blockIdx.x;
+    if (b >= b_size) return;
+
+    // Master gate — bootstrap default OFF preserves Phase 7a bit-equality.
+    const float enabled = isv[RL_F5_STATE_MASK_ENABLED_INDEX];
+    if (enabled <= 0.5f) return;
+
+    // Position layout: pos_state[b * pos_bytes + 0..4] = position_lots:i32
+    // (canonical foxhunt offset; matches rl_band_mask.cu and
+    // rl_confidence_gate.cu readers).
+    const int position_lots =
+        *reinterpret_cast<const int*>(pos_state + b * pos_bytes);
+
+    const float neg_inf = -INFINITY;
+    float* row = pi_logits + b * N_ACTIONS;
+
+    if (position_lots == 0) {
+        // FLAT — mask Hold + all close/trail/half-flat; force open commit.
+        row[ACTION_HOLD]            = neg_inf;
+        row[ACTION_FLAT_FROM_LONG]  = neg_inf;
+        row[ACTION_FLAT_FROM_SHORT] = neg_inf;
+        row[ACTION_TRAIL_TIGHTEN]   = neg_inf;
+        row[ACTION_TRAIL_LOOSEN]    = neg_inf;
+        row[ACTION_HALF_FLAT_LONG]  = neg_inf;
+        row[ACTION_HALF_FLAT_SHORT] = neg_inf;
+        // Surviving: {ShortLarge=0, ShortSmall=1, LongSmall=5, LongLarge=6}.
+    } else if (position_lots > 0) {
+        // LONG — mask all short-side actions; same-side opens remain
+        // available (pyramid resolution via actions_to_market_targets).
+        row[ACTION_SHORT_LARGE]     = neg_inf;
+        row[ACTION_SHORT_SMALL]     = neg_inf;
+        row[ACTION_FLAT_FROM_SHORT] = neg_inf;
+        row[ACTION_HALF_FLAT_SHORT] = neg_inf;
+    } else {
+        // SHORT — symmetric: mask all long-side actions.
+        row[ACTION_LONG_SMALL]      = neg_inf;
+        row[ACTION_LONG_LARGE]      = neg_inf;
+        row[ACTION_FLAT_FROM_LONG]  = neg_inf;
+        row[ACTION_HALF_FLAT_LONG]  = neg_inf;
+    }
+
+    // Trail-at-cap branch (mq2pc-specific). When ANY active unit has its
+    // trail saturated at the per-unit-initial_r ceiling, TrailLoosen is a
+    // mechanical no-op in `rl_trail_mutate.cu` — mask it.
+    //
+    // From flat, TrailLoosen is already masked above; this branch only
+    // adds the mask for in-position states (the trail buffers are
+    // meaningful only when units are active).
+    if (position_lots != 0) {
+        const float trail_ratio = isv[RL_TRAIL_MAX_INITIAL_R_RATIO_INDEX];
+        // Use a small relative epsilon to catch float-comparison saturation.
+        const float eps = 1.0e-3f;
+        bool any_at_cap = false;
+        const int base = b * MAX_UNITS;
+        for (int u = 0; u < MAX_UNITS; ++u) {
+            if (unit_active[base + u]) {
+                const float t        = unit_trail_distance[base + u];
+                const float r0       = unit_initial_r[base + u];
+                const float cap      = r0 * trail_ratio;
+                if (cap > 0.0f && t >= cap * (1.0f - eps)) {
+                    any_at_cap = true;
+                    break;
+                }
+            }
+        }
+        if (any_at_cap) {
+            row[ACTION_TRAIL_LOOSEN] = neg_inf;
+        }
+    }
+}

crates/ml-alpha/cuda/rl_surfer_scaffold_controller.cu

@@ -0,0 +1,110 @@
+// rl_surfer_scaffold_controller.cu — adaptive Phase 5 shaping weight.
+//
+// Spec: docs/superpowers/specs/2026-06-01-reward-policy-alignment-investigation.md §6
+//
+// Reads (from ISV):
+//   RL_WIN_RATE_EMA_INDEX (677)            — agent's running win rate
+//   RL_CUMULATIVE_DONES_INDEX (660)        — total closed-trade count (resets at
+//                                            fold/eval boundary; controller bootstraps
+//                                            scaffold back to 1.0 from there)
+//   RL_EDGE_PH_FRAC_ALERTED_INDEX (751)    — fraction of batches whose Page-Hinkley
+//                                            edge-decay detector has alerted; used as
+//                                            re-engagement trigger when policy edge
+//                                            degrades
+//   RL_SURFER_BREAK_EVEN_WR_INDEX (754)    — config, default 0.30
+//   RL_SURFER_K_SHARPNESS_INDEX (755)      — config, default 30.0
+//   RL_SURFER_WARMUP_TRADES_INDEX (756)    — config, default 200.0
+//
+// Writes (to ISV):
+//   RL_SURFER_SCAFFOLD_WEIGHT_INDEX (753)  — w ∈ [0,1] consumed by
+//                                            rl_fused_reward_pipeline.cu Phase 5
+//
+// Math (v5.2):
+//   competence   = confidence(n_trades) × sigmoid(k_sharp × (wr_ema − break_even))
+//   w_competence = 1 − competence
+//   w_decay      = max(0, 2 × frac_alerted − 1)   // v5.1: fires above 50% baseline
+//   w            = clamp(max(w_competence, w_decay), 0, 1)
+//
+// v5.2 fix (alpha-rl-mjsmr step 99-249 verdict 2026-06-02): dropped the
+// `max(0, …)` clamp on `wr_excess`. With the clamp, wr<break_even mapped to
+// sigmoid(0)=0.5 (half-scaffold at novice agent — wrong). Now wr=0.20 maps
+// to sigmoid(−3)≈0.05 ⇒ competence≈0.05 ⇒ w_competence≈0.95 (full scaffold,
+// correct novice-bias). Symmetric around break_even — competence saturates
+// fast both directions for k_sharp=30.
+//
+// Behavioral table:
+//   wr_ema     wr-bk    sigmoid    competence (n_trades≫warmup)    w_competence
+//   0.20      -0.10    0.047       0.05                            0.95   (full scaffold)
+//   0.27      -0.03    0.29        0.29                            0.71
+//   0.30       0.00    0.50        0.50                            0.50   (half at break-even)
+//   0.33      +0.03    0.71        0.71                            0.29
+//   0.40      +0.10    0.953       0.95                            0.05   (pure pnl)
+//
+// Per `feedback_no_atomicadd`: single-thread launch (1×1×1), no atomic ops.
+// Per `feedback_cpu_is_read_only`: pure device-side.
+// Per `feedback_no_nvrtc`: pre-compiled cubin.
+
+#include <stdint.h>
+#include <math_constants.h>
+
+// ISV slot indices (must match crates/ml-alpha/src/rl/isv_slots.rs)
+#define RL_WIN_RATE_EMA_INDEX               677
+#define RL_CUMULATIVE_DONES_INDEX           660
+#define RL_EDGE_PH_FRAC_ALERTED_INDEX       751
+#define RL_SURFER_SCAFFOLD_WEIGHT_INDEX     753
+#define RL_SURFER_BREAK_EVEN_WR_INDEX       754
+#define RL_SURFER_K_SHARPNESS_INDEX         755
+#define RL_SURFER_WARMUP_TRADES_INDEX       756
+#define RL_SURFER_SCAFFOLD_FORCE_PIN_INDEX  824
+
+__device__ static inline float sigmoidf(float x) {
+    return 1.0f / (1.0f + expf(-x));
+}
+
+extern "C" __global__ void rl_surfer_scaffold_controller(float* isv) {
+    // Single-thread kernel — launched (1,1,1)/(1,1,1).
+    if (threadIdx.x != 0 || blockIdx.x != 0) return;
+
+    // Phase A force-pin (2026-06-05): when set, leave slot 753 at its
+    // bootstrap value (pure-pnl) instead of overwriting it. Fixes the
+    // cosmetic-bootstrap bug (pearl_reward_misalign_blocks_f4_slot753_override).
+    if (isv[RL_SURFER_SCAFFOLD_FORCE_PIN_INDEX] > 0.5f) {
+        return;  // do NOT write isv[RL_SURFER_SCAFFOLD_WEIGHT_INDEX]
+    }
+
+    const float wr_ema       = isv[RL_WIN_RATE_EMA_INDEX];
+    const float n_trades     = isv[RL_CUMULATIVE_DONES_INDEX];
+    const float frac_decay   = isv[RL_EDGE_PH_FRAC_ALERTED_INDEX];
+    const float break_even   = isv[RL_SURFER_BREAK_EVEN_WR_INDEX];
+    const float k_sharp      = isv[RL_SURFER_K_SHARPNESS_INDEX];
+    const float warmup_n     = isv[RL_SURFER_WARMUP_TRADES_INDEX];
+
+    // Confidence: sigmoid centered on warmup_n, scale = 30% of warmup.
+    // n_trades=0 → confidence ≈ sigmoid(-warmup/(0.3*warmup)) = sigmoid(-3.33) ≈ 0.034
+    // n_trades=warmup → confidence = sigmoid(0) = 0.5
+    // n_trades=2*warmup → confidence ≈ sigmoid(3.33) ≈ 0.966
+    const float warmup_scale = fmaxf(warmup_n * 0.3f, 1.0f);  // floor to avoid div-by-zero
+    const float confidence   = sigmoidf((n_trades - warmup_n) / warmup_scale);
+
+    // Win-rate distance from break-even (signed — v5.2 drops the max(0,...) clamp
+    // so wr<break_even properly maps to low competence ⇒ full scaffold).
+    const float wr_distance = wr_ema - break_even;
+
+    // Competence: agent must have BOTH trade-count confidence AND wr above break-even.
+    const float competence = confidence * sigmoidf(k_sharp * wr_distance);
+
+    // Inverse: scaffold weight from competence.
+    const float w_competence = 1.0f - competence;
+
+    // Edge-decay re-engagement: only fires ABOVE 50% baseline. Train-time PH
+    // naturally alerts on a steady fraction of batches even during healthy
+    // learning (pearl_edge_decay_detector_phase1_validated_train_also_decays);
+    // re-engagement must measure EXCESS alertedness, not absolute level, or it
+    // pins the scaffold at w=1 forever (alpha-rl-zf6s5 step 5719 failure mode).
+    const float w_decay = fmaxf(0.0f, 2.0f * frac_decay - 1.0f);
+
+    const float w_raw = fmaxf(w_competence, w_decay);
+    const float w     = fmaxf(0.0f, fminf(1.0f, w_raw));
+
+    isv[RL_SURFER_SCAFFOLD_WEIGHT_INDEX] = w;
+}

crates/ml-alpha/cuda/rl_target_tau_controller.cu

@@ -26,16 +26,34 @@
 // the target-net design exists to provide.
 
 #define RL_TARGET_TAU_INDEX     401
-#define TAU_MIN                0.001f
-#define RL_TARGET_TAU_MAX_INDEX 573
+// τ MIN clamp bound is now ISV-driven per the 2026-05-30 clamp-bound
+// extension. ISV-residence makes the floor runtime-tunable and aligns
+// with the broader principle that every controller bound is observed-
+// signal driven rather than calibrated against a prior regime.
+#define RL_TARGET_TAU_MIN_INDEX           642
+#define RL_TARGET_TAU_MAX_INDEX           573
 // ISV-driven bootstrap + target.
 #define RL_TAU_BOOTSTRAP_INDEX            473
 #define RL_DIV_TARGET_INDEX               457
 // Schulman params from shared global slots (same as ppo_clip).
 #define RL_SCHULMAN_TOLERANCE_INDEX       468
 #define RL_SCHULMAN_ADJUST_RATE_INDEX     469
-#define DIV_NOISE_FLOOR_FRAC              0.01f
-#define WIENER_ALPHA_FLOOR                0.4f
+// Wiener-α floor — shared across 9 controllers (slot 659).
+#define RL_WIENER_ALPHA_FLOOR_INDEX       659
+
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// noise floor derives from observed q_divergence_ema variance via Welford
+// triples, asymmetric Schulman widening requires N consecutive below-band
+// observations. Replaces hardcoded DIV_NOISE_FLOOR_FRAC=0.01f which was
+// calibrated against the pre-Phase-4.5 divergence regime — under Phase 4.5
+// the 1%-of-target floor is ~100× too low and the controller never moved
+// from bootstrap (alpha-rl-... fold 0 confirmed τ stuck at 0.005).
+#define RL_Q_DIV_VAR_COUNT_INDEX           592
+#define RL_Q_DIV_VAR_M2_INDEX              594
+#define RL_Q_DIV_BELOW_COUNT_INDEX         595
+#define NOISE_FLOOR_TARGET_FRAC            0.5f  // floor ≥ 50% of target
+#define NOISE_FLOOR_STD_MULTIPLIER         2.0f  // floor ≥ 2σ of observed signal
+#define WIDEN_PATIENCE_CONSECUTIVE         3.0f  // widen requires N below-band steps
 
 
 // ─────────────────────────────────────────────────────────────────────
@@ -77,25 +95,50 @@ extern "C" __global__ void rl_target_tau_controller(
 
     // ISV-driven divergence target (was hardcoded #define).
     const float div_target = isv[RL_DIV_TARGET_INDEX];
-    const float div_noise_floor = div_target * DIV_NOISE_FLOOR_FRAC;
 
-    // Noise-floor gate.
+    // Adaptive noise floor — signal-driven per
+    // `pearl_zscore_normalization_for_magnitude_asymmetric_signals` and
+    // `feedback_adaptive_not_tuned`. Floor must scale with observed signal
+    // magnitude AND have an absolute minimum tied to the target so a
+    // momentarily-noisy signal can't trigger spurious adjustments.
+    // Welford sample variance = M² / (count − 1) when count > 1.
+    const float div_count = isv[RL_Q_DIV_VAR_COUNT_INDEX];
+    const float div_var = (div_count > 1.0f)
+        ? isv[RL_Q_DIV_VAR_M2_INDEX] / (div_count - 1.0f)
+        : 0.0f;
+    const float div_std = sqrtf(div_var);
+    const float div_noise_floor = fmaxf(div_target * NOISE_FLOOR_TARGET_FRAC,
+                                         div_std * NOISE_FLOOR_STD_MULTIPLIER);
+
+    // Noise-floor gate: divergence below the adaptive floor is dominated by
+    // numerical noise OR signal stays naturally below target under the
+    // current architecture. Hold τ.
     if (q_divergence_norm < div_noise_floor) return;
 
-    // Bounded multiplicative adjustment.
-    float ratio;
+    // Asymmetric Schulman (spec 2026-05-30 Section "Approach C, folded in"):
+    // raising τ fires on a single above-band observation — real Q
+    // divergence is a safety signal we act on fast (target net falling
+    // behind = raise the bootstrap rate). Lowering τ requires N consecutive
+    // below-band observations so a single noisy step can't push τ toward
+    // the floor. Below-band counter is per-controller in ISV.
     const float tolerance   = isv[RL_SCHULMAN_TOLERANCE_INDEX];
     const float adjust_rate = isv[RL_SCHULMAN_ADJUST_RATE_INDEX];
+    float ratio;
     if (q_divergence_norm > div_target * tolerance) {
-        ratio = adjust_rate;
+        ratio = adjust_rate;                              // raise τ — single observation
+        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = 0.0f;           // reset patience
     } else if (q_divergence_norm < div_target / tolerance) {
-        ratio = 1.0f / adjust_rate;
+        const float new_count = isv[RL_Q_DIV_BELOW_COUNT_INDEX] + 1.0f;
+        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = new_count;
+        ratio = (new_count >= WIDEN_PATIENCE_CONSECUTIVE) ? (1.0f / adjust_rate) : 1.0f;
     } else {
+        isv[RL_Q_DIV_BELOW_COUNT_INDEX] = 0.0f;           // in-band → reset
         ratio = 1.0f;
     }
     float tau_target = tau_prev * ratio;
+    const float tau_min = isv[RL_TARGET_TAU_MIN_INDEX];
     const float tau_max = isv[RL_TARGET_TAU_MAX_INDEX];
-    tau_target = fmaxf(TAU_MIN, fminf(tau_target, tau_max));
+    tau_target = fmaxf(tau_min, fminf(tau_target, tau_max));
 
     // First-observation replace-directly: if
     // prev is still exactly the hardcoded bootstrap value, this is
@@ -112,9 +155,9 @@ extern "C" __global__ void rl_target_tau_controller(
     }
 
     // Wiener-α blend with floor per pearl_wiener_alpha_floor_for_nonstationary.
-    const float a       = fmaxf(alpha, WIENER_ALPHA_FLOOR);
+    const float a       = fmaxf(alpha, isv[RL_WIENER_ALPHA_FLOOR_INDEX]);
     float       tau_new = (1.0f - a) * tau_prev + a * tau_target;
 
-    tau_new = fmaxf(TAU_MIN, fminf(tau_new, tau_max));
+    tau_new = fmaxf(tau_min, fminf(tau_new, tau_max));
     isv[RL_TARGET_TAU_INDEX] = tau_new;
 }

crates/ml-alpha/cuda/rl_trail_mutate.cu

@@ -1,40 +1,56 @@
 // rl_trail_mutate.cu — SP20 P5 trail mutation kernel.
 //
-// Handles the previously-dead a7 (TrailTighten) and a8 (TrailLoosen)
-// actions per `pearl_dead_trail_stop_actions_a7_a8`. Mutates each
-// active unit's trail_distance bounded by ISV-driven MIN/MAX with
-// symmetric reciprocal adjust rate per SP20 §4.12:
-//   a7 (tighten): trail = max(MIN, trail × rate)
-//   a8 (loosen):  trail = min(MAX, trail / rate)
+// Handles a7 (TrailTighten) and a8 (TrailLoosen) — closes
+// `pearl_dead_trail_stop_actions_a7_a8`. Mutates each active unit's
+// trail_distance bounded by ISV-driven MIN/MAX. Each direction has its
+// own independent factor per spec 2026-05-30-adaptive-risk-management:
 //
-// Tighten and loosen are reciprocal: N tightens followed by N loosens
-// returns trail to its original distance.
+//   a7 (tighten): trail = max(MIN, trail × TIGHTEN_FACTOR)   (default 0.9)
+//   a8 (loosen):  trail = min(MAX, trail × LOOSEN_FACTOR)    (default 1.1)
 //
-// Audit history: scripts/audit-wiring.sh dogfood pass flagged that
-// a7/a8 had no consumer anywhere in the codebase prior to this
-// kernel.
+// Tighten and loosen are NO LONGER strictly reciprocal — the agent can
+// learn (via the ISV slots' controllers, if any) to bias one direction
+// or the other. Bootstrap factors (0.9 / 1.1) preserve the prior
+// approximately-symmetric behavior.
+//
+// Slot migration: previously read `RL_TRAIL_ADJUST_RATE_INDEX = 497`
+// and used `trail × rate` for tighten and `trail / rate` for loosen.
+// Now reads independent `RL_TRAIL_TIGHTEN_FACTOR_INDEX = 682` and
+// `RL_TRAIL_LOOSEN_FACTOR_INDEX = 683` from the risk-management spec.
+//
+// Phase 5 (2026-06-04): adds a per-unit absolute ceiling on the loosen
+// action. The TrailLoosen pathology surfaced by the Phase 4-A3
+// ultrathink investigation showed mean trail 376 → max 2959 ticks
+// (~$37k risk per position) because the multiplicative loosen had no
+// per-unit anchor — only the global slot 495 cap (100.0 price units).
+// The fix: clamp `unit_trail_distance ≤ unit_initial_r ·
+// RL_TRAIL_MAX_INITIAL_R_RATIO` after the multiply. Ratio bootstrap
+// 4.0 — agent can widen ≤ 4× from open, far below the smoke fleet's
+// 2959-tick worst case.
 //
 // One thread per (batch, unit). Mutates ALL active units uniformly
-// when the batch chose a7/a8 — matches SP20 §2.2 Tier 2 design
-// ("a7/a8 uniformly tighten/loosen all active units").
+// when the batch chose a7/a8 — matches SP20 §2.2 Tier 2 design.
 //
 // Per `feedback_no_atomicadd`: per-(batch, unit) independent writes.
 // Per `feedback_cpu_is_read_only`: pure device-side.
-// Per `feedback_isv_for_adaptive_bounds`: MIN/MAX/rate all ISV slots.
+// Per `feedback_isv_for_adaptive_bounds`: MIN/MAX/factors all ISV slots.
 
 #include <stdint.h>
 
-#define MAX_UNITS                          4
-#define ACTION_TRAIL_TIGHTEN               7
-#define ACTION_TRAIL_LOOSEN                8
-#define RL_TRAIL_MIN_INDEX                 494
-#define RL_TRAIL_MAX_INDEX                 495
-#define RL_TRAIL_ADJUST_RATE_INDEX         497
+#define MAX_UNITS                                4
+#define ACTION_TRAIL_TIGHTEN                     7
+#define ACTION_TRAIL_LOOSEN                      8
+#define RL_TRAIL_MIN_INDEX                       494
+#define RL_TRAIL_MAX_INDEX                       495
+#define RL_TRAIL_TIGHTEN_FACTOR_INDEX            682
+#define RL_TRAIL_LOOSEN_FACTOR_INDEX             683
+#define RL_TRAIL_MAX_INITIAL_R_RATIO_INDEX       814
 
 extern "C" __global__ void rl_trail_mutate(
     const int*           __restrict__ actions,             // [B]
     const float*         __restrict__ isv,
     const unsigned char* __restrict__ unit_active,         // [B * MAX_UNITS]
+    const float*         __restrict__ unit_initial_r,      // [B * MAX_UNITS]
     float*               __restrict__ unit_trail_distance, // [B * MAX_UNITS] IN/OUT
     int                                b_size
 ) {
@@ -48,17 +64,27 @@ extern "C" __global__ void rl_trail_mutate(
     const int idx = b * MAX_UNITS + u;
     if (unit_active[idx] == 0) return;
 
-    const float trail_min   = isv[RL_TRAIL_MIN_INDEX];
-    const float trail_max   = isv[RL_TRAIL_MAX_INDEX];
-    const float adjust_rate = isv[RL_TRAIL_ADJUST_RATE_INDEX];
-    const float current     = unit_trail_distance[idx];
+    const float trail_min = isv[RL_TRAIL_MIN_INDEX];
+    const float trail_max = isv[RL_TRAIL_MAX_INDEX];
+    const float current   = unit_trail_distance[idx];
 
     float updated;
     if (action == ACTION_TRAIL_TIGHTEN) {
-        updated = fmaxf(trail_min, current * adjust_rate);
+        const float factor = isv[RL_TRAIL_TIGHTEN_FACTOR_INDEX];  // bootstrap 0.9
+        updated = fmaxf(trail_min, current * factor);
     } else {  // ACTION_TRAIL_LOOSEN
-        const float inv_rate = (adjust_rate > 1e-6f) ? (1.0f / adjust_rate) : 1.0f;
-        updated = fminf(trail_max, current * inv_rate);
+        const float factor = isv[RL_TRAIL_LOOSEN_FACTOR_INDEX];   // bootstrap 1.1
+        updated = fminf(trail_max, current * factor);
+
+        // Phase 5 per-unit absolute ceiling: trail ≤ initial_r · ratio.
+        // Guards against the bimodal Hold+TrailLoosen risk-shifting
+        // pathology (Phase 4-A3 diagnosis 2026-06-04).
+        const float initial_r = unit_initial_r[idx];
+        if (initial_r > 1e-8f) {
+            const float ratio = isv[RL_TRAIL_MAX_INITIAL_R_RATIO_INDEX];
+            const float per_unit_cap = initial_r * ratio;
+            updated = fminf(updated, per_unit_cap);
+        }
     }
     unit_trail_distance[idx] = updated;
 }

crates/ml-alpha/cuda/rl_v_blend.cu

@@ -0,0 +1,37 @@
+// rl_v_blend.cu — Phase 4.4 adaptive V baseline blend (2026-05-30).
+//
+// V_used[b] = α × V_scalar[b] + (1 − α) × V_dq[b]
+//
+// α read on-device from ISV[alpha_slot], emitted by
+// rl_v_blend_alpha_controller (separate kernel) which adapts α
+// based on observed |V_dq − V_scalar| / |V_scalar| tracking ratio.
+//
+// α = 1.0: pure Plan A v2 behavior (V_scalar drives PPO advantage)
+// α = 0.0: pure Phase 4.3 behavior (V_dq drives PPO advantage)
+// Anywhere in between: adaptive blend
+//
+// Per feedback_cpu_is_read_only: pure device kernel; α computed
+// device-side by the controller.
+// Per pearl_no_host_branches_in_captured_graph: graph-safe (reads
+// ISV pointer, no host params).
+// Per feedback_no_atomicadd: sole-writer per cell.
+//
+// Block layout: grid=(ceil(B/256), 1, 1), block=(256, 1, 1). Pure
+// elementwise op.
+
+extern "C" __global__ void rl_v_blend(
+    const float* __restrict__ v_scalar,    // [B]
+    const float* __restrict__ v_dq,        // [B]
+    const float* __restrict__ isv,         // ISV bus
+    int          B,
+    int          alpha_slot,
+    float*       __restrict__ v_blended    // [B]
+) {
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
+    if (b >= B) return;
+    // Defensive clamp to [0, 1] — controller should keep α bounded
+    // (per pearl_audit_unboundedness_for_implicit_asymmetry) but a
+    // kernel-side guard protects against any controller bug.
+    const float a = fminf(1.0f, fmaxf(0.0f, isv[alpha_slot]));
+    v_blended[b] = a * v_scalar[b] + (1.0f - a) * v_dq[b];
+}

crates/ml-alpha/cuda/rl_v_blend_alpha_controller.cu

@@ -0,0 +1,160 @@
+// rl_v_blend_alpha_controller.cu — Phase 4.4 ISV-adaptive V blend (2026-05-30).
+//
+// Drives α ∈ [0, 1] for `V_used = α × V_scalar + (1−α) × V_dq` based
+// on observed V_dq vs V_scalar tracking ratio:
+//
+//   track_ratio = EMA(|V_dq − V_scalar|) / EMA(|V_scalar|)
+//
+//   if track_ratio > 1.5 × TARGET:   α ← min(α + step, 1.0)  ↑ V_scalar
+//   if track_ratio < TARGET / 1.5:   α ← max(α - step, 0.0)  ↑ V_dq
+//   else:                            hold α
+//
+// Per pearl_wiener_alpha_floor_for_nonstationary: Schulman bounded
+// discrete step, no Wiener-α blending of the controller variable
+// itself (α is the controlled quantity).
+//
+// Per pearl_first_observation_bootstrap: bootstrap α = 1.0 on
+// sentinel input (ISV[alpha_slot] == 0), EMAs use first observation
+// directly. After bootstrap, α never naturally returns to exactly 0
+// because Schulman step (0.01) is unlikely to land on it; if it
+// does, controller re-bootstraps harmlessly.
+//
+// Per pearl_blend_formulas_must_have_permanent_floor: dead-signal
+// guard — if EMA(|V_scalar|) < adaptive floor, hold α (no V signal
+// to calibrate against; the trainer hasn't seen meaningful rewards
+// yet).
+//
+// Per feedback_cpu_is_read_only: pure device kernel; reads V_scalar,
+// V_dq, ISV; emits α + EMAs to ISV. No host control.
+//
+// Adaptive controller floors (spec 2026-05-30-adaptive-controller-floor-design):
+// the 5 design constants below become ISV-driven so they can be tuned
+// at runtime without recompile. The dead-signal floor additionally
+// adapts to observed |V_scalar| variance via Welford slots 626/627/628
+// (Welford updates wired by the trainer pass alongside the other
+// controller Welford triples).
+//
+// Block layout: grid=(1, 1, 1), block=(BLOCK_X=1024, 1, 1). Single
+// block does parallel reduction over batch up to B=1024. Thread 0
+// performs the controller update.
+
+#define BLOCK_X 1024
+// ISV-driven slots — replace prior hardcoded design constants per the
+// 2026-05-30 adaptive-controller-floor spec.
+#define RL_V_BLEND_DEAD_SIGNAL_FLOOR_INDEX     621
+#define RL_V_BLEND_TARGET_TRACK_RATIO_INDEX    622
+#define RL_V_BLEND_SCHULMAN_STEP_INDEX         623
+#define RL_V_BLEND_EMA_ALPHA_INDEX             624
+#define RL_V_BLEND_BOOTSTRAP_ALPHA_INDEX       625
+#define RL_V_BLEND_SCALAR_VAR_COUNT_INDEX      626
+#define RL_V_BLEND_SCALAR_VAR_M2_INDEX         628
+// Adaptive-dead-floor scaling for the Welford std term — keeps the
+// floor at least one σ_observed × ADAPTIVE_DEAD_FLOOR_STD_SCALE above
+// numerical noise even when the ISV-resident absolute floor is tighter.
+#define ADAPTIVE_DEAD_FLOOR_STD_SCALE          0.1f
+
+extern "C" __global__ void rl_v_blend_alpha_controller(
+    const float* __restrict__ v_scalar,        // [B]
+    const float* __restrict__ v_dq,            // [B]
+    float*       __restrict__ isv,             // ISV bus
+    int          B,
+    int          alpha_slot,                   // ISV[α]
+    int          trackerr_ema_slot,            // ISV[|V_dq − V_scalar|_ema]
+    int          v_scalar_mag_ema_slot         // ISV[|V_scalar|_ema]  (dead-signal floor)
+) {
+    const int tid = threadIdx.x;
+    if (tid >= BLOCK_X) return;
+
+    // ── Per-thread partial sums over strided batch ──
+    float track_partial = 0.0f;
+    float mag_partial = 0.0f;
+    for (int b = tid; b < B; b += BLOCK_X) {
+        const float vs = v_scalar[b];
+        const float vd = v_dq[b];
+        track_partial += fabsf(vd - vs);
+        mag_partial += fabsf(vs);
+    }
+
+    // ── Tree-reduce in shared mem ──
+    __shared__ float s_t[BLOCK_X];
+    __shared__ float s_m[BLOCK_X];
+    s_t[tid] = track_partial;
+    s_m[tid] = mag_partial;
+    __syncthreads();
+
+    for (int stride = BLOCK_X / 2; stride > 0; stride >>= 1) {
+        if (tid < stride) {
+            s_t[tid] += s_t[tid + stride];
+            s_m[tid] += s_m[tid + stride];
+        }
+        __syncthreads();
+    }
+
+    if (tid == 0) {
+        const float inv_B = 1.0f / (float)B;
+        const float track_mean = s_t[0] * inv_B;
+        const float mag_mean   = s_m[0] * inv_B;
+
+        // ── ISV-driven design constants (spec 2026-05-30) ──
+        const float ema_alpha          = isv[RL_V_BLEND_EMA_ALPHA_INDEX];
+        const float target_track_ratio = isv[RL_V_BLEND_TARGET_TRACK_RATIO_INDEX];
+        const float schulman_step      = isv[RL_V_BLEND_SCHULMAN_STEP_INDEX];
+        const float bootstrap_alpha    = isv[RL_V_BLEND_BOOTSTRAP_ALPHA_INDEX];
+
+        // ── Adaptive dead-signal floor ─────────────────────────────────
+        // Combines the ISV-resident absolute floor with an observed
+        // |V_scalar| variance term (Welford sample variance =
+        // M² / (count − 1) when count > 1). Cold-start safe: count=0
+        // → var=0 → adaptive = isv[621] absolute default. Once Welford
+        // accumulates observations, the floor scales with σ_observed so
+        // the dead-signal gate adapts to whatever magnitude regime
+        // |V_scalar| settles into post-Phase-4.5.
+        const float vmag_count = isv[RL_V_BLEND_SCALAR_VAR_COUNT_INDEX];
+        const float vmag_var = (vmag_count > 1.0f)
+            ? isv[RL_V_BLEND_SCALAR_VAR_M2_INDEX] / (vmag_count - 1.0f)
+            : 0.0f;
+        const float vmag_std = sqrtf(vmag_var);
+        const float dead_floor_abs = isv[RL_V_BLEND_DEAD_SIGNAL_FLOOR_INDEX];
+        const float adaptive_dead_floor = fmaxf(dead_floor_abs,
+                                                 vmag_std * ADAPTIVE_DEAD_FLOOR_STD_SCALE);
+
+        // ── Bootstrap α on sentinel ──
+        float alpha = isv[alpha_slot];
+        if (alpha == 0.0f) {
+            alpha = bootstrap_alpha;
+        }
+
+        // ── First-observation bootstrap on EMAs ──
+        float prev_track_ema = isv[trackerr_ema_slot];
+        float prev_mag_ema   = isv[v_scalar_mag_ema_slot];
+        const float track_ema = (prev_track_ema == 0.0f)
+            ? track_mean
+            : (1.0f - ema_alpha) * prev_track_ema + ema_alpha * track_mean;
+        const float mag_ema = (prev_mag_ema == 0.0f)
+            ? mag_mean
+            : (1.0f - ema_alpha) * prev_mag_ema + ema_alpha * mag_mean;
+
+        // ── Dead-signal guard: V_scalar magnitude too small to calibrate against ──
+        if (mag_ema < adaptive_dead_floor) {
+            isv[trackerr_ema_slot] = track_ema;
+            isv[v_scalar_mag_ema_slot] = mag_ema;
+            isv[alpha_slot] = alpha;  // hold (write bootstrap if needed)
+            return;
+        }
+
+        // ── Track ratio + Schulman-bounded step on α ──
+        const float track_ratio = track_ema / mag_ema;
+        if (track_ratio > 1.5f * target_track_ratio) {
+            // V_dq diverged from V_scalar → raise α toward V_scalar
+            alpha = fminf(alpha + schulman_step, 1.0f);
+        } else if (track_ratio < target_track_ratio / 1.5f) {
+            // V_dq tracks V_scalar well → lower α toward V_dq
+            alpha = fmaxf(alpha - schulman_step, 0.0f);
+        }
+        // else: hold α (within band)
+
+        isv[alpha_slot] = alpha;
+        isv[trackerr_ema_slot] = track_ema;
+        isv[v_scalar_mag_ema_slot] = mag_ema;
+    }
+}

crates/ml-alpha/cuda/rl_win_rate_ema_update.cu

@@ -0,0 +1,93 @@
+// rl_win_rate_ema_update.cu — Layer 4 (Kelly) input EMA producer.
+//
+// Tracks observed per-step win_rate as an EMA across closed trades.
+// Spec: docs/superpowers/specs/2026-05-30-adaptive-risk-management-design.md
+//
+// Inputs:
+//   rewards[b]    f32 — per-batch realized pnl delta this step (shaped)
+//   dones[b]      f32 — 1.0 if a trade closed this step, else 0.0
+//
+// Trade outcome is derived inline: win = (done & reward > 0),
+// loss = (done & reward < 0), no-close otherwise.
+//
+// Output: ISV[RL_WIN_RATE_EMA_INDEX = 677]
+//
+// Bootstrap semantics per `pearl_first_observation_bootstrap`:
+//   sentinel = 0.5 (neutral 50% win rate); first non-trivial step replaces
+//   directly. Zero observations on a given step (no closes) → no update.
+//
+// Per `feedback_no_atomicadd`: single-thread single-block, sums across
+// b_size sequentially.
+// Per `feedback_cpu_is_read_only`: pure device kernel; trainer launches
+// each step after rl_fused_reward_pipeline writes rewards + dones.
+// Per `feedback_isv_for_adaptive_bounds`: EMA-α is currently a structural
+// constant 0.05 (≈ 20-trade effective window) — same pattern as
+// ema_update_per_step where α is a structural smoothing parameter.
+
+#include <stdint.h>
+
+#define RL_WIN_RATE_EMA_INDEX 677
+#define EMA_ALPHA_FAST        0.05f
+#define SENTINEL              0.5f
+// B-6 ISV-driven adaptive asymmetric Wiener-α. See B-6 spec for math.
+#define RL_EMA_ALPHA_SLOW_MIN_INDEX       721
+#define RL_EMA_TRUST_FULL_THRESHOLD_INDEX 722
+#define RL_EMA_CV_GAIN_INDEX              723
+#define RL_CUMULATIVE_DONES_INDEX         660
+#define RL_REWARD_MAG_VAR_COUNT_INDEX     615
+#define RL_REWARD_MAG_VAR_MEAN_INDEX      616
+#define RL_REWARD_MAG_VAR_M2_INDEX        617
+
+extern "C" __global__ void rl_win_rate_ema_update(
+    float*       __restrict__ isv,
+    const float* __restrict__ rewards,                   // [b_size] shaped pnl delta
+    const float* __restrict__ dones,                     // [b_size] 1.0 = close
+    int                       b_size
+) {
+    // Single-thread guard. Block shape (1,1,1) by contract.
+    if (threadIdx.x != 0 || threadIdx.y != 0 || threadIdx.z != 0) return;
+    if (blockIdx.x  != 0 || blockIdx.y  != 0 || blockIdx.z  != 0) return;
+
+    // Count this step's closed trades and wins (done & reward > 0).
+    int closed = 0;
+    int wins   = 0;
+    for (int b = 0; b < b_size; ++b) {
+        if (dones[b] >= 0.5f) {
+            closed += 1;
+            if (rewards[b] > 0.0f) wins += 1;
+        }
+    }
+    if (closed == 0) return;  // no observation this step
+
+    const float step_wr = (float)wins / (float)closed;
+    const float prev    = isv[RL_WIN_RATE_EMA_INDEX];
+
+    // B-6 ISV-driven adaptive asymmetric Wiener-α.
+    // α_slow_eff = α_slow_min + (α_fast − α_slow_min) × trust_eff
+    const float a_slow_min  = isv[RL_EMA_ALPHA_SLOW_MIN_INDEX];
+    const float a_fast      = EMA_ALPHA_FAST;
+    const float n_trades    = isv[RL_CUMULATIVE_DONES_INDEX];
+    const float n_full      = isv[RL_EMA_TRUST_FULL_THRESHOLD_INDEX];
+    const float cv_gain     = isv[RL_EMA_CV_GAIN_INDEX];
+
+    float trust = (n_full > 0.0f) ? fminf(1.0f, n_trades / n_full) : 1.0f;
+    if (cv_gain > 0.0f) {
+        const float wf_count = isv[RL_REWARD_MAG_VAR_COUNT_INDEX];
+        if (wf_count > 1.0f) {
+            const float wf_m2   = isv[RL_REWARD_MAG_VAR_M2_INDEX];
+            const float wf_mean = isv[RL_REWARD_MAG_VAR_MEAN_INDEX];
+            const float wf_var  = wf_m2 / (wf_count - 1.0f);
+            const float cv      = (wf_mean > 1e-6f) ? sqrtf(wf_var) / wf_mean : 0.0f;
+            trust *= expf(-cv * cv_gain);
+        }
+    }
+    const float a_slow_eff = a_slow_min + (a_fast - a_slow_min) * trust;
+
+    // wr_ema: slow-up (skeptical of high WR), fast-down (admit pessimism)
+    const float alpha = (step_wr > prev) ? a_slow_eff : a_fast;
+    float ema_new = (1.0f - alpha) * prev + alpha * step_wr;
+    // Hard-bound [0, 1] in case of any precision corner case.
+    if (ema_new < 0.0f) ema_new = 0.0f;
+    if (ema_new > 1.0f) ema_new = 1.0f;
+    isv[RL_WIN_RATE_EMA_INDEX] = ema_new;
+}

crates/ml-alpha/cuda/rollout_pack.cu

@@ -0,0 +1,42 @@
+// rollout_pack.cu — Per-step pack helpers for Phase 1B-B rollout collection.
+//
+// Spec: docs/superpowers/specs/2026-06-02-trainer-rollout-buffer-gae.md §1.2
+// Plan: docs/superpowers/plans/2026-06-02-trainer-rollout-buffer-gae-implementation.md §Phase 1B-B
+//
+// The trainer's per-step `dones_d` is `f32` in {0.0, 1.0} (legacy contract
+// driven by `compute_advantage_return` and the K-loop sampled buffers).
+// The rollout buffer's `dones_d` is `u8` (compact storage — 4× smaller,
+// matches the `gae_backward_sweep` kernel's `uint8_t*` input). This kernel
+// packs a per-step `[B]` f32 done vector into the rollout buffer's
+// `[B × T]` u8 slice at offset `bt = b * T + t` for the current write
+// cursor `t`.
+//
+// Single-thread-per-batch kernel (one thread per env). Deterministic by
+// construction — no atomic ops, no reductions, no shared memory. The
+// fmaxf clamp + ≥0.5 thresholding makes the conversion robust to fp32
+// noise (the trainer never produces non-{0, 1} dones, but the pack is
+// defensive).
+//
+// Determinism contract: each thread writes one distinct element, so the
+// kernel is bit-equal across runs for identical inputs. Compatible with
+// `pearl_determinism_achieved`.
+//
+// Per `feedback_no_atomicadd`: no atomic ops.
+// Per `feedback_cpu_is_read_only`: pure device-side, no host roundtrip.
+// Per `feedback_no_nvrtc`: pre-compiled cubin via build.rs.
+
+#include <stdint.h>
+
+extern "C" __global__ void rollout_pack_dones_f32_to_u8(
+    const float* __restrict__ dones_f32,   // [B] — per-step trainer dones (f32 in {0, 1})
+    uint8_t* __restrict__ dones_u8_bt,     // [B × T] — rollout buffer dones (u8)
+    const int B,
+    const int T,
+    const int t_cursor                     // current write cursor in [0, T)
+) {
+    const int b = blockIdx.x * blockDim.x + threadIdx.x;
+    if (b >= B) return;
+    const int idx = b * T + t_cursor;
+    const float d = dones_f32[b];
+    dones_u8_bt[idx] = (d >= 0.5f) ? (uint8_t)1 : (uint8_t)0;
+}

crates/ml-alpha/cuda/variable_selection.cu

@@ -26,6 +26,24 @@
 #define VSN_FEATURE_DIM 40
 #define VSN_BLOCK       64    // round up to warp-multiple; threads i >= FEATURE_DIM idle.
 
+// 2026-05-29 stride-mismatch fix.
+// VSN's input buffer (window_tensor_d) is allocated [B, K, ENCODER_INPUT_DIM=56]
+// by perception.rs (snap features [0..40) + per-batch broadcast context
+// [40..56) written by rl_encoder_context_broadcast). VSN only processes the
+// first VSN_FEATURE_DIM=40 features per row (snap features), but the input
+// rows are spaced 56 floats apart, not 40. The kernel originally indexed x
+// with stride VSN_FEATURE_DIM=40 — correct ONLY for row 0; every subsequent
+// row read mixed broadcast-context + snap features across the [B, K, 56]
+// row boundaries. Symptoms: intermittent step-4 NaN as accumulating trade
+// context magnitudes overflowed VSN's softmax via the bleed.
+//
+// Fix: use VSN_X_ROW_STRIDE=56 for reading x in both forward and backward.
+// Output (gates, y) and gradient outputs (grad_W, grad_b, grad_x) remain at
+// VSN_FEATURE_DIM=40 because the downstream consumers (Mamba2 L1 with
+// in_dim=40) read at compact 40-stride. grad_x is unused downstream (see
+// `vsn_grad_x_d` audit — write-only), so its stride doesn't matter.
+#define VSN_X_ROW_STRIDE 56   // = ENCODER_INPUT_DIM in heads.rs / perception.rs
+
 extern "C" __global__ void variable_selection_fwd(
     const float* __restrict__ W_vsn,         // [FEATURE_DIM, FEATURE_DIM]
     const float* __restrict__ b_vsn,         // [FEATURE_DIM]
@@ -38,7 +56,7 @@ extern "C" __global__ void variable_selection_fwd(
     int tid = threadIdx.x;
     if (row >= n_rows) return;
 
-    const float* x_row = x + (long long)row * VSN_FEATURE_DIM;
+    const float* x_row = x + (long long)row * VSN_X_ROW_STRIDE;
 
     // Shared mem: gate_logit + max-reduce scratch + sum-reduce scratch.
     __shared__ float s_logit[VSN_FEATURE_DIM];
@@ -170,7 +188,7 @@ extern "C" __global__ void variable_selection_bwd(
     float dy_i = 0.0f;
     if (tid < VSN_FEATURE_DIM) {
         gates_i = gates[(long long)row * VSN_FEATURE_DIM + tid];
-        x_i = x[(long long)row * VSN_FEATURE_DIM + tid];
+        x_i = x[(long long)row * VSN_X_ROW_STRIDE + tid];
         dy_i = grad_y[(long long)row * VSN_FEATURE_DIM + tid];
         s_gates[tid] = gates_i;
         s_dgates[tid] = dy_i * x_i;
@@ -201,7 +219,7 @@ extern "C" __global__ void variable_selection_bwd(
         const float dl_t = s_dlogit[tid];
         #pragma unroll
         for (int j = 0; j < VSN_FEATURE_DIM; ++j) {
-            const float xj = x[(long long)row * VSN_FEATURE_DIM + j];
+            const float xj = x[(long long)row * VSN_X_ROW_STRIDE + j];
             grad_W_vsn_scratch[row_FF + (long long)tid * VSN_FEATURE_DIM + j]
                 += dl_t * xj;
         }

crates/ml-alpha/src/cublas_determinism.rs

@@ -0,0 +1,77 @@
+//! cuBLAS math-mode helper for the determinism foundation (spec §2.B + §4).
+//!
+//! Per `docs/superpowers/notes/2026-06-02-determinism-phase2.2-mamba2-investigation.md`:
+//! the cuBLAS GEMM default algorithm (`CUBLAS_GEMM_DFALT`) permits split-K
+//! accumulation with non-deterministic ordering on Ampere+ when TF32 mode
+//! is on. The fix is to call `cublasSetMathMode(handle, CUBLAS_PEDANTIC_MATH)`
+//! at every handle construction site — that filters out the non-deterministic
+//! algorithm variants.
+//!
+//! Spec §4 dev/prod toggle: `FOXHUNT_DETERMINISTIC` env var (default "1" in
+//! dev, where verdict trust matters; "0" in production, where the 10-15%
+//! TF32 speed gain matters more than reproducibility).
+//!
+//! Call this immediately after `CudaBlas::new(...)` at every handle site
+//! in `crates/ml-alpha/src/`. The 3 known sites (2026-06-02) are:
+//!   - `mamba2_block.rs`        (Mamba2Block::new, line ~535)
+//!   - `rl/dqn.rs`              (DqnHead::new, line ~364)
+//!   - `rl/iqn.rs`              (IqnHead::new, line ~261)
+//!
+//! Per `feedback_isv_for_adaptive_bounds.md`: env-var read is one-shot at
+//! handle construction; the mode is fixed for the lifetime of the handle.
+//! No per-step ISV adjustment is needed (or possible, since the mode is
+//! handle-level state).
+
+use anyhow::{anyhow, Result};
+use cudarc::cublas::CudaBlas;
+
+/// Apply the dev/prod-toggleable cuBLAS math mode to a freshly-constructed
+/// `CudaBlas` handle.
+///
+/// `FOXHUNT_DETERMINISTIC=1` (default) → `CUBLAS_PEDANTIC_MATH`. Deterministic
+/// across runs; ~10-15% slower than TF32 on Ampere+ GEMMs.
+///
+/// `FOXHUNT_DETERMINISTIC=0` → `CUBLAS_TF32_TENSOR_OP_MATH`. Faster, but
+/// `CUBLAS_GEMM_DFALT` may pick non-deterministic split-K variants — same-seed
+/// runs can diverge by ~1e-6 after a handful of GEMMs, cascading via the
+/// optimizer into ~10% trajectory drift over 200 steps.
+///
+/// Returns the input handle wrapped in `Ok` on success (passthrough for
+/// ergonomic call-site chaining), or `Err` if the cuBLAS call fails.
+pub fn apply_deterministic_math_mode(cublas: CudaBlas) -> Result<CudaBlas> {
+    // Per `pearl_build_rs_rerun_if_env_changed.md`: this env-var read is a
+    // runtime decision (not a build-time one), so no `cargo:rerun-if-env-changed`
+    // is needed. The env var is checked once per handle construction.
+    //
+    // Phase 2.4 control-mode addition (2026-06-02): added `2` as control
+    // mode (CUBLAS_DEFAULT_MATH — no TF32, no PEDANTIC, pure FP32) to
+    // disambiguate whether PEDANTIC fully eliminates split-K or just
+    // some variants. Per dispatch ask.
+    let env_value = std::env::var("FOXHUNT_DETERMINISTIC")
+        .unwrap_or_else(|_| "1".to_string());
+
+    let mode = match env_value.as_str() {
+        "0" => cudarc::cublas::sys::cublasMath_t::CUBLAS_TF32_TENSOR_OP_MATH,
+        "2" => cudarc::cublas::sys::cublasMath_t::CUBLAS_DEFAULT_MATH,
+        _ => cudarc::cublas::sys::cublasMath_t::CUBLAS_PEDANTIC_MATH,
+    };
+
+    unsafe {
+        cudarc::cublas::sys::cublasSetMathMode(*cublas.handle(), mode)
+            .result()
+            .map_err(|e| anyhow!("cublasSetMathMode {mode:?}: {e:?}"))?;
+    }
+
+    // Print once per handle so callers can verify the env var propagated.
+    // Phase 2.4: this is essential diagnostics — the Phase 2.3 outcome
+    // note claimed PEDANTIC was active but later determinism-check runs
+    // showed attn_q still diverging, so we need explicit confirmation.
+    static MODE_PRINTED: std::sync::OnceLock<()> = std::sync::OnceLock::new();
+    MODE_PRINTED.get_or_init(|| {
+        eprintln!(
+            "[cublas_determinism] FOXHUNT_DETERMINISTIC={env_value} → mode={mode:?}"
+        );
+    });
+
+    Ok(cublas)
+}

crates/ml-alpha/src/data/gpu_dataset.rs

@@ -188,7 +188,6 @@ impl GpuDataLoader {
         soa: &SoaBufferPtrs,
         seq_len: usize,
         batch_size: usize,
-        label_outs: [u64; 5],
     ) -> Result<()> {
         let mut args = RawArgs::new();
         args.push_ptr(dataset.snapshots_d.raw_ptr());
@@ -211,18 +210,6 @@ impl GpuDataLoader {
         args.push_ptr(self.sample_file_offset_d.raw_ptr());
         args.push_ptr(self.sample_anchor_d.raw_ptr());
         args.push_ptr(self.sample_file_idx_d.raw_ptr());
-        // Fused label gather arguments
-        args.push_i32(dataset.total_snapshots as i32);
-        args.push_ptr(dataset.labels_d.raw_ptr());
-        args.push_ptr(dataset.outcome_prof_long_d.raw_ptr());
-        args.push_ptr(dataset.outcome_prof_short_d.raw_ptr());
-        args.push_ptr(dataset.outcome_size_long_d.raw_ptr());
-        args.push_ptr(dataset.outcome_size_short_d.raw_ptr());
-        args.push_ptr(label_outs[0]);
-        args.push_ptr(label_outs[1]);
-        args.push_ptr(label_outs[2]);
-        args.push_ptr(label_outs[3]);
-        args.push_ptr(label_outs[4]);
         args.push_i32(batch_size as i32);
         let mut ptrs = args.build_arg_ptrs();
         unsafe {

crates/ml-alpha/src/lib.rs

@@ -1,3 +1,10 @@
+// The `build_diag_value` builder in `trainer::integrated` constructs the
+// per-step diag JSONL via a deeply-nested `serde_json::json!{ ... }` macro
+// (~30 nested object blocks × per-block field counts). The macro's
+// recursive expansion exceeds serde_json's default budget of 128 levels.
+// Raising to 256 covers the current schema with headroom.
+#![recursion_limit = "256"]
+
 //! ml-alpha — CfC perception + multi-horizon alpha heads.
 //!
 //! Phase A (this crate): snapshot-level CfC trunk + 5 horizon heads,
@@ -46,6 +53,11 @@ pub mod multi_horizon_labels;
 // Gate reference only — Mamba2 baseline against which CfC must compete.
 pub mod mamba2_block;
 
+// Determinism foundation (spec 2026-06-02 §2.B): cuBLAS PEDANTIC mode helper
+// used at every CudaBlas::new() site to disable non-deterministic GEMM
+// algorithms. Gated by FOXHUNT_DETERMINISTIC env var (default "1" in dev).
+pub mod cublas_determinism;
+
 pub use isv::IsvBus;
 pub use multi_horizon_labels::{generate_labels, LongHorizonLabels};
 // Re-exports added as the relevant tasks land:

crates/ml-alpha/src/mamba2_block.rs

@@ -534,6 +534,13 @@ impl Mamba2Block {
         // our gemm shapes (largest is hidden_dim×in_dim ≈ 128×32).
         let cublas = CudaBlas::new(Arc::clone(&stream))
             .map_err(|e| anyhow!("Mamba2Block: cuBLAS init failed: {e}"))?;
+        // Determinism foundation (spec 2026-06-02 §2.B):
+        // Disable non-deterministic GEMM algorithms. Per the Phase 2.2
+        // mamba2 investigation, the 3 backward GEMMs in
+        // backward_from_h_enriched_seq_full_into were the root cause of
+        // the eval-pnl drift between same-seed runs.
+        let cublas = crate::cublas_determinism::apply_deterministic_math_mode(cublas)
+            .map_err(|e| anyhow!("Mamba2Block: cublas determinism setup: {e}"))?;
         const CUBLAS_WORKSPACE_BYTES: usize = 8 * 1024 * 1024;
         let cublas_workspace = stream
             .alloc_zeros::<u8>(CUBLAS_WORKSPACE_BYTES)
@@ -547,12 +554,6 @@ impl Mamba2Block {
             )
             .result()
             .map_err(|e| anyhow!("Mamba2Block: cublasSetWorkspace_v2: {e:?}"))?;
-            cudarc::cublas::sys::cublasSetMathMode(
-                *cublas.handle(),
-                cudarc::cublas::sys::cublasMath_t::CUBLAS_TF32_TENSOR_OP_MATH,
-            )
-            .result()
-            .map_err(|e| anyhow!("Mamba2Block: cublasSetMathMode TF32: {e:?}"))?;
         }
 
         // ── Parameter allocation + initialisation. ──────────────────────

crates/ml-alpha/src/rl/band_head.rs

@@ -0,0 +1,597 @@
+//! Phase 4-A: No-transaction-band head.
+//!
+//! Small two-output linear projection `h_t [B, HIDDEN_DIM] → band_pre [B, 2]`,
+//! followed by an asymmetric `±|tanh| × N_max_eff` activation that produces
+//! a per-batch lower bound `b_l ≤ 0` and upper bound `b_u ≥ 0` in position
+//! (lots) units. The action selection layer (`rl_band_mask.cu`) forces
+//! `actions[b] = Hold` whenever `position_lots[b] ∈ [b_l, b_u]`, encoding
+//! the Davis-Norman (1990) optimal no-transaction region as an architectural
+//! default rather than a learned preference.
+//!
+//! Spec: `docs/superpowers/specs/2026-06-03-no-transaction-band-architecture.md`.
+//! Pearls: `pearl_scoped_init_seed_for_reproducibility`,
+//! `pearl_bootstrap_must_respect_clamp_range`,
+//! `pearl_determinism_achieved`,
+//! `pearl_foxhunt_pi_trained_by_q_distillation_not_ppo`.
+//!
+//! ## Phase 4-A scope
+//!
+//! This module ships the FORWARD path only (sized weights + linear projection
+//! + asymmetric activation + turnover regularizer loss kernel handles). The
+//! head's master gate at `RL_BAND_ENABLED_INDEX` (slot 799) bootstraps to
+//! `0.0` (OFF), preserving bit-equality with the Phase 3D baseline until an
+//! operator flips the slot for A/B testing.
+//!
+//! The backward chain into the encoder (`grad_h_t` accumulation) is wired
+//! by the turnover regularizer kernel writing to per-batch scratch; the
+//! trainer integration site launches the kernel for OBSERVABILITY only in
+//! Phase 4-A — the gradient is materialised but NOT folded into the encoder
+//! optimizer step. Phase 4-B will land the adaptive controller plus the
+//! full encoder backward chain.
+
+use std::sync::Arc;
+
+use anyhow::{Context, Result};
+use cudarc::driver::{
+    CudaFunction, CudaModule, CudaSlice, CudaStream, DevicePtrMut,
+};
+use cudarc::driver::sys::CUstream;
+use ml_core::cuda_autograd::init::scoped_init_seed;
+use ml_core::device::MlDevice;
+use rand::{Rng, SeedableRng};
+use rand_chacha::ChaCha8Rng;
+
+use crate::heads::HIDDEN_DIM;
+use crate::pinned_mem::MappedF32Buffer;
+use crate::trainer::raw_launch::{RawArgs, raw_launch};
+
+const BAND_HEAD_FORWARD_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_head_forward.cubin"));
+const BAND_MASK_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_mask.cubin"));
+const BAND_TURNOVER_LOSS_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_turnover_loss.cubin"));
+const BAND_FRAC_AGGREGATE_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_frac_aggregate.cubin"));
+const BAND_TURNOVER_CONTROLLER_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_turnover_controller.cubin"));
+const BAND_HEAD_BACKWARD_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/rl_band_head_backward.cubin"));
+
+/// Number of band outputs (`b_l`, `b_u`).
+pub const BAND_OUT: usize = 2;
+
+/// Construction config for [`BandHead`].
+#[derive(Clone, Debug)]
+pub struct BandHeadConfig {
+    /// Encoder hidden dim feeding the band head.
+    pub hidden_dim: usize,
+    /// Batch size — used to pre-allocate per-batch scratch buffers.
+    pub b_size: usize,
+    /// Random seed for Xavier init. Reproducibility per
+    /// `pearl_scoped_init_seed_for_reproducibility`.
+    pub seed: u64,
+    /// Initial bias for `b_l` pre-activation (drives `b_l_init = activation
+    /// × N_max_eff`). Set by the trainer from `RL_BAND_LOWER_INIT_INDEX`
+    /// bootstrap (−0.5 → `atanh(0.5)` ≈ −0.549 after sign flip; the trainer
+    /// passes the `atanh`-adjusted value).
+    pub b_l_init_bias: f32,
+    /// Initial bias for `b_u` pre-activation.
+    pub b_u_init_bias: f32,
+}
+
+/// No-transaction-band head. Lives parallel to [`crate::rl::ppo::PolicyHead`]
+/// and [`crate::rl::multi_head_policy::MultiHeadPolicy`]; produces a per-batch
+/// `(b_l, b_u)` pair consumed by `rl_band_mask.cu` to override post-sampling
+/// actions to Hold when `position ∈ [b_l, b_u]`.
+pub struct BandHead {
+    #[allow(dead_code)]
+    cfg: BandHeadConfig,
+    stream: Arc<CudaStream>,
+    raw_stream: CUstream,
+
+    // ── Kernel handles ────────────────────────────────────────────────
+    _forward_module: Arc<CudaModule>,
+    linear_fwd_fn: CudaFunction,
+    apply_activation_fn: CudaFunction,
+    _mask_module: Arc<CudaModule>,
+    mask_fn: CudaFunction,
+    _turnover_loss_module: Arc<CudaModule>,
+    turnover_loss_fn: CudaFunction,
+    // ── Phase 4-B handles ────────────────────────────────────────────
+    _frac_aggregate_module: Arc<CudaModule>,
+    frac_aggregate_fn: CudaFunction,
+    _turnover_controller_module: Arc<CudaModule>,
+    turnover_controller_fn: CudaFunction,
+    _backward_module: Arc<CudaModule>,
+    backward_fn: CudaFunction,
+
+    // ── Online weights ────────────────────────────────────────────────
+    /// `W_band[j, c]` row-major over `(j ∈ {0, 1}, c ∈ HIDDEN_DIM)`. Two
+    /// output neurons — small Xavier init scaled by 0.01 (matches PolicyHead).
+    pub w_band_d: CudaSlice<f32>,
+    /// `b_band[j]` — per-output bias. Initialised from `cfg.b_l_init_bias`
+    /// and `cfg.b_u_init_bias` so the first forward yields `b_l ≈ −0.5 ·
+    /// N_max_eff` and `b_u ≈ +0.5 · N_max_eff` (moderate initial band).
+    pub b_band_d: CudaSlice<f32>,
+
+    // ── Forward output buffers (persisted for diag) ───────────────────
+    /// `[B × 2]` pre-activation linear outputs.
+    pub band_pre_d: CudaSlice<f32>,
+    /// `[B × 2]` post-activation band — `b_l ≤ 0 ≤ b_u`, in lots units.
+    /// Consumed by `rl_band_mask.cu` and `rl_band_turnover_loss.cu`.
+    pub band_out_d: CudaSlice<f32>,
+
+    // ── Turnover-loss per-batch scratch (observability in Phase 4-A) ──
+    /// `[B]` — sigmoid-surrogate "in band" mass per batch element.
+    pub m_soft_per_b_d: CudaSlice<f32>,
+    /// `[B]` — per-batch loss contribution (same scalar value, ×1/B).
+    pub loss_per_b_d: CudaSlice<f32>,
+    /// `[B × 2]` — per-batch grad on `(b_l, b_u)` from the turnover
+    /// regularizer. Phase 4-B folds into encoder grad via `backward()`.
+    pub grad_band_per_b_d: CudaSlice<f32>,
+
+    // ── Phase 4-B backward-chain scratch ──────────────────────────────
+    /// `[B × BAND_OUT × HIDDEN_DIM]` — per-batch weight grads. Caller
+    /// reduces via `reduce_axis0` into `grad_w_d`.
+    pub grad_w_per_b_d: CudaSlice<f32>,
+    /// `[B × BAND_OUT]` — per-batch bias grads. Reduced into `grad_b_d`.
+    pub grad_b_per_b_d: CudaSlice<f32>,
+    /// `[B × HIDDEN_DIM]` — per-batch encoder-input grad (OVERWRITE).
+    /// Caller folds into encoder grad via `grad_h_accumulate_scaled`.
+    pub grad_h_t_d: CudaSlice<f32>,
+    /// `[BAND_OUT × HIDDEN_DIM]` — reduced weight grad, Adam target.
+    pub grad_w_d: CudaSlice<f32>,
+    /// `[BAND_OUT]` — reduced bias grad, Adam target.
+    pub grad_b_d: CudaSlice<f32>,
+}
+
+impl BandHead {
+    /// Allocate weights + forward buffers, load cubins.
+    ///
+    /// Weight init: Xavier-uniform scaled by 0.01 (matches PolicyHead) —
+    /// keeps initial pre-activation near zero so `tanh(0) = 0` and the band
+    /// boundary is entirely driven by the bias init.
+    pub fn new(dev: &MlDevice, cfg: BandHeadConfig) -> Result<Self> {
+        let stream: Arc<CudaStream> = dev
+            .cuda_stream()
+            .context("band_head stream")?
+            .clone();
+        let ctx = dev.cuda_context().context("band_head ctx")?;
+
+        // ── Load cubins ──────────────────────────────────────────────
+        let forward_module = ctx
+            .load_cubin(BAND_HEAD_FORWARD_CUBIN.to_vec())
+            .context("load rl_band_head_forward cubin")?;
+        let linear_fwd_fn = forward_module
+            .load_function("rl_band_head_linear_fwd")
+            .context("load rl_band_head_linear_fwd")?;
+        let apply_activation_fn = forward_module
+            .load_function("rl_band_apply_activation")
+            .context("load rl_band_apply_activation")?;
+        let mask_module = ctx
+            .load_cubin(BAND_MASK_CUBIN.to_vec())
+            .context("load rl_band_mask cubin")?;
+        let mask_fn = mask_module
+            .load_function("rl_band_mask")
+            .context("load rl_band_mask")?;
+        let turnover_loss_module = ctx
+            .load_cubin(BAND_TURNOVER_LOSS_CUBIN.to_vec())
+            .context("load rl_band_turnover_loss cubin")?;
+        let turnover_loss_fn = turnover_loss_module
+            .load_function("rl_band_turnover_loss")
+            .context("load rl_band_turnover_loss")?;
+        let frac_aggregate_module = ctx
+            .load_cubin(BAND_FRAC_AGGREGATE_CUBIN.to_vec())
+            .context("load rl_band_frac_aggregate cubin")?;
+        let frac_aggregate_fn = frac_aggregate_module
+            .load_function("rl_band_frac_aggregate")
+            .context("load rl_band_frac_aggregate")?;
+        let turnover_controller_module = ctx
+            .load_cubin(BAND_TURNOVER_CONTROLLER_CUBIN.to_vec())
+            .context("load rl_band_turnover_controller cubin")?;
+        let turnover_controller_fn = turnover_controller_module
+            .load_function("rl_band_turnover_controller")
+            .context("load rl_band_turnover_controller")?;
+        let backward_module = ctx
+            .load_cubin(BAND_HEAD_BACKWARD_CUBIN.to_vec())
+            .context("load rl_band_head_backward cubin")?;
+        let backward_fn = backward_module
+            .load_function("rl_band_head_backward")
+            .context("load rl_band_head_backward")?;
+
+        // ── Weight init: Xavier-0.01 + bias seed ─────────────────────
+        // Per pearl_scoped_init_seed_for_reproducibility, install the
+        // scoped seed guard before drawing Xavier samples. The salt is
+        // an arbitrary fixed offset so the band-head init does not collide
+        // with PolicyHead / ValueHead / MultiHeadPolicy seeds.
+        let band_seed = cfg.seed.wrapping_add(0xBA_5EED_u64);
+        let _seed_guard = scoped_init_seed(band_seed);
+        let mut rng = ChaCha8Rng::seed_from_u64(band_seed);
+
+        let n_in = cfg.hidden_dim;
+        let scale = 0.01_f32 * (6.0_f32 / (n_in + BAND_OUT) as f32).sqrt();
+        let w_host: Vec<f32> = (0..BAND_OUT * n_in)
+            .map(|_| rng.gen_range(-scale..scale))
+            .collect();
+        let b_host: Vec<f32> = vec![cfg.b_l_init_bias, cfg.b_u_init_bias];
+
+        let w_band_d = upload(&stream, &w_host)?;
+        let b_band_d = upload(&stream, &b_host)?;
+
+        // ── Forward output buffers ───────────────────────────────────
+        let band_pre_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * BAND_OUT)
+            .context("alloc band_pre_d")?;
+        let band_out_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * BAND_OUT)
+            .context("alloc band_out_d")?;
+
+        // ── Turnover-loss per-batch scratch ──────────────────────────
+        let m_soft_per_b_d = stream
+            .alloc_zeros::<f32>(cfg.b_size)
+            .context("alloc m_soft_per_b_d")?;
+        let loss_per_b_d = stream
+            .alloc_zeros::<f32>(cfg.b_size)
+            .context("alloc loss_per_b_d")?;
+        let grad_band_per_b_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * BAND_OUT)
+            .context("alloc grad_band_per_b_d")?;
+
+        // ── Phase 4-B backward scratch ───────────────────────────────
+        let grad_w_per_b_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * BAND_OUT * cfg.hidden_dim)
+            .context("alloc grad_w_per_b_d")?;
+        let grad_b_per_b_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * BAND_OUT)
+            .context("alloc grad_b_per_b_d")?;
+        let grad_h_t_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.hidden_dim)
+            .context("alloc band grad_h_t_d")?;
+        let grad_w_d = stream
+            .alloc_zeros::<f32>(BAND_OUT * cfg.hidden_dim)
+            .context("alloc band grad_w_d")?;
+        let grad_b_d = stream
+            .alloc_zeros::<f32>(BAND_OUT)
+            .context("alloc band grad_b_d")?;
+
+        let raw_stream = stream.cu_stream();
+        Ok(Self {
+            cfg,
+            stream,
+            raw_stream,
+            _forward_module: forward_module,
+            linear_fwd_fn,
+            apply_activation_fn,
+            _mask_module: mask_module,
+            mask_fn,
+            _turnover_loss_module: turnover_loss_module,
+            turnover_loss_fn,
+            _frac_aggregate_module: frac_aggregate_module,
+            frac_aggregate_fn,
+            _turnover_controller_module: turnover_controller_module,
+            turnover_controller_fn,
+            _backward_module: backward_module,
+            backward_fn,
+            w_band_d,
+            b_band_d,
+            band_pre_d,
+            band_out_d,
+            m_soft_per_b_d,
+            loss_per_b_d,
+            grad_band_per_b_d,
+            grad_w_per_b_d,
+            grad_b_per_b_d,
+            grad_h_t_d,
+            grad_w_d,
+            grad_b_d,
+        })
+    }
+
+    /// Stream used to launch all kernels owned by this head.
+    pub fn stream(&self) -> &Arc<CudaStream> {
+        &self.stream
+    }
+
+    /// Phase 4-A forward — emits `band_out_d [B × 2]` with `b_l ≤ 0 ≤ b_u`.
+    ///
+    /// Two-stage launch on the same stream:
+    ///   1. `rl_band_head_linear_fwd` — `band_pre = b_band + W_band · h_t`.
+    ///   2. `rl_band_apply_activation` — `b_l = −|tanh(pre[0])| · N_max_eff`,
+    ///      `b_u = +|tanh(pre[1])| · N_max_eff`.
+    ///
+    /// `N_max_eff` is read inside the activation kernel from
+    /// `RL_HEAT_CAP_MAX_LOTS_INDEX` (slot 504).
+    pub fn forward(
+        &mut self,
+        h_t: &CudaSlice<f32>,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+    ) -> Result<()> {
+        debug_assert_eq!(h_t.len(), b_size * HIDDEN_DIM);
+        debug_assert_eq!(self.band_pre_d.len(), b_size * BAND_OUT);
+        debug_assert_eq!(self.band_out_d.len(), b_size * BAND_OUT);
+
+        let b_i = b_size as i32;
+
+        // ── Stage 1: linear forward ──────────────────────────────────
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(self.w_band_d.raw_ptr());
+            args.push_ptr(self.b_band_d.raw_ptr());
+            args.push_ptr(h_t.raw_ptr());
+            args.push_i32(b_i);
+            args.push_ptr(self.band_pre_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.linear_fwd_fn.cu_function(),
+                    (b_size as u32, BAND_OUT as u32, 1),
+                    (HIDDEN_DIM as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("rl_band_head_linear_fwd: {:?}", e))?;
+            }
+        }
+
+        // ── Stage 2: asymmetric ±|tanh| × N_max_eff activation ──────
+        {
+            let grid_x = ((b_size as u32) + 31) / 32;
+            let mut args = RawArgs::new();
+            args.push_ptr(self.band_pre_d.raw_ptr());
+            args.push_ptr(*isv_dev_ptr);
+            args.push_i32(b_i);
+            args.push_ptr(self.band_out_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.apply_activation_fn.cu_function(),
+                    (grid_x.max(1), 1, 1),
+                    (32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("rl_band_apply_activation: {:?}", e))?;
+            }
+        }
+        Ok(())
+    }
+
+    /// Phase 4-A mask launch — overrides `actions[b]` to `Hold` whenever
+    /// `position_lots[b] ∈ [band_out_d[b, 0], band_out_d[b, 1]]`. Reads
+    /// the master gate at `RL_BAND_ENABLED_INDEX` (slot 799) and returns a
+    /// no-op when ≤ 0.5 (Phase 3D bit-equality).
+    ///
+    /// MUST be launched OUTSIDE graph capture (matches the existing
+    /// `rl_confidence_gate` pattern at `integrated.rs:7487-7530`) since the
+    /// host-side master-gate branch precedes it.
+    pub fn launch_mask(
+        &self,
+        actions_d: &CudaSlice<i32>,
+        pos_state_d: &CudaSlice<u8>,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+        pos_bytes: usize,
+    ) -> Result<()> {
+        debug_assert_eq!(actions_d.len(), b_size);
+        debug_assert_eq!(self.band_out_d.len(), b_size * BAND_OUT);
+
+        let mut args = RawArgs::new();
+        args.push_ptr(actions_d.raw_ptr());
+        args.push_ptr(self.band_out_d.raw_ptr());
+        args.push_ptr(pos_state_d.raw_ptr());
+        args.push_ptr(*isv_dev_ptr);
+        args.push_i32(b_size as i32);
+        args.push_i32(pos_bytes as i32);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.mask_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (1, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_band_mask: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Phase 4-B per-step `frac_not_masked` reducer launch. Reads
+    /// `band_out_d` + `pos_state` and writes the per-step fleet-fraction
+    /// (= 1 − frac_in_band) to `RL_BAND_FRAC_NOT_MASKED_OBSERVED_INDEX`
+    /// (slot 812) via a single-block tree-reduce. Consumed by the
+    /// turnover controller on the same step.
+    ///
+    /// Master-gated at slot 799 inside the kernel: when the band is OFF
+    /// the kernel writes 0.0 and returns. Launched OUTSIDE graph capture
+    /// (matches the controller below — both run host-side post-forward
+    /// once `band_out_d` is materialised).
+    pub fn launch_frac_aggregate(
+        &self,
+        pos_state_d: &CudaSlice<u8>,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+        pos_bytes: usize,
+    ) -> Result<()> {
+        // Block-dim = next pow-of-two ≥ b_size, capped at 1024 (single
+        // block tree-reduce semantics; the kernel iterates with stride
+        // bdim if b_size > bdim).
+        let block_dim = (b_size as u32)
+            .next_power_of_two()
+            .clamp(1, 1024);
+        let smem = (block_dim as usize * std::mem::size_of::<f32>()) as u32;
+        let mut args = RawArgs::new();
+        args.push_ptr(self.band_out_d.raw_ptr());
+        args.push_ptr(pos_state_d.raw_ptr());
+        args.push_ptr(*isv_dev_ptr);
+        args.push_i32(b_size as i32);
+        args.push_i32(pos_bytes as i32);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.frac_aggregate_fn.cu_function(),
+                (1, 1, 1),
+                (block_dim, 1, 1),
+                smem,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_band_frac_aggregate: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Phase 4-B adaptive turnover-target controller launch. Single-thread
+    /// kernel; reads the per-step `frac_not_masked` written by
+    /// `launch_frac_aggregate` and updates the EMA (slot 809) +
+    /// adaptive target (slot 811) using first-observation bootstrap +
+    /// asymmetric Schulman-bounded adapter.
+    ///
+    /// MUST be launched AFTER `launch_frac_aggregate` (which writes the
+    /// controller's input slot) and BEFORE `launch_turnover_loss` on the
+    /// same step (which reads slot 811).
+    pub fn launch_turnover_controller(&self, isv_dev_ptr: &u64) -> Result<()> {
+        let mut args = RawArgs::new();
+        args.push_ptr(*isv_dev_ptr);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.turnover_controller_fn.cu_function(),
+                (1, 1, 1),
+                (1, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_band_turnover_controller: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Phase 4-B turnover regularizer loss launch. Now wired into the
+    /// joint-loss path (`step_synthetic_body`) as the band's training
+    /// signal: emits `loss_per_b_d` + `grad_band_per_b_d` consumed by
+    /// `backward()` on the same step.
+    ///
+    /// `turnover_t` is the host-supplied scalar mean of `(1 − m_soft)` from
+    /// the previous step (Option (b) target-tracking semantics per spec
+    /// §3.1). The kernel uses `turnover_t − target` for the loss; the
+    /// per-batch gradient routes through the sigmoid surrogate `(1 − m_soft)`.
+    pub fn launch_turnover_loss(
+        &mut self,
+        pos_state_d: &CudaSlice<u8>,
+        isv_dev_ptr: &u64,
+        turnover_t: f32,
+        b_size: usize,
+        pos_bytes: usize,
+    ) -> Result<()> {
+        let grid_x = ((b_size as u32) + 31) / 32;
+        let mut args = RawArgs::new();
+        args.push_ptr(self.band_out_d.raw_ptr());
+        args.push_ptr(pos_state_d.raw_ptr());
+        args.push_ptr(*isv_dev_ptr);
+        args.push_f32(turnover_t);
+        args.push_i32(b_size as i32);
+        args.push_i32(pos_bytes as i32);
+        args.push_ptr(self.m_soft_per_b_d.raw_ptr());
+        args.push_ptr(self.loss_per_b_d.raw_ptr());
+        args.push_ptr(self.grad_band_per_b_d.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.turnover_loss_fn.cu_function(),
+                (grid_x.max(1), 1, 1),
+                (32, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_band_turnover_loss: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Phase 4-B backward chain — propagates `grad_band_per_b_d [B × 2]`
+    /// (produced by `launch_turnover_loss`) through the asymmetric
+    /// `±|tanh| × N_max_eff` activation and the linear projection into:
+    ///   * `grad_w_per_b_d [B × BAND_OUT × HIDDEN_DIM]` — per-batch
+    ///     weight grad scratch; caller reduces via `reduce_axis0` into
+    ///     `grad_w_d` for Adam consumption.
+    ///   * `grad_b_per_b_d [B × BAND_OUT]` — per-batch bias grad scratch.
+    ///   * `grad_h_t_d [B × HIDDEN_DIM]` — encoder-input grad (OVERWRITE).
+    ///     Caller folds into the encoder grad combiner via
+    ///     `grad_h_accumulate_scaled`.
+    ///
+    /// The kernel reads the master gate at slot 799 and writes zeros when
+    /// disabled — bit-equality with the Phase 3D baseline is preserved
+    /// even if the host-side launch is unconditional.
+    pub fn backward(
+        &mut self,
+        h_t: &CudaSlice<f32>,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+    ) -> Result<()> {
+        debug_assert_eq!(h_t.len(), b_size * HIDDEN_DIM);
+        debug_assert_eq!(
+            self.grad_w_per_b_d.len(),
+            b_size * BAND_OUT * HIDDEN_DIM
+        );
+        debug_assert_eq!(self.grad_b_per_b_d.len(), b_size * BAND_OUT);
+        debug_assert_eq!(self.grad_h_t_d.len(), b_size * HIDDEN_DIM);
+
+        let mut args = RawArgs::new();
+        args.push_ptr(self.w_band_d.raw_ptr());
+        args.push_ptr(self.band_pre_d.raw_ptr());
+        args.push_ptr(h_t.raw_ptr());
+        args.push_ptr(self.grad_band_per_b_d.raw_ptr());
+        args.push_ptr(*isv_dev_ptr);
+        args.push_i32(b_size as i32);
+        args.push_ptr(self.grad_w_per_b_d.raw_ptr());
+        args.push_ptr(self.grad_b_per_b_d.raw_ptr());
+        args.push_ptr(self.grad_h_t_d.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.backward_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (HIDDEN_DIM as u32, 1, 1),
+                (BAND_OUT * std::mem::size_of::<f32>()) as u32,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_band_head_backward: {:?}", e))?;
+        }
+        Ok(())
+    }
+}
+
+// ── pinned-staging upload helper (mirrors ppo::upload) ────────────────────
+
+fn upload(stream: &Arc<CudaStream>, host: &[f32]) -> Result<CudaSlice<f32>> {
+    let n = host.len();
+    let staging = unsafe { MappedF32Buffer::new(n) }
+        .map_err(|e| anyhow::anyhow!("band_head upload staging: {e}"))?;
+    staging.write_from_slice(host);
+    let mut dst = stream
+        .alloc_zeros::<f32>(n)
+        .context("band_head upload alloc")?;
+    if n > 0 {
+        let nbytes = n * std::mem::size_of::<f32>();
+        unsafe {
+            let (dst_ptr, _g) = dst.device_ptr_mut(stream);
+            cudarc::driver::result::memcpy_dtod_async(
+                dst_ptr,
+                staging.dev_ptr,
+                nbytes,
+                stream.cu_stream(),
+            )
+            .context("band_head upload DtoD")?;
+        }
+    }
+    Ok(dst)
+}

crates/ml-alpha/src/rl/dqn.rs

@@ -113,6 +113,10 @@ const DQN_HEAD_CUBIN: &[u8] = include_bytes!(concat!(
     env!("OUT_DIR"),
     "/dqn_distributional_q.cubin"
 ));
+const PPO_LOSS_REDUCE_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/ppo_loss_reduce_b.cubin"
+));
 const DQN_TARGET_SOFT_UPDATE_CUBIN: &[u8] = include_bytes!(concat!(
     env!("OUT_DIR"),
     "/dqn_target_soft_update.cubin"
@@ -121,6 +125,14 @@ const BELLMAN_PROJ_CUBIN: &[u8] = include_bytes!(concat!(
     env!("OUT_DIR"),
     "/bellman_target_projection.cubin"
 ));
+const SATURATION_REDUCE_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_bellman_target_saturation_reduce.cubin"
+));
+const Q_DISTRIBUTION_STATS_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_q_distribution_stats.cubin"
+));
 
 /// Construction config for [`DqnHead`].
 #[derive(Clone, Debug)]
@@ -160,12 +172,22 @@ pub struct DqnHead {
     raw_stream: CUstream,
 
     _module: Arc<CudaModule>,
+    /// F4.1 reducer cubin (`ppo_loss_reduce_b.cu`) kept alive while
+    /// `loss_mean_reduce_fn` references it.
+    _loss_reduce_module: Arc<CudaModule>,
     /// Forward kernel: `dqn_distributional_q_fwd` from
     /// `cuda/dqn_distributional_q.cu`. Produces raw atom logits.
     pub fwd_fn: CudaFunction,
     /// Backward kernel: `dqn_distributional_q_bwd`. Computes categorical
     /// CE loss + `∂L/∂logits` given a pre-projected target distribution.
+    /// Writes per-batch CE to `loss_per_batch[B]` only (no atomicAdd to
+    /// any scalar — that's `mean_reduce_b_f32` below).
     pub bwd_fn: CudaFunction,
+    /// F4.1 (2026-05-31) generic `[B] → [1]` block tree-reduce mean,
+    /// shared with the PPO surrogate path (same kernel name, same
+    /// cubin). Used to produce the scalar `loss_out` diagnostic for
+    /// the LR controller; replaces the prior in-kernel atomicAdd.
+    pub loss_mean_reduce_fn: CudaFunction,
     /// Phase E.2 backward chain: `dqn_grad_w_b_h_t`. Maps the `grad_logits`
     /// output of `bwd_fn` into per-batch `grad_w` / `grad_b` scratch buffers
     /// + an OVERWRITE `grad_h_t` slot for the integrated trainer to fold
@@ -194,6 +216,24 @@ pub struct DqnHead {
     /// `bellman_target_projection`, `dqn_select_action_atoms`, and
     /// `bellman_fused_select_project` — live in the same translation unit).
     _bellman_module: Arc<CudaModule>,
+    /// B-9 (2026-06-01): cross-batch tree-reduce of per-batch
+    /// Bellman-target saturation tallies. Reads the four `[B] f32`
+    /// scratch buffers populated by either bellman variant and writes
+    /// ISV slots 726-729 (top/bot saturation rate + max/min pre-proj).
+    /// Pure observability — does not perturb training dynamics.
+    pub saturation_reduce_fn: CudaFunction,
+    _saturation_reduce_module: Arc<CudaModule>,
+
+    /// B-10 (2026-06-01) G1: Q-distribution informativeness diagnostic.
+    /// Two entry points in the same cubin:
+    /// - `rl_q_distribution_per_batch`: per-block per-action softmax over
+    ///   atoms + entropy + E_Q computation. Grid `(B, 1, 1)` × block
+    ///   `(Q_N_ATOMS, 1, 1)`. Writes 3 per-batch scratch arrays.
+    /// - `rl_q_distribution_reduce`: cross-batch tree-reduce, single-block,
+    ///   writes ISV slots 730 / 731 / 732. Pure observability.
+    pub q_distribution_per_batch_fn: CudaFunction,
+    pub q_distribution_reduce_fn: CudaFunction,
+    _q_distribution_stats_module: Arc<CudaModule>,
 
     /// Phase R5: element-wise target-net soft update kernel handle.
     /// `target[i] = (1 - τ) · target[i] + τ · current[i]` reading τ
@@ -244,6 +284,12 @@ impl DqnHead {
         let bwd_fn = module
             .load_function("dqn_distributional_q_bwd")
             .context("load dqn_distributional_q_bwd")?;
+        let loss_reduce_module = ctx
+            .load_cubin(PPO_LOSS_REDUCE_CUBIN.to_vec())
+            .context("load ppo_loss_reduce_b cubin (for mean_reduce_b_f32)")?;
+        let loss_mean_reduce_fn = loss_reduce_module
+            .load_function("mean_reduce_b_f32")
+            .context("load mean_reduce_b_f32")?;
         let grad_w_b_h_t_fn = module
             .load_function("dqn_grad_w_b_h_t")
             .context("load dqn_grad_w_b_h_t")?;
@@ -260,6 +306,25 @@ impl DqnHead {
             .load_function("bellman_fused_select_project")
             .context("load bellman_fused_select_project")?;
 
+        // B-9 (2026-06-01): C51 Bellman-target saturation reducer.
+        let saturation_reduce_module = ctx
+            .load_cubin(SATURATION_REDUCE_CUBIN.to_vec())
+            .context("load rl_bellman_target_saturation_reduce cubin")?;
+        let saturation_reduce_fn = saturation_reduce_module
+            .load_function("rl_bellman_target_saturation_reduce")
+            .context("load rl_bellman_target_saturation_reduce")?;
+
+        // B-10 (2026-06-01): Q-distribution informativeness diagnostic.
+        let q_distribution_stats_module = ctx
+            .load_cubin(Q_DISTRIBUTION_STATS_CUBIN.to_vec())
+            .context("load rl_q_distribution_stats cubin")?;
+        let q_distribution_per_batch_fn = q_distribution_stats_module
+            .load_function("rl_q_distribution_per_batch")
+            .context("load rl_q_distribution_per_batch")?;
+        let q_distribution_reduce_fn = q_distribution_stats_module
+            .load_function("rl_q_distribution_reduce")
+            .context("load rl_q_distribution_reduce")?;
+
         // Phase R5: target soft-update kernel.
         let target_soft_update_module = ctx
             .load_cubin(DQN_TARGET_SOFT_UPDATE_CUBIN.to_vec())
@@ -298,6 +363,11 @@ impl DqnHead {
         // cudaMalloc that would break CUDA Graph stream capture.
         let cublas = CudaBlas::new(Arc::clone(&stream))
             .context("DqnHead: cuBLAS init")?;
+        // Determinism foundation (spec 2026-06-02 §2.B): disable
+        // non-deterministic GEMM algorithms. Same fix as Mamba2Block,
+        // applied to the DQN distributional-Q forward + backward GEMMs.
+        let cublas = crate::cublas_determinism::apply_deterministic_math_mode(cublas)
+            .context("DqnHead: cublas determinism setup")?;
         const CUBLAS_WORKSPACE_BYTES: usize = 8 * 1024 * 1024;
         let cublas_workspace = stream
             .alloc_zeros::<u8>(CUBLAS_WORKSPACE_BYTES)
@@ -311,12 +381,6 @@ impl DqnHead {
             )
             .result()
             .map_err(|e| anyhow::anyhow!("DqnHead: cublasSetWorkspace_v2: {e:?}"))?;
-            cudarc::cublas::sys::cublasSetMathMode(
-                *cublas.handle(),
-                cudarc::cublas::sys::cublasMath_t::CUBLAS_TF32_TENSOR_OP_MATH,
-            )
-            .result()
-            .map_err(|e| anyhow::anyhow!("DqnHead: cublasSetMathMode TF32: {e:?}"))?;
         }
 
         // Bias-add and reduce-sum-axis0 kernel handles from ml-core.
@@ -330,6 +394,8 @@ impl DqnHead {
             stream,
             raw_stream,
             _module: module,
+            _loss_reduce_module: loss_reduce_module,
+            loss_mean_reduce_fn,
             fwd_fn,
             bwd_fn,
             grad_w_b_h_t_fn,
@@ -337,6 +403,11 @@ impl DqnHead {
             select_action_atoms_fn,
             bellman_fused_fn,
             _bellman_module: bellman_module,
+            saturation_reduce_fn,
+            _saturation_reduce_module: saturation_reduce_module,
+            q_distribution_per_batch_fn,
+            q_distribution_reduce_fn,
+            _q_distribution_stats_module: q_distribution_stats_module,
             target_soft_update_fn,
             _target_soft_update_module: target_soft_update_module,
             w_d,
@@ -494,10 +565,14 @@ impl DqnHead {
     }
 
     /// Phase E.2 backward chain stage 1 — categorical CE on the taken
-    /// action's atom distribution. Writes `loss_out [1]` and
-    /// `grad_logits [B × N_ACTIONS × Q_N_ATOMS]`. The `loss_out` scalar
-    /// is accumulated with atomicAdd (Phase C deferred fix — see kernel
-    /// header). `grad_logits` flows into `grad_w_b_h_t` next.
+    /// action's atom distribution. Writes `loss_per_batch [B]` and
+    /// `grad_logits [B × N_ACTIONS × Q_N_ATOMS]`.
+    ///
+    /// F4.1 (2026-05-31): the cross-batch scalar `loss_out` is now
+    /// produced by a separate `mean_reduce_b_f32` block tree-reduce
+    /// kernel that the caller invokes on `loss_per_batch`. The prior
+    /// in-kernel `atomicAdd(loss_out, ce/B)` is gone (per
+    /// `feedback_no_atomicadd`).
     #[allow(clippy::too_many_arguments)]
     pub fn backward_logits(
         &self,
@@ -505,7 +580,6 @@ impl DqnHead {
         target_dist: &CudaSlice<f32>,
         actions_taken: &CudaSlice<i32>,
         b_size: usize,
-        loss_out_dev_ptr: &u64,
         loss_per_batch: &mut CudaSlice<f32>,
         grad_logits: &mut CudaSlice<f32>,
     ) -> Result<()> {
@@ -525,7 +599,6 @@ impl DqnHead {
         args.push_ptr(target_dist.raw_ptr());
         args.push_ptr(actions_taken.raw_ptr());
         args.push_i32(b_i);
-        args.push_ptr(*loss_out_dev_ptr);
         args.push_ptr(loss_per_batch.raw_ptr());
         args.push_ptr(grad_logits.raw_ptr());
         let mut ptrs = args.build_arg_ptrs();
@@ -540,6 +613,37 @@ impl DqnHead {
         Ok(())
     }
 
+    /// F4.1 (2026-05-31) block tree-reduce `loss_per_batch [B] → scalar
+    /// mean` written to `loss_out_dev_ptr`. Replaces the prior in-kernel
+    /// `atomicAdd(loss_out, ce/B)` from `dqn_distributional_q_bwd`. Per
+    /// `feedback_no_atomicadd`: single block, 256 threads, grid-strided
+    /// over B, shared-memory tree-reduce, single-writer store.
+    pub fn reduce_loss_to_scalar(
+        &self,
+        loss_per_batch: &CudaSlice<f32>,
+        b_size: usize,
+        loss_out_dev_ptr: &u64,
+    ) -> Result<()> {
+        debug_assert_eq!(loss_per_batch.len(), b_size);
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(loss_per_batch.raw_ptr());
+        args.push_i32(b_i);
+        args.push_ptr(*loss_out_dev_ptr);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.loss_mean_reduce_fn.cu_function(),
+                (1, 1, 1),
+                (256, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("mean_reduce_b_f32 (dqn loss): {:?}", e))?;
+        }
+        Ok(())
+    }
+
     /// Phase E.2 backward chain stage 2 (LEGACY — kept for reference;
     /// production path is [`backward_gemm`]).
     ///
@@ -767,12 +871,22 @@ impl DqnHead {
         isv_dev_ptr: &u64,
         b_size: usize,
         target_dist_d: &mut CudaSlice<f32>,
+        // B-9 (2026-06-01): per-batch saturation tally scratch outputs;
+        // consumed by `launch_saturation_reduce` after this call.
+        sat_top_per_batch_d: &mut CudaSlice<f32>,
+        sat_bot_per_batch_d: &mut CudaSlice<f32>,
+        max_pre_per_batch_d: &mut CudaSlice<f32>,
+        min_pre_per_batch_d: &mut CudaSlice<f32>,
     ) -> Result<()> {
         debug_assert_eq!(target_logits_d.len(), b_size * Q_N_ATOMS);
         debug_assert_eq!(rewards_d.len(), b_size);
         debug_assert_eq!(dones_d.len(), b_size);
         debug_assert_eq!(n_step_gammas_d.len(), b_size);
         debug_assert_eq!(target_dist_d.len(), b_size * Q_N_ATOMS);
+        debug_assert_eq!(sat_top_per_batch_d.len(), b_size);
+        debug_assert_eq!(sat_bot_per_batch_d.len(), b_size);
+        debug_assert_eq!(max_pre_per_batch_d.len(), b_size);
+        debug_assert_eq!(min_pre_per_batch_d.len(), b_size);
 
         let b_i = b_size as i32;
         let mut args = RawArgs::new();
@@ -783,6 +897,10 @@ impl DqnHead {
         args.push_ptr(*isv_dev_ptr);
         args.push_i32(b_i);
         args.push_ptr(target_dist_d.raw_ptr());
+        args.push_ptr(sat_top_per_batch_d.raw_ptr());
+        args.push_ptr(sat_bot_per_batch_d.raw_ptr());
+        args.push_ptr(max_pre_per_batch_d.raw_ptr());
+        args.push_ptr(min_pre_per_batch_d.raw_ptr());
         let mut ptrs = args.build_arg_ptrs();
         unsafe {
             raw_launch(
@@ -815,6 +933,12 @@ impl DqnHead {
         isv_dev_ptr: &u64,
         b_size: usize,
         target_dist_d: &mut CudaSlice<f32>,
+        // B-9 (2026-06-01): per-batch saturation tally scratch outputs;
+        // consumed by `launch_saturation_reduce` after this call.
+        sat_top_per_batch_d: &mut CudaSlice<f32>,
+        sat_bot_per_batch_d: &mut CudaSlice<f32>,
+        max_pre_per_batch_d: &mut CudaSlice<f32>,
+        min_pre_per_batch_d: &mut CudaSlice<f32>,
     ) -> Result<()> {
         debug_assert_eq!(full_logits_d.len(), b_size * N_ACTIONS * Q_N_ATOMS);
         debug_assert_eq!(actions_d.len(), b_size);
@@ -822,6 +946,10 @@ impl DqnHead {
         debug_assert_eq!(dones_d.len(), b_size);
         debug_assert_eq!(n_step_gammas_d.len(), b_size);
         debug_assert_eq!(target_dist_d.len(), b_size * Q_N_ATOMS);
+        debug_assert_eq!(sat_top_per_batch_d.len(), b_size);
+        debug_assert_eq!(sat_bot_per_batch_d.len(), b_size);
+        debug_assert_eq!(max_pre_per_batch_d.len(), b_size);
+        debug_assert_eq!(min_pre_per_batch_d.len(), b_size);
 
         let b_i = b_size as i32;
         let mut args = RawArgs::new();
@@ -833,6 +961,10 @@ impl DqnHead {
         args.push_ptr(*isv_dev_ptr);
         args.push_i32(b_i);
         args.push_ptr(target_dist_d.raw_ptr());
+        args.push_ptr(sat_top_per_batch_d.raw_ptr());
+        args.push_ptr(sat_bot_per_batch_d.raw_ptr());
+        args.push_ptr(max_pre_per_batch_d.raw_ptr());
+        args.push_ptr(min_pre_per_batch_d.raw_ptr());
         let mut ptrs = args.build_arg_ptrs();
         unsafe {
             raw_launch(
@@ -845,6 +977,119 @@ impl DqnHead {
         Ok(())
     }
 
+    /// B-9 (2026-06-01): launch the cross-batch saturation reducer
+    /// kernel. Reads the four `[B] f32` scratch buffers populated by
+    /// either `project_bellman_target` or `fused_select_and_project_bellman`
+    /// and writes per-step rates + extremes to ISV slots 726-729. Call
+    /// this AFTER one of the two bellman variants runs in a given step.
+    #[allow(clippy::too_many_arguments)]
+    pub fn launch_saturation_reduce(
+        &self,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+        sat_top_per_batch_d: &CudaSlice<f32>,
+        sat_bot_per_batch_d: &CudaSlice<f32>,
+        max_pre_per_batch_d: &CudaSlice<f32>,
+        min_pre_per_batch_d: &CudaSlice<f32>,
+    ) -> Result<()> {
+        debug_assert_eq!(sat_top_per_batch_d.len(), b_size);
+        debug_assert_eq!(sat_bot_per_batch_d.len(), b_size);
+        debug_assert_eq!(max_pre_per_batch_d.len(), b_size);
+        debug_assert_eq!(min_pre_per_batch_d.len(), b_size);
+
+        // Power-of-2 block size, capped at 256 and bounded above by
+        // next_power_of_two(B). Identity-padded shared mem ensures
+        // threads with no work don't pollute the tree-reduce.
+        let block_dim = (b_size as u32).next_power_of_two().clamp(1, 256);
+        let smem = (4 * block_dim as usize * std::mem::size_of::<f32>()) as u32;
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(*isv_dev_ptr);
+        args.push_ptr(sat_top_per_batch_d.raw_ptr());
+        args.push_ptr(sat_bot_per_batch_d.raw_ptr());
+        args.push_ptr(max_pre_per_batch_d.raw_ptr());
+        args.push_ptr(min_pre_per_batch_d.raw_ptr());
+        args.push_i32(b_i);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.saturation_reduce_fn.cu_function(),
+                (1, 1, 1), (block_dim, 1, 1), smem,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("rl_bellman_target_saturation_reduce: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// B-10 (2026-06-01) G1: launch the Q-distribution informativeness
+    /// diagnostic — two-kernel pattern (per-batch tally + cross-batch
+    /// reduce) consuming online Q logits + the atom support buffer.
+    /// Writes ISV slots 730 / 731 / 732. Pure observability; safe to
+    /// call after each Q forward.
+    #[allow(clippy::too_many_arguments)]
+    pub fn launch_q_distribution_stats(
+        &self,
+        isv_dev_ptr: &u64,
+        q_logits_d: &CudaSlice<f32>,
+        atom_supports_d: &CudaSlice<f32>,
+        b_size: usize,
+        // Per-batch scratch (overwritten each call).
+        q_ent_per_batch_d: &mut CudaSlice<f32>,
+        q_range_per_batch_d: &mut CudaSlice<f32>,
+        q_abs_max_per_batch_d: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        debug_assert_eq!(q_logits_d.len(), b_size * N_ACTIONS * Q_N_ATOMS);
+        debug_assert_eq!(atom_supports_d.len(), Q_N_ATOMS);
+        debug_assert_eq!(q_ent_per_batch_d.len(), b_size);
+        debug_assert_eq!(q_range_per_batch_d.len(), b_size);
+        debug_assert_eq!(q_abs_max_per_batch_d.len(), b_size);
+
+        let b_i = b_size as i32;
+
+        // ── Pass 1: per-batch tally (grid (B,1,1) × block (Q_N_ATOMS,1,1)).
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(q_logits_d.raw_ptr());
+            args.push_ptr(atom_supports_d.raw_ptr());
+            args.push_i32(b_i);
+            args.push_ptr(q_ent_per_batch_d.raw_ptr());
+            args.push_ptr(q_range_per_batch_d.raw_ptr());
+            args.push_ptr(q_abs_max_per_batch_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.q_distribution_per_batch_fn.cu_function(),
+                    (b_size as u32, 1, 1), (Q_N_ATOMS as u32, 1, 1), 0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                ).map_err(|e| anyhow::anyhow!("rl_q_distribution_per_batch: {:?}", e))?;
+            }
+        }
+
+        // ── Pass 2: cross-batch tree reduce (single block).
+        {
+            let block_dim = (b_size as u32).next_power_of_two().clamp(1, 256);
+            let smem = (3 * block_dim as usize * std::mem::size_of::<f32>()) as u32;
+            let mut args = RawArgs::new();
+            args.push_ptr(*isv_dev_ptr);
+            args.push_ptr(q_ent_per_batch_d.raw_ptr());
+            args.push_ptr(q_range_per_batch_d.raw_ptr());
+            args.push_ptr(q_abs_max_per_batch_d.raw_ptr());
+            args.push_i32(b_i);
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.q_distribution_reduce_fn.cu_function(),
+                    (1, 1, 1), (block_dim, 1, 1), smem,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                ).map_err(|e| anyhow::anyhow!("rl_q_distribution_reduce: {:?}", e))?;
+            }
+        }
+        Ok(())
+    }
+
     /// Stream used to launch all kernels owned by this head. Phase E's
     /// training loop reads this when scheduling the soft-update kernel.
     pub fn stream(&self) -> &Arc<CudaStream> {

crates/ml-alpha/src/rl/dueling_q.rs

@@ -0,0 +1,530 @@
+//! Phase 4 — Independent Dueling Q head (2026-05-30).
+//!
+//! Parallel head to C51/IQN/π/value_head with ZERO shared state with
+//! downstream consumers (ensemble, distill, action selection). Trains
+//! its own V + A weights via Bellman loss on composed_Q at taken action.
+//!
+//! V output feeds PPO advantage baseline (Phase 4.3) — composed_Q is
+//! internal to this head's loss path and never consumed elsewhere.
+//!
+//! Per spec docs/superpowers/specs/2026-05-30-phase4-independent-dueling-head-design.md.
+//!
+//! ## Why a separate head (vs Phase 3 modifications to IQN)
+//!
+//! All 5 prior dueling attempts (Phase 2 v2, Phase 3.1, 3.2, 3.2c,
+//! 3.1-fix) failed because they modified existing architectures'
+//! weights or outputs in ways that perturbed downstream consumers. See
+//! the four session pearls captured in the spec's §10.
+//!
+//! Phase 4's design is **structurally encapsulated**: DuelingQHead has
+//! ITS OWN weights (w_v, b_v, w_a, b_a) and its OWN Bellman loss.
+//! Mean-zero A gradient pattern only affects DuelingQHead's training,
+//! never C51's or IQN's weights. composed_Q never feeds ensemble or
+//! distill or action selection.
+//!
+//! ## Forward
+//!
+//! ```text
+//!   V[b]            = Σ_c w_v[c] × h_t[b, c] + b_v[0]
+//!   A[b, a]         = Σ_c w_a[c, a] × h_t[b, c] + b_a[a]
+//!   composed_Q[b, a] = V[b] + A[b, a] − (1/N) Σ_a' A[b, a']
+//! ```
+//!
+//! Single fused kernel (`rl_dueling_q_forward`) computes all three.
+//!
+//! ## Constraints honoured
+//!
+//!   * `feedback_no_atomicadd` — sole-writer per output cell.
+//!   * `feedback_cpu_is_read_only` — pure device kernels.
+//!   * `feedback_no_htod_htoh_only_mapped_pinned` — weight uploads stage
+//!     through `MappedF32Buffer`.
+//!   * `feedback_no_nvrtc` — pre-compiled cubins via `build.rs`.
+//!   * `pearl_scoped_init_seed_for_reproducibility` — `new()` installs
+//!     `scoped_init_seed` before drawing Xavier samples.
+
+use std::sync::Arc;
+
+use anyhow::{Context, Result};
+use cudarc::driver::{CudaFunction, CudaModule, CudaSlice, CudaStream};
+use cudarc::driver::sys::CUstream;
+use ml_core::cuda_autograd::init::scoped_init_seed;
+use ml_core::device::MlDevice;
+use rand::{Rng, SeedableRng};
+use rand_chacha::ChaCha8Rng;
+
+use crate::heads::HIDDEN_DIM;
+use crate::pinned_mem::MappedF32Buffer;
+use crate::rl::common::N_ACTIONS;
+use crate::trainer::raw_launch::{RawArgs, raw_launch};
+
+const DUELING_Q_FORWARD_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_dueling_q_forward.cubin"
+));
+const DUELING_Q_BELLMAN_TARGET_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_dueling_q_bellman_target.cubin"
+));
+const DUELING_Q_LOSS_AND_GRAD_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_dueling_q_loss_and_grad.cubin"
+));
+const DUELING_Q_DECOMPOSE_AND_BWD_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_dueling_q_decompose_and_bwd.cubin"
+));
+/// Reuse the existing dqn_target_soft_update kernel — it's a generic
+/// element-wise `target = (1−τ) target + τ online` blend that works
+/// for any tensor size. τ read from ISV[RL_TARGET_TAU_INDEX=401].
+const DQN_TARGET_SOFT_UPDATE_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/dqn_target_soft_update.cubin"
+));
+
+/// Construction config for [`DuelingQHead`].
+#[derive(Clone, Debug)]
+pub struct DuelingQHeadConfig {
+    /// Encoder hidden dimension `h_t [B, HIDDEN_DIM]` feeding the head.
+    /// Must equal the kernel-side `HIDDEN_DIM` define (128).
+    pub hidden_dim: usize,
+    /// Random seed for Xavier init. Distinct from C51 / IQN / V_scalar
+    /// seeds so initial draws are independent.
+    pub seed: u64,
+}
+
+impl Default for DuelingQHeadConfig {
+    fn default() -> Self {
+        Self {
+            hidden_dim: HIDDEN_DIM,
+            seed: 0x4DEAD_1234,
+        }
+    }
+}
+
+/// Independent dueling Q head — V + A decomposition with scalar
+/// Bellman loss. Trains in parallel to C51 / IQN; supplies V_dq for
+/// PPO advantage baseline use (Phase 4.3).
+pub struct DuelingQHead {
+    #[allow(dead_code)]
+    cfg: DuelingQHeadConfig,
+    stream: Arc<CudaStream>,
+    raw_stream: CUstream,
+
+    // ── Kernel handles ───────────────────────────────────────────────
+    _fwd_module: Arc<CudaModule>,
+    pub forward_fn: CudaFunction,
+    _bellman_module: Arc<CudaModule>,
+    pub bellman_target_fn: CudaFunction,
+    _loss_module: Arc<CudaModule>,
+    pub loss_and_grad_fn: CudaFunction,
+    _bwd_module: Arc<CudaModule>,
+    pub decompose_and_bwd_fn: CudaFunction,
+    _soft_update_module: Arc<CudaModule>,
+    pub soft_update_fn: CudaFunction,
+
+    // ── Online weights ───────────────────────────────────────────────
+    /// V projection weights `[HIDDEN_DIM]`.
+    pub w_v_d: CudaSlice<f32>,
+    /// V projection bias `[1]`.
+    pub b_v_d: CudaSlice<f32>,
+    /// A projection weights `[HIDDEN_DIM × N_ACTIONS]`, row-major
+    /// (kernel reads `w_a[c * N_ACTIONS + a]`).
+    pub w_a_d: CudaSlice<f32>,
+    /// A projection bias `[N_ACTIONS]`.
+    pub b_a_d: CudaSlice<f32>,
+
+    // ── Target-network weights (soft-updated each step) ──────────────
+    pub w_v_target_d: CudaSlice<f32>,
+    pub b_v_target_d: CudaSlice<f32>,
+    pub w_a_target_d: CudaSlice<f32>,
+    pub b_a_target_d: CudaSlice<f32>,
+}
+
+impl DuelingQHead {
+    /// Allocate device weights, load cubins, cache kernel handles.
+    pub fn new(dev: &MlDevice, cfg: DuelingQHeadConfig) -> Result<Self> {
+        let stream: Arc<CudaStream> = dev
+            .cuda_stream()
+            .context("dueling_q_head stream")?
+            .clone();
+        let ctx = dev.cuda_context().context("dueling_q_head ctx")?;
+
+        // ── Load forward cubin ───────────────────────────────────────
+        let fwd_module = ctx
+            .load_cubin(DUELING_Q_FORWARD_CUBIN.to_vec())
+            .context("load rl_dueling_q_forward cubin")?;
+        let forward_fn = fwd_module
+            .load_function("rl_dueling_q_forward")
+            .context("load rl_dueling_q_forward")?;
+        let bellman_module = ctx
+            .load_cubin(DUELING_Q_BELLMAN_TARGET_CUBIN.to_vec())
+            .context("load rl_dueling_q_bellman_target cubin")?;
+        let bellman_target_fn = bellman_module
+            .load_function("rl_dueling_q_bellman_target_build")
+            .context("load rl_dueling_q_bellman_target_build")?;
+        let loss_module = ctx
+            .load_cubin(DUELING_Q_LOSS_AND_GRAD_CUBIN.to_vec())
+            .context("load rl_dueling_q_loss_and_grad cubin")?;
+        let loss_and_grad_fn = loss_module
+            .load_function("rl_dueling_q_loss_and_grad")
+            .context("load rl_dueling_q_loss_and_grad")?;
+        let bwd_module = ctx
+            .load_cubin(DUELING_Q_DECOMPOSE_AND_BWD_CUBIN.to_vec())
+            .context("load rl_dueling_q_decompose_and_bwd cubin")?;
+        let decompose_and_bwd_fn = bwd_module
+            .load_function("rl_dueling_q_decompose_and_weight_grad")
+            .context("load rl_dueling_q_decompose_and_weight_grad")?;
+        // Reuse dqn_target_soft_update kernel — generic element-wise blend.
+        let soft_update_module = ctx
+            .load_cubin(DQN_TARGET_SOFT_UPDATE_CUBIN.to_vec())
+            .context("load dqn_target_soft_update cubin for dueling")?;
+        let soft_update_fn = soft_update_module
+            .load_function("dqn_target_soft_update")
+            .context("load dqn_target_soft_update for dueling")?;
+
+        // ── Weight init (Xavier uniform, scaled by 0.01 like sibling heads) ──
+        // Per pearl_scoped_init_seed_for_reproducibility.
+        let _seed_guard = scoped_init_seed(cfg.seed);
+        let mut rng = ChaCha8Rng::seed_from_u64(cfg.seed);
+
+        // V projection: HIDDEN_DIM → 1
+        let v_scale = 0.01_f32 * (6.0_f32 / (cfg.hidden_dim + 1) as f32).sqrt();
+        let w_v_host: Vec<f32> = (0..cfg.hidden_dim)
+            .map(|_| rng.gen_range(-v_scale..v_scale))
+            .collect();
+        let b_v_host: Vec<f32> = vec![0.0_f32; 1];
+
+        // A projection: HIDDEN_DIM → N_ACTIONS
+        let a_scale =
+            0.01_f32 * (6.0_f32 / (cfg.hidden_dim + N_ACTIONS) as f32).sqrt();
+        let w_a_host: Vec<f32> = (0..cfg.hidden_dim * N_ACTIONS)
+            .map(|_| rng.gen_range(-a_scale..a_scale))
+            .collect();
+        let b_a_host: Vec<f32> = vec![0.0_f32; N_ACTIONS];
+
+        // Upload online weights.
+        let w_v_d = upload(&stream, &w_v_host)?;
+        let b_v_d = upload(&stream, &b_v_host)?;
+        let w_a_d = upload(&stream, &w_a_host)?;
+        let b_a_d = upload(&stream, &b_a_host)?;
+
+        // Upload target weights (identical init — soft-updated by trainer).
+        let w_v_target_d = upload(&stream, &w_v_host)?;
+        let b_v_target_d = upload(&stream, &b_v_host)?;
+        let w_a_target_d = upload(&stream, &w_a_host)?;
+        let b_a_target_d = upload(&stream, &b_a_host)?;
+
+        let raw_stream = stream.cu_stream();
+
+        Ok(Self {
+            cfg,
+            stream,
+            raw_stream,
+            _fwd_module: fwd_module,
+            forward_fn,
+            _bellman_module: bellman_module,
+            bellman_target_fn,
+            _loss_module: loss_module,
+            loss_and_grad_fn,
+            _bwd_module: bwd_module,
+            decompose_and_bwd_fn,
+            _soft_update_module: soft_update_module,
+            soft_update_fn,
+            w_v_d,
+            b_v_d,
+            w_a_d,
+            b_a_d,
+            w_v_target_d,
+            b_v_target_d,
+            w_a_target_d,
+            b_a_target_d,
+        })
+    }
+
+    /// Stream used to launch all kernels owned by this head.
+    pub fn stream(&self) -> &Arc<CudaStream> {
+        &self.stream
+    }
+
+    /// cuBLAS-free forward pass with online weights.
+    ///
+    /// Computes V[B], A[B × N_ACTIONS], and composed_Q[B × N_ACTIONS]
+    /// in a single fused kernel.
+    ///
+    /// Block layout: grid=(B, 1, 1), block=(HIDDEN_DIM, 1, 1),
+    /// shared_mem = HIDDEN_DIM × 4 bytes (for s_h cache).
+    pub fn forward(
+        &self,
+        h_t: &CudaSlice<f32>,
+        b_size: usize,
+        v_out: &mut CudaSlice<f32>,
+        a_out: &mut CudaSlice<f32>,
+        q_composed_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        self.forward_inner(
+            h_t,
+            &self.w_v_d, &self.b_v_d,
+            &self.w_a_d, &self.b_a_d,
+            b_size, v_out, a_out, q_composed_out,
+        )
+    }
+
+    /// cuBLAS-free forward pass with target-network weights.
+    pub fn forward_target(
+        &self,
+        h_t: &CudaSlice<f32>,
+        b_size: usize,
+        v_target_out: &mut CudaSlice<f32>,
+        a_target_out: &mut CudaSlice<f32>,
+        q_target_composed_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        self.forward_inner(
+            h_t,
+            &self.w_v_target_d, &self.b_v_target_d,
+            &self.w_a_target_d, &self.b_a_target_d,
+            b_size, v_target_out, a_target_out, q_target_composed_out,
+        )
+    }
+
+    /// Internal forward — parameterised over weight slices so online /
+    /// target paths share code.
+    #[allow(clippy::too_many_arguments)]
+    fn forward_inner(
+        &self,
+        h_t: &CudaSlice<f32>,
+        w_v: &CudaSlice<f32>,
+        b_v: &CudaSlice<f32>,
+        w_a: &CudaSlice<f32>,
+        b_a: &CudaSlice<f32>,
+        b_size: usize,
+        v_out: &mut CudaSlice<f32>,
+        a_out: &mut CudaSlice<f32>,
+        q_composed_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        let hd = self.cfg.hidden_dim;
+        debug_assert_eq!(h_t.len(), b_size * hd);
+        debug_assert_eq!(w_v.len(), hd);
+        debug_assert_eq!(b_v.len(), 1);
+        debug_assert_eq!(w_a.len(), hd * N_ACTIONS);
+        debug_assert_eq!(b_a.len(), N_ACTIONS);
+        debug_assert_eq!(v_out.len(), b_size);
+        debug_assert_eq!(a_out.len(), b_size * N_ACTIONS);
+        debug_assert_eq!(q_composed_out.len(), b_size * N_ACTIONS);
+
+        let b_i = b_size as i32;
+        let smem = (hd * std::mem::size_of::<f32>()) as u32;
+        let mut args = RawArgs::new();
+        args.push_ptr(h_t.raw_ptr());
+        args.push_ptr(w_v.raw_ptr());
+        args.push_ptr(b_v.raw_ptr());
+        args.push_ptr(w_a.raw_ptr());
+        args.push_ptr(b_a.raw_ptr());
+        args.push_i32(b_i);
+        args.push_ptr(v_out.raw_ptr());
+        args.push_ptr(a_out.raw_ptr());
+        args.push_ptr(q_composed_out.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.forward_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (hd as u32, 1, 1),
+                smem,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("rl_dueling_q_forward: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Build the scalar Bellman target from the target network's
+    /// composed_Q at s_{t+1}:
+    ///   a*[b]           = argmax_a' target_composed_Q[b, a']
+    ///   target_value[b] = r[b] + γ^n × (1 − done[b]) × target_composed_Q[b, a*[b]]
+    ///
+    /// Per-sample γ^n is passed (matches PER n-step convention used by
+    /// C51 / IQN target builds).
+    pub fn build_bellman_target(
+        &self,
+        target_composed_q: &CudaSlice<f32>,
+        rewards: &CudaSlice<f32>,
+        dones: &CudaSlice<f32>,
+        n_step_gammas: &CudaSlice<f32>,
+        b_size: usize,
+        target_value_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        debug_assert_eq!(target_composed_q.len(), b_size * N_ACTIONS);
+        debug_assert_eq!(rewards.len(), b_size);
+        debug_assert_eq!(dones.len(), b_size);
+        debug_assert_eq!(n_step_gammas.len(), b_size);
+        debug_assert_eq!(target_value_out.len(), b_size);
+
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(target_composed_q.raw_ptr());
+        args.push_ptr(rewards.raw_ptr());
+        args.push_ptr(dones.raw_ptr());
+        args.push_ptr(n_step_gammas.raw_ptr());
+        args.push_i32(b_i);
+        args.push_ptr(target_value_out.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.bellman_target_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (N_ACTIONS as u32, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("rl_dueling_q_bellman_target_build: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Scalar Huber loss on (target − online_composed_Q[taken]).
+    /// Emits per-batch loss and grad_composed (only taken action has
+    /// nonzero gradient — single-Q regression).
+    pub fn compute_loss_and_grad(
+        &self,
+        online_composed_q: &CudaSlice<f32>,
+        target_value: &CudaSlice<f32>,
+        actions_taken: &CudaSlice<i32>,
+        b_size: usize,
+        loss_per_batch: &mut CudaSlice<f32>,
+        grad_composed_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        debug_assert_eq!(online_composed_q.len(), b_size * N_ACTIONS);
+        debug_assert_eq!(target_value.len(), b_size);
+        debug_assert_eq!(actions_taken.len(), b_size);
+        debug_assert_eq!(loss_per_batch.len(), b_size);
+        debug_assert_eq!(grad_composed_out.len(), b_size * N_ACTIONS);
+
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(online_composed_q.raw_ptr());
+        args.push_ptr(target_value.raw_ptr());
+        args.push_ptr(actions_taken.raw_ptr());
+        args.push_i32(b_i);
+        args.push_ptr(loss_per_batch.raw_ptr());
+        args.push_ptr(grad_composed_out.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.loss_and_grad_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (N_ACTIONS as u32, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("rl_dueling_q_loss_and_grad: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Decompose grad_composed → grad_V + grad_A via mean-subtraction
+    /// Jacobian, then produce per-batch weight gradients via outer
+    /// product with h_t. Caller reduces axis 0 to final weight grads.
+    #[allow(clippy::too_many_arguments)]
+    pub fn decompose_and_backward_to_weights(
+        &self,
+        h_t: &CudaSlice<f32>,
+        grad_composed: &CudaSlice<f32>,
+        actions_taken: &CudaSlice<i32>,
+        b_size: usize,
+        grad_w_v_per_batch: &mut CudaSlice<f32>,
+        grad_b_v_per_batch: &mut CudaSlice<f32>,
+        grad_w_a_per_batch: &mut CudaSlice<f32>,
+        grad_b_a_per_batch: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        let hd = self.cfg.hidden_dim;
+        debug_assert_eq!(h_t.len(), b_size * hd);
+        debug_assert_eq!(grad_composed.len(), b_size * N_ACTIONS);
+        debug_assert_eq!(actions_taken.len(), b_size);
+        debug_assert_eq!(grad_w_v_per_batch.len(), b_size * hd);
+        debug_assert_eq!(grad_b_v_per_batch.len(), b_size);
+        debug_assert_eq!(grad_w_a_per_batch.len(), b_size * hd * N_ACTIONS);
+        debug_assert_eq!(grad_b_a_per_batch.len(), b_size * N_ACTIONS);
+
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(h_t.raw_ptr());
+        args.push_ptr(grad_composed.raw_ptr());
+        args.push_ptr(actions_taken.raw_ptr());
+        args.push_i32(b_i);
+        args.push_ptr(grad_w_v_per_batch.raw_ptr());
+        args.push_ptr(grad_b_v_per_batch.raw_ptr());
+        args.push_ptr(grad_w_a_per_batch.raw_ptr());
+        args.push_ptr(grad_b_a_per_batch.raw_ptr());
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.decompose_and_bwd_fn.cu_function(),
+                (b_size as u32, 1, 1),
+                (hd as u32, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            ).map_err(|e| anyhow::anyhow!("rl_dueling_q_decompose_and_bwd: {:?}", e))?;
+        }
+        Ok(())
+    }
+
+    /// Soft-update target network: `target = (1−τ) × target + τ × online`
+    /// element-wise on all four weight tensors. τ read from
+    /// `ISV[RL_TARGET_TAU_INDEX=401]` — same controller as Q's target.
+    /// Should be called once per training step AFTER the Adam steps so
+    /// the update reflects the latest online weights.
+    pub fn soft_update_target(&mut self, isv_dev_ptr: &u64) -> Result<()> {
+        let launch_blend = |n: usize, online: u64, target: u64, label: &str| -> Result<()> {
+            let n_i = n as i32;
+            let mut args = RawArgs::new();
+            args.push_ptr(online);
+            args.push_ptr(target);
+            args.push_ptr(*isv_dev_ptr);
+            args.push_i32(n_i);
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.soft_update_fn.cu_function(),
+                    (((n as u32) + 255) / 256, 1, 1),
+                    (256, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                ).map_err(|e| anyhow::anyhow!("dueling soft_update_target ({label}): {e:?}"))?;
+            }
+            Ok(())
+        };
+        launch_blend(self.w_v_d.len(), self.w_v_d.raw_ptr(), self.w_v_target_d.raw_ptr(), "w_v")?;
+        launch_blend(self.b_v_d.len(), self.b_v_d.raw_ptr(), self.b_v_target_d.raw_ptr(), "b_v")?;
+        launch_blend(self.w_a_d.len(), self.w_a_d.raw_ptr(), self.w_a_target_d.raw_ptr(), "w_a")?;
+        launch_blend(self.b_a_d.len(), self.b_a_d.raw_ptr(), self.b_a_target_d.raw_ptr(), "b_a")?;
+        Ok(())
+    }
+}
+
+// ── pinned-staging upload helper (mirrors aux_heads.rs::upload) ──
+
+fn upload(stream: &Arc<CudaStream>, host: &[f32]) -> Result<CudaSlice<f32>> {
+    let n = host.len();
+    let staging = unsafe { MappedF32Buffer::new(n) }
+        .map_err(|e| anyhow::anyhow!("dueling_q upload staging: {e}"))?;
+    staging.write_from_slice(host);
+    let dst = stream
+        .alloc_zeros::<f32>(n)
+        .context("dueling_q upload alloc")?;
+    if n > 0 {
+        let nbytes = n * std::mem::size_of::<f32>();
+        unsafe {
+            let dst_ptr = dst.raw_ptr();
+            crate::trainer::raw_launch::raw_memcpy_dtod_async(
+                dst_ptr,
+                staging.dev_ptr,
+                nbytes,
+                stream.cu_stream(),
+            )
+            .map_err(|e| anyhow::anyhow!("dueling_q upload DtoD: {:?}", e))?;
+        }
+    }
+    Ok(dst)
+}

crates/ml-alpha/src/rl/gpu_replay.rs

@@ -47,7 +47,7 @@ impl GpuReplayBuffer {
             nstep_write_idx_d: stream.alloc_zeros(b_size).context("gpu_replay nstep_write_idx")?,
             nstep_count_d: stream.alloc_zeros(b_size).context("gpu_replay nstep_count")?,
             flush_flags_d: stream.alloc_zeros(b_size).context("gpu_replay flush_flags")?,
-            write_offsets_d: stream.alloc_zeros(b_size + 1).context("gpu_replay write_offsets")?,
+            write_offsets_d: stream.alloc_zeros(b_size + 2).context("gpu_replay write_offsets")?,
             sample_indices_d: stream.alloc_zeros(b_size).context("gpu_replay sample_indices")?,
             sample_prng_d: stream.alloc_zeros(b_size).context("gpu_replay sample_prng")?,
         })

crates/ml-alpha/src/rl/iqn.rs

@@ -212,8 +212,17 @@ pub struct IqnHead {
 
     // ── Forward kernels (split pipeline) ─────────────────────────────
     _fwd_module: Arc<CudaModule>,
-    /// Stage 1: tau sampling + cosine basis computation.
+    /// Stage 1: tau sampling + cosine basis computation. READ-ONLY on
+    /// `prng_state` per determinism Phase 2.6 fix (2026-06-02).
     pub tau_cos_features_fn: CudaFunction,
+    /// Determinism Phase 2.6 sibling: advance the per-batch xorshift32
+    /// PRNG state by 8 steps. Run AFTER `tau_cos_features_fn` so the
+    /// sampling sees a stable read across all (tau_idx) blocks. The
+    /// kernel-launch ordering on a single stream is the grid-wide
+    /// barrier (replaces the racy "tau_idx==0 block writes prng_state
+    /// at end of monolithic kernel" pattern that produced run-dependent
+    /// τ values for tau_idx > 0 pre-fix).
+    pub advance_prng_state_fn: CudaFunction,
     /// Stage 3: bias-add → ReLU → hadamard product with h_t.
     pub relu_hadamard_fn: CudaFunction,
     /// Stage 5: bias addition to cuBLAS output projection result.
@@ -260,6 +269,11 @@ impl IqnHead {
         // ── cuBLAS handle + pre-allocated workspace ──────────────────
         let cublas = CudaBlas::new(Arc::clone(&stream))
             .map_err(|e| anyhow::anyhow!("IqnHead: cuBLAS init: {e}"))?;
+        // Determinism foundation (spec 2026-06-02 §2.B): disable
+        // non-deterministic GEMM algorithms. Same fix as Mamba2Block,
+        // applied to the IQN τ-conditioned GEMMs.
+        let cublas = crate::cublas_determinism::apply_deterministic_math_mode(cublas)
+            .map_err(|e| anyhow::anyhow!("IqnHead: cublas determinism setup: {e}"))?;
         let cublas_workspace = stream
             .alloc_zeros::<u8>(CUBLAS_WORKSPACE_BYTES)
             .map_err(|e| anyhow::anyhow!("IqnHead: cuBLAS workspace: {e}"))?;
@@ -281,6 +295,11 @@ impl IqnHead {
         let tau_cos_features_fn = fwd_module
             .load_function("rl_iqn_tau_cos_features")
             .context("load rl_iqn_tau_cos_features")?;
+        // Determinism Phase 2.6 (2026-06-02): companion advance kernel
+        // for the now read-only `rl_iqn_tau_cos_features`. Same cubin.
+        let advance_prng_state_fn = fwd_module
+            .load_function("rl_iqn_advance_prng_state")
+            .context("load rl_iqn_advance_prng_state")?;
         let relu_hadamard_fn = fwd_module
             .load_function("rl_iqn_relu_hadamard")
             .context("load rl_iqn_relu_hadamard")?;
@@ -360,6 +379,7 @@ impl IqnHead {
             _cublas_workspace: cublas_workspace,
             _fwd_module: fwd_module,
             tau_cos_features_fn,
+            advance_prng_state_fn,
             relu_hadamard_fn,
             bias_add_q_fn,
             expected_q_fn,
@@ -479,6 +499,34 @@ impl IqnHead {
             }
         }
 
+        // ── Stage 1b: advance PRNG state (determinism Phase 2.6 fix).
+        // The previous monolithic `rl_iqn_tau_cos_features` had a read-
+        // write race: all N_TAU blocks per batch read `prng_state[batch]`
+        // at kernel head, and the (tau_idx==0) block wrote back the
+        // advanced state at kernel tail — with NO inter-block barrier.
+        // Run on the same stream → kernel-launch ordering acts as a
+        // grid-wide barrier between the (now read-only) sampling and
+        // the (single-thread-per-batch) advance. No race possible.
+        // Per `feedback_no_atomicadd.md` + canonical Phase-2 rebuild rule.
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(prng_state.raw_ptr());
+            args.push_i32(b_size as i32);
+            let mut ptrs = args.build_arg_ptrs();
+            let block_x = 256u32.min(b_size as u32).max(1);
+            let grid_x = ((b_size as u32) + block_x - 1) / block_x;
+            unsafe {
+                raw_launch(
+                    self.advance_prng_state_fn.cu_function(),
+                    (grid_x, 1, 1),
+                    (block_x, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                ).map_err(|e| anyhow::anyhow!("rl_iqn_advance_prng_state: {:?}", e))?;
+            }
+        }
+
         // ── Stage 2: cuBLAS SGEMM — embed_out = cos_features @ W_embed ──
         {
             let w_ptr = w_embed.raw_ptr();

crates/ml-alpha/src/rl/mod.rs

@@ -15,14 +15,17 @@
 //! ISV slot constants only. Subsequent phases (B-H) wire the heads, controllers,
 //! training loop, Argo plumbing, and backtest gate.
 
+pub mod band_head;
 pub mod common;
 pub mod dqn;
+pub mod dueling_q;
 pub mod gpu_hindsight;
 pub mod gpu_replay;
 pub mod frd;
 pub mod iqn;
 pub mod isv_slots;
 pub mod loss_balance;
+pub mod multi_head_policy;
 pub mod noisy;
 pub mod ppo;
 pub mod reward;

crates/ml-alpha/src/rl/multi_head_policy.rs

@@ -0,0 +1,921 @@
+//! K-head policy with regime-gated routing.
+//!
+//! Spec: docs/superpowers/specs/2026-06-02-multi-head-policy-with-r-multiple.md
+//!       ADDENDUM 2026-06-03 §R.3-R.6
+//! Plan: docs/superpowers/plans/2026-06-03-multi-head-policy-implementation.md (Phase 2A-A)
+//! Pearl: pearl_local_smoke_noise_floor_and_regime_concentration
+//!
+//! ## Forward
+//!
+//! ```text
+//!   gate_logits = W_gate @ regime_h + b_gate           // gating head (bypass VSN)
+//!   gate_probs  = softmax_K(gate_logits)
+//!   pi_logits_k = W_heads_k @ h_t + b_heads_k          // K policy heads
+//!   pi_probs_k  = softmax_A(pi_logits_k)
+//!   pi_probs    = Σ_k gate_probs[k] · pi_probs_k       // mixture
+//!   pi_logits   = log(pi_probs + 1e-12)
+//! ```
+//!
+//! Backward (Phase 2A-B) — standard MoE Jacobian distributes the Q-distill
+//! gradient on `pi_logits` to (a) per-head `pi_logits_k` and (b)
+//! `gate_logits`. Phase 2A-A only ships the forward path; backward kernels
+//! arrive in the next phase.
+//!
+//! ## Why a parallel-channel gating head
+//!
+//! Empirical regime-attenuation finding: at the Phase 0 baseline, the
+//! single policy head is regime-conditional on `popart_envelope`
+//! (TVD(Q1, Q4 action dist) = 0.169) but NOT on `session_pnl_variance_ema`
+//! (TVD = 0.015), despite vol context living at `regime[3]` in the encoder
+//! input. The asymmetry maps to VSN's softmax-over-40 gating constraint
+//! structurally limiting any single encoder-input feature to ~1/40 of the
+//! attention budget. The gating head reads `step_regime_d[b][0..6]`
+//! DIRECTLY — bypassing VSN/Mamba2 — so the per-head mixture can route by
+//! vol regime without competing against 39 other channels.
+//!
+//! ## Constraints honoured
+//!
+//!   * `feedback_no_atomicadd` — sole-writer per output cell across both kernels.
+//!   * `feedback_cpu_is_read_only` — pure device kernels.
+//!   * `feedback_no_htod_htoh_only_mapped_pinned` — weight uploads stage
+//!     through `MappedF32Buffer` via the local `upload` helper (mirrors
+//!     `rl/ppo.rs::upload` and `rl/dueling_q.rs::upload`).
+//!   * `feedback_no_nvrtc` — pre-compiled cubins via `build.rs`.
+//!   * `pearl_scoped_init_seed_for_reproducibility` — `new()` installs
+//!     `scoped_init_seed` before drawing any deterministic random samples.
+//!   * `feedback_single_source_of_truth_no_duplicates` — `MAX_K_HEADS=8`
+//!     mirrors the `#define` in `multi_head_policy_forward.cu` /
+//!     `multi_head_policy_gate_forward.cu`; the constant lives here for
+//!     the runtime bounds check.
+
+use std::sync::Arc;
+
+use anyhow::{Context, Result};
+use cudarc::driver::sys::CUstream;
+use cudarc::driver::{CudaFunction, CudaModule, CudaSlice, CudaStream};
+use ml_core::cuda_autograd::init::scoped_init_seed;
+use ml_core::device::MlDevice;
+
+use crate::cfc::snap_features::REGIME_DIM;
+use crate::heads::HIDDEN_DIM;
+use crate::pinned_mem::MappedF32Buffer;
+use crate::rl::common::N_ACTIONS;
+use crate::trainer::raw_launch::{raw_launch, raw_memcpy_dtod_async, RawArgs};
+
+const FORWARD_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/multi_head_policy_forward.cubin"));
+const GATE_FORWARD_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/multi_head_policy_gate_forward.cubin"
+));
+const BACKWARD_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/multi_head_policy_backward.cubin"
+));
+const AUX_PRIOR_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/multi_head_policy_aux_prior.cubin"
+));
+const REDUCE_AXIS0_CUBIN: &[u8] =
+    include_bytes!(concat!(env!("OUT_DIR"), "/reduce_axis0.cubin"));
+const AGGREGATE_DIAG_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/multi_head_policy_aggregate_diag.cubin"
+));
+
+/// Compile-time upper bound on K — mirrors the `#define MAX_K_HEADS 8` in
+/// both kernel sources. The runtime K (from `RL_POLICY_NUM_HEADS_INDEX`)
+/// must satisfy `1 ≤ K ≤ MAX_K_HEADS`.
+pub const MAX_K_HEADS: usize = 8;
+
+/// Construction config for [`MultiHeadPolicy`].
+#[derive(Clone, Debug)]
+pub struct MultiHeadPolicyConfig {
+    /// Number of policy heads. Bootstrap value comes from
+    /// `RL_POLICY_NUM_HEADS_INDEX = 761`; this struct accepts the value
+    /// directly so callers don't need an ISV read at allocation time.
+    pub k: usize,
+    /// Batch size — number of independent (h_t, regime_h) rows processed
+    /// per forward call. Matches `n_batch` everywhere else in the trainer.
+    pub b_size: usize,
+    /// Random seed for the gating-head weight init. Per
+    /// `pearl_scoped_init_seed_for_reproducibility`, this guards a
+    /// `scoped_init_seed` block so initial draws are deterministic.
+    pub seed: u64,
+}
+
+impl Default for MultiHeadPolicyConfig {
+    fn default() -> Self {
+        Self {
+            k: 3,
+            b_size: 0,
+            seed: 0xC0_1D_C0_DE,
+        }
+    }
+}
+
+/// K-head policy with a parallel-channel regime gating head.
+///
+/// All device buffers are allocated in `new()`. Forward runs the gate
+/// kernel then the mixture kernel on the same stream — `gate_probs_d`
+/// hand-off is single-stream so no extra sync is needed.
+pub struct MultiHeadPolicy {
+    pub cfg: MultiHeadPolicyConfig,
+    stream: Arc<CudaStream>,
+    raw_stream: CUstream,
+
+    // ── Kernel handles ────────────────────────────────────────────────
+    _forward_module: Arc<CudaModule>,
+    forward_fn: CudaFunction,
+    _gate_forward_module: Arc<CudaModule>,
+    gate_forward_fn: CudaFunction,
+    _backward_module: Arc<CudaModule>,
+    backward_pi_fn: CudaFunction,
+    backward_gate_fn: CudaFunction,
+    _aux_prior_module: Arc<CudaModule>,
+    aux_prior_fn: CudaFunction,
+    _reduce_axis0_module: Arc<CudaModule>,
+    reduce_axis0_fn: CudaFunction,
+    _aggregate_diag_module: Arc<CudaModule>,
+    aggregate_diag_fn: CudaFunction,
+
+    // ── Policy-head weights ([K × N_ACTIONS × HIDDEN_DIM] row-major) ──
+    /// `W_heads[k, a, j]` — row-major flat over `(k, a, j)`.
+    pub w_heads_d: CudaSlice<f32>,
+    /// `b_heads[k, a]` — per-head per-action bias. Initial per-head action
+    /// priors live here (see [`MultiHeadPolicy::new`]).
+    pub b_heads_d: CudaSlice<f32>,
+
+    // ── Gating-head weights ([K × REGIME_DIM=6]) ──────────────────────
+    pub w_gate_d: CudaSlice<f32>,
+    pub b_gate_d: CudaSlice<f32>,
+
+    // ── Forward output buffers (persisted for backward) ───────────────
+    /// Pre-softmax gating logits `[B × K]`.
+    pub gate_logits_d: CudaSlice<f32>,
+    /// Post-softmax gating probabilities `[B × K]`. Sums to 1 per batch row.
+    pub gate_probs_d: CudaSlice<f32>,
+    /// Per-head pre-softmax logits `[B × K × N_ACTIONS]`.
+    pub pi_logits_k_d: CudaSlice<f32>,
+    /// Per-head post-softmax probabilities `[B × K × N_ACTIONS]`. Sums to
+    /// 1 per (batch, head) row.
+    pub pi_probs_k_d: CudaSlice<f32>,
+
+    // ── Per-head action priors ([K × N_ACTIONS]) ──────────────────────
+    /// Distribution priors for the aux KL term. Per-head priors mirror
+    /// the init bias of [`MultiHeadPolicy::new`] so the aux loss does not
+    /// fight the asymmetry-break initialization (`pearl_bootstrap_must_respect_clamp_range`
+    /// applied to priors). Heads 3..K (if K > 3) carry uniform priors.
+    pub priors_d: CudaSlice<f32>,
+
+    // ── Backward output buffers ───────────────────────────────────────
+    /// `[B × K × N_ACTIONS]` — gradient on per-head logits. Populated by
+    /// the backward pi kernel (mixture + softmax-Jacobian); aux prior
+    /// kernel adds its β-weighted contribution. Available for diagnostics
+    /// or further chain-rule routing in Phase 2A-C.
+    pub grad_pi_logits_k_d: CudaSlice<f32>,
+    /// `[B × K]` — gradient on the gating distribution (before softmax-Jacobian),
+    /// computed by the pi backward kernel and consumed by the gate backward kernel.
+    pub grad_gate_probs_d: CudaSlice<f32>,
+    /// `[B × K]` — gradient on the pre-softmax gate logits (for diagnostics).
+    pub grad_gate_logits_d: CudaSlice<f32>,
+    /// `[B × HIDDEN_DIM]` — head's contribution to the encoder grad. The
+    /// `backward()` method writes (OVERWRITE) into this scratch; the
+    /// caller folds it into the encoder's `grad_h_t` via
+    /// `grad_h_accumulate_scaled`.
+    pub grad_h_t_scratch_d: CudaSlice<f32>,
+    /// `[B × REGIME_DIM]` — gradient on the regime input. Computed for
+    /// completeness but NOT routed upstream in Phase 2A-B (regime is
+    /// loader-precomputed).
+    pub grad_regime_h_d: CudaSlice<f32>,
+
+    // ── Per-batch grad scratch (for reduce_axis0) ─────────────────────
+    grad_w_heads_pb_d: CudaSlice<f32>,
+    grad_b_heads_pb_d: CudaSlice<f32>,
+    grad_w_gate_pb_d: CudaSlice<f32>,
+    grad_b_gate_pb_d: CudaSlice<f32>,
+
+    // ── Reduced grad buffers (post `reduce_axis0`) ────────────────────
+    /// Reduced grad on `W_heads`, ready for an Adam step in Phase 2A-C.
+    pub grad_w_heads_d: CudaSlice<f32>,
+    /// Reduced grad on `b_heads`.
+    pub grad_b_heads_d: CudaSlice<f32>,
+    /// Reduced grad on `W_gate`.
+    pub grad_w_gate_d: CudaSlice<f32>,
+    /// Reduced grad on `b_gate`.
+    pub grad_b_gate_d: CudaSlice<f32>,
+}
+
+impl MultiHeadPolicy {
+    /// Allocate weights + forward buffers, load cubins, install per-head
+    /// init biases for asymmetry-break specialization.
+    ///
+    /// Per-head action priors (verified against
+    /// [`crate::rl::common::Action`] enum values):
+    ///
+    /// | head | role             | bias slot | action      |
+    /// |------|------------------|-----------|-------------|
+    /// | 0    | SHORT / risk-off | 0         | ShortLarge  |
+    /// | 1    | LONG  / risk-on  | 5, 6      | LongSmall, LongLarge |
+    /// | 2    | HOLD  / stable   | 2         | Hold        |
+    ///
+    /// Heads 3-7 (if K > 3) carry zero bias — pure data-driven specialization.
+    pub fn new(dev: &MlDevice, cfg: MultiHeadPolicyConfig) -> Result<Self> {
+        assert!(
+            cfg.k >= 1 && cfg.k <= MAX_K_HEADS,
+            "MultiHeadPolicy: K must be in [1, {MAX_K_HEADS}]; got {}",
+            cfg.k
+        );
+        assert!(
+            cfg.b_size > 0,
+            "MultiHeadPolicy: b_size must be > 0; got {}",
+            cfg.b_size
+        );
+
+        let stream: Arc<CudaStream> = dev
+            .cuda_stream()
+            .context("multi_head_policy stream")?
+            .clone();
+        let ctx = dev
+            .cuda_context()
+            .context("multi_head_policy ctx")?;
+
+        // ── Load cubins (repo convention: const &[u8] + load_cubin) ───
+        let forward_module = ctx
+            .load_cubin(FORWARD_CUBIN.to_vec())
+            .context("load multi_head_policy_forward cubin")?;
+        let forward_fn = forward_module
+            .load_function("multi_head_policy_forward")
+            .context("load multi_head_policy_forward fn")?;
+        let gate_forward_module = ctx
+            .load_cubin(GATE_FORWARD_CUBIN.to_vec())
+            .context("load multi_head_policy_gate_forward cubin")?;
+        let gate_forward_fn = gate_forward_module
+            .load_function("multi_head_policy_gate_forward")
+            .context("load multi_head_policy_gate_forward fn")?;
+        let backward_module = ctx
+            .load_cubin(BACKWARD_CUBIN.to_vec())
+            .context("load multi_head_policy_backward cubin")?;
+        let backward_pi_fn = backward_module
+            .load_function("multi_head_policy_backward_pi")
+            .context("load multi_head_policy_backward_pi fn")?;
+        let backward_gate_fn = backward_module
+            .load_function("multi_head_policy_backward_gate")
+            .context("load multi_head_policy_backward_gate fn")?;
+        let aux_prior_module = ctx
+            .load_cubin(AUX_PRIOR_CUBIN.to_vec())
+            .context("load multi_head_policy_aux_prior cubin")?;
+        let aux_prior_fn = aux_prior_module
+            .load_function("multi_head_policy_aux_prior")
+            .context("load multi_head_policy_aux_prior fn")?;
+        let reduce_axis0_module = ctx
+            .load_cubin(REDUCE_AXIS0_CUBIN.to_vec())
+            .context("load reduce_axis0 cubin (multi_head_policy)")?;
+        let reduce_axis0_fn = reduce_axis0_module
+            .load_function("reduce_axis0")
+            .context("load reduce_axis0 fn (multi_head_policy)")?;
+        let aggregate_diag_module = ctx
+            .load_cubin(AGGREGATE_DIAG_CUBIN.to_vec())
+            .context("load multi_head_policy_aggregate_diag cubin")?;
+        let aggregate_diag_fn = aggregate_diag_module
+            .load_function("multi_head_policy_aggregate_diag")
+            .context("load multi_head_policy_aggregate_diag fn")?;
+
+        // Install determinism guard before drawing any random samples
+        // (pearl_scoped_init_seed_for_reproducibility).
+        let _seed_guard = scoped_init_seed(cfg.seed);
+
+        // ── Policy-head weights ───────────────────────────────────────
+        // Zero-init the linear projections; per-head action priors live
+        // entirely on the bias vector so the asymmetry-break is precise
+        // and survives Xavier draws (which would average to zero anyway
+        // at random init but introduce per-step noise).
+        let w_heads_d = stream
+            .alloc_zeros::<f32>(cfg.k * N_ACTIONS * HIDDEN_DIM)
+            .context("alloc w_heads_d")?;
+
+        // Per-head init biases — verified against Action enum
+        // (crates/ml-alpha/src/rl/common.rs:56-70):
+        //   0=ShortLarge   5=LongSmall   6=LongLarge   2=Hold
+        let mut b_heads_init = vec![0.0_f32; cfg.k * N_ACTIONS];
+        if cfg.k >= 1 {
+            // Head 0 — SHORT-bias / risk-off
+            b_heads_init[0 * N_ACTIONS + 0] += 0.5;
+        }
+        if cfg.k >= 2 {
+            // Head 1 — LONG-bias / risk-on
+            b_heads_init[1 * N_ACTIONS + 5] += 0.5;
+            b_heads_init[1 * N_ACTIONS + 6] += 0.5;
+        }
+        if cfg.k >= 3 {
+            // Head 2 — HOLD / stable (Phase 0 dominant action)
+            b_heads_init[2 * N_ACTIONS + 2] += 0.5;
+        }
+        // Phase 3D-A (2026-06-03): structural Hold-action elevation across
+        // ALL heads. The 4:1 open-vs-hold action prior (4 opens: 0,1,5,6 vs
+        // 1 hold: 2) biases uniform-init sampling toward trading
+        // (P(open)=36%, P(hold)=9%). Adding +log(4)≈1.386 to every head's
+        // Hold bias counter-balances this at init while preserving the
+        // per-head specialization additions above (Head 0 still gets +0.5
+        // on ShortLarge PLUS +1.386 on Hold; Head 2 gets +0.5 + +1.386 =
+        // +1.886 on Hold). Mirror the change in `build_priors` below so
+        // the aux-KL prior does not fight the new initialization.
+        //
+        // Literature: Cao et al. 2026 (arXiv:2603.29086) action-space-prior
+        // adjustment; one of three concurrent Phase 3D interventions
+        // (B: quadratic impact cost; C: PPO surrogate restoration).
+        let hold_bias: f32 = (4.0_f32).ln();
+        for head in 0..cfg.k {
+            b_heads_init[head * N_ACTIONS + 2] += hold_bias;
+        }
+        let b_heads_d = upload(&stream, &b_heads_init)
+            .context("upload b_heads init")?;
+
+        // ── Gating-head weights ───────────────────────────────────────
+        // Deterministic Xavier-style init scaled to keep initial gate
+        // logits near 0 (softmax ≈ uniform over K — no head wins by
+        // accident at step 0). The sin(i × 0.123) ramp is reproducible
+        // across hosts without needing an RNG; combined with
+        // scoped_init_seed it survives the determinism contract.
+        let gate_scale = (1.0_f32 / REGIME_DIM as f32).sqrt() * 0.1_f32;
+        let w_gate_init: Vec<f32> = (0..cfg.k * REGIME_DIM)
+            .map(|i| (i as f32 * 0.123_f32).sin() * gate_scale)
+            .collect();
+        let w_gate_d = upload(&stream, &w_gate_init)
+            .context("upload w_gate init")?;
+        let b_gate_d = stream
+            .alloc_zeros::<f32>(cfg.k)
+            .context("alloc b_gate_d")?;
+
+        // ── Forward output buffers (persisted for backward) ───────────
+        let gate_logits_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k)
+            .context("alloc gate_logits_d")?;
+        let gate_probs_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k)
+            .context("alloc gate_probs_d")?;
+        let pi_logits_k_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * N_ACTIONS)
+            .context("alloc pi_logits_k_d")?;
+        let pi_probs_k_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * N_ACTIONS)
+            .context("alloc pi_probs_k_d")?;
+
+        // ── Per-head action priors ────────────────────────────────────
+        // Mirror the per-head init bias so the aux KL term does not fight
+        // the asymmetry-break initialization. Heads 3..K (if K > 3) get a
+        // uniform prior.
+        let priors_host = build_priors(cfg.k);
+        let priors_d = upload(&stream, &priors_host)
+            .context("upload aux KL priors")?;
+
+        // ── Backward output buffers ───────────────────────────────────
+        let grad_pi_logits_k_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * N_ACTIONS)
+            .context("alloc grad_pi_logits_k_d")?;
+        let grad_gate_probs_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k)
+            .context("alloc grad_gate_probs_d")?;
+        let grad_gate_logits_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k)
+            .context("alloc grad_gate_logits_d")?;
+        let grad_h_t_scratch_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * HIDDEN_DIM)
+            .context("alloc grad_h_t_scratch_d")?;
+        let grad_regime_h_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * REGIME_DIM)
+            .context("alloc grad_regime_h_d")?;
+
+        // ── Per-batch grad scratch (for reduce_axis0) ────────────────
+        let grad_w_heads_pb_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * N_ACTIONS * HIDDEN_DIM)
+            .context("alloc grad_w_heads_pb_d")?;
+        let grad_b_heads_pb_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * N_ACTIONS)
+            .context("alloc grad_b_heads_pb_d")?;
+        let grad_w_gate_pb_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k * REGIME_DIM)
+            .context("alloc grad_w_gate_pb_d")?;
+        let grad_b_gate_pb_d = stream
+            .alloc_zeros::<f32>(cfg.b_size * cfg.k)
+            .context("alloc grad_b_gate_pb_d")?;
+
+        // ── Reduced grad buffers ──────────────────────────────────────
+        let grad_w_heads_d = stream
+            .alloc_zeros::<f32>(cfg.k * N_ACTIONS * HIDDEN_DIM)
+            .context("alloc grad_w_heads_d")?;
+        let grad_b_heads_d = stream
+            .alloc_zeros::<f32>(cfg.k * N_ACTIONS)
+            .context("alloc grad_b_heads_d")?;
+        let grad_w_gate_d = stream
+            .alloc_zeros::<f32>(cfg.k * REGIME_DIM)
+            .context("alloc grad_w_gate_d")?;
+        let grad_b_gate_d = stream
+            .alloc_zeros::<f32>(cfg.k)
+            .context("alloc grad_b_gate_d")?;
+
+        let raw_stream = stream.cu_stream();
+
+        Ok(Self {
+            cfg,
+            stream,
+            raw_stream,
+            _forward_module: forward_module,
+            forward_fn,
+            _gate_forward_module: gate_forward_module,
+            gate_forward_fn,
+            _backward_module: backward_module,
+            backward_pi_fn,
+            backward_gate_fn,
+            _aux_prior_module: aux_prior_module,
+            aux_prior_fn,
+            _reduce_axis0_module: reduce_axis0_module,
+            reduce_axis0_fn,
+            _aggregate_diag_module: aggregate_diag_module,
+            aggregate_diag_fn,
+            w_heads_d,
+            b_heads_d,
+            w_gate_d,
+            b_gate_d,
+            gate_logits_d,
+            gate_probs_d,
+            pi_logits_k_d,
+            pi_probs_k_d,
+            priors_d,
+            grad_pi_logits_k_d,
+            grad_gate_probs_d,
+            grad_gate_logits_d,
+            grad_h_t_scratch_d,
+            grad_regime_h_d,
+            grad_w_heads_pb_d,
+            grad_b_heads_pb_d,
+            grad_w_gate_pb_d,
+            grad_b_gate_pb_d,
+            grad_w_heads_d,
+            grad_b_heads_d,
+            grad_w_gate_d,
+            grad_b_gate_d,
+        })
+    }
+
+    /// Stream owned by this head. All kernels are launched on this stream
+    /// so the gate→mixture hand-off needs no extra synchronization.
+    pub fn stream(&self) -> &Arc<CudaStream> {
+        &self.stream
+    }
+
+    /// Number of policy heads.
+    pub fn k(&self) -> usize {
+        self.cfg.k
+    }
+
+    /// Batch size this head was allocated for.
+    pub fn b_size(&self) -> usize {
+        self.cfg.b_size
+    }
+
+    /// Forward pass: gating head then mixture kernel.
+    ///
+    ///   1. `multi_head_policy_gate_forward` reads `regime_h [B × 6]`
+    ///      and writes `gate_logits_d [B × K]` + `gate_probs_d [B × K]`.
+    ///   2. `multi_head_policy_forward` reads `h_t [B × HIDDEN_DIM]` and
+    ///      `gate_probs_d`, writes `pi_logits_k_d` + `pi_probs_k_d`
+    ///      (cached for backward) and `pi_logits_out [B × N_ACTIONS]`
+    ///      (the mixture log-probs consumed by downstream Q-distill).
+    ///
+    /// Both kernels are deterministic by construction (single block per
+    /// batch, fixed summation order). No atomicAdd.
+    pub fn forward(
+        &self,
+        h_t: &CudaSlice<f32>,
+        regime_h: &CudaSlice<f32>,
+        pi_logits_out: &mut CudaSlice<f32>,
+    ) -> Result<()> {
+        let b = self.cfg.b_size;
+        let k = self.cfg.k;
+        debug_assert_eq!(h_t.len(), b * HIDDEN_DIM, "h_t shape mismatch");
+        debug_assert_eq!(
+            regime_h.len(),
+            b * REGIME_DIM,
+            "regime_h shape mismatch"
+        );
+        debug_assert_eq!(
+            pi_logits_out.len(),
+            b * N_ACTIONS,
+            "pi_logits_out shape mismatch"
+        );
+
+        let b_i = b as i32;
+        let k_i = k as i32;
+
+        // ── Step 1: gating head ───────────────────────────────────────
+        // Grid = (B), Block = (K). Reads regime_h DIRECTLY (no VSN).
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(regime_h.raw_ptr());
+            args.push_ptr(self.w_gate_d.raw_ptr());
+            args.push_ptr(self.b_gate_d.raw_ptr());
+            args.push_ptr(self.gate_logits_d.raw_ptr());
+            args.push_ptr(self.gate_probs_d.raw_ptr());
+            args.push_i32(b_i);
+            args.push_i32(k_i);
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.gate_forward_fn.cu_function(),
+                    (b as u32, 1, 1),
+                    (k as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("multi_head_policy_gate_forward: {e:?}"))?;
+            }
+        }
+
+        // ── Step 2: per-head policy + mixture ─────────────────────────
+        // Grid = (B), Block = (N_ACTIONS). Reads h_t + gate_probs_d.
+        // Single-stream hand-off, no extra sync needed.
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(h_t.raw_ptr());
+            args.push_ptr(self.w_heads_d.raw_ptr());
+            args.push_ptr(self.b_heads_d.raw_ptr());
+            args.push_ptr(self.gate_probs_d.raw_ptr());
+            args.push_ptr(self.pi_logits_k_d.raw_ptr());
+            args.push_ptr(self.pi_probs_k_d.raw_ptr());
+            args.push_ptr(pi_logits_out.raw_ptr());
+            args.push_i32(b_i);
+            args.push_i32(k_i);
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.forward_fn.cu_function(),
+                    (b as u32, 1, 1),
+                    (N_ACTIONS as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("multi_head_policy_forward: {e:?}"))?;
+            }
+        }
+
+        Ok(())
+    }
+
+    /// Launch the device-aggregated diagnostics kernel (Phase 2A-D).
+    ///
+    /// Reduces the forward outputs `gate_probs_d [B × K]` and
+    /// `pi_probs_k_d [B × K × N_ACTIONS]` over the batch axis and writes
+    /// 25 scalars into the ISV bus:
+    ///
+    ///   * `gate_probs_mean[k]`       — slots 765..773 (K-stride 8)
+    ///   * `gate_argmax_mass[k]`      — slots 773..781 (K-stride 8)
+    ///   * `gate_entropy_mean`        — slot 781 (scalar)
+    ///   * `per_head_entropy_mean[k]` — slots 782..790 (K-stride 8)
+    ///
+    /// Tail entries past runtime K are written 0.0 so the diag JSON
+    /// schema is constant for K ∈ [1, 8] (`MAX_K_HEADS` mirror).
+    ///
+    /// Call **after** `forward()` and **before** the next step's forward
+    /// — the kernel reads forward outputs that are overwritten each step.
+    /// Launches on the struct's stream so the producer→consumer ordering
+    /// is single-stream (no extra sync needed).
+    ///
+    /// Per `feedback_no_atomicadd`: tree-reduce in shared memory; each
+    /// ISV destination has a single writer thread.
+    pub fn emit_diag_stats(&self, isv_dev_ptr: u64) -> Result<()> {
+        let b = self.cfg.b_size;
+        let k = self.cfg.k;
+        let b_i = b as i32;
+        let k_i = k as i32;
+
+        // Launch shape: Grid = (MAX_K_HEADS + 1, 1, 1), Block = (128, 1, 1).
+        // Matches the role assignment in `multi_head_policy_aggregate_diag.cu`.
+        const BLOCK_THREADS: u32 = 128;
+        let grid_x: u32 = (MAX_K_HEADS as u32) + 1;
+
+        let mut args = RawArgs::new();
+        args.push_ptr(self.gate_probs_d.raw_ptr());
+        args.push_ptr(self.pi_probs_k_d.raw_ptr());
+        args.push_ptr(isv_dev_ptr);
+        args.push_i32(b_i);
+        args.push_i32(k_i);
+        args.push_i32(crate::rl::isv_slots::RL_POLICY_GATE_PROBS_MEAN_BASE_INDEX as i32);
+        args.push_i32(crate::rl::isv_slots::RL_POLICY_GATE_ARGMAX_MASS_BASE_INDEX as i32);
+        args.push_i32(crate::rl::isv_slots::RL_POLICY_GATE_ENTROPY_MEAN_INDEX as i32);
+        args.push_i32(crate::rl::isv_slots::RL_POLICY_PER_HEAD_ENTROPY_MEAN_BASE_INDEX as i32);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.aggregate_diag_fn.cu_function(),
+                (grid_x, 1, 1),
+                (BLOCK_THREADS, 1, 1),
+                0,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("multi_head_policy_aggregate_diag: {e:?}"))?;
+        }
+
+        Ok(())
+    }
+
+    /// Backward pass through the mixture, per-head softmax, and gating softmax.
+    ///
+    /// Inputs:
+    ///   * `grad_pi_logits_d [B × N_ACTIONS]` — incoming gradient on the
+    ///     mixture log-probs (forward output). In Phase 2A-C this will be
+    ///     produced by `rl_q_pi_distill_grad`.
+    ///   * `h_t_d [B × HIDDEN_DIM]` — same encoder hidden state passed to
+    ///     forward (re-passed because backward needs it for the weight grad).
+    ///   * `regime_h_d [B × REGIME_DIM]` — same regime input passed to
+    ///     forward.
+    ///   * `isv_dev_ptr` — raw device pointer to the trainer's ISV bus.
+    ///     The aux prior kernel reads slot `RL_POLICY_AUX_PRIOR_BETA_INDEX`.
+    ///
+    /// Pipeline (single stream, sequential ordering):
+    ///   1. `multi_head_policy_backward_pi` — distributes incoming grad
+    ///      through mixture + per-head softmax. Writes
+    ///      `grad_pi_logits_k_d`, `grad_gate_probs_d`, per-batch
+    ///      `grad_W_heads_pb` + `grad_b_heads_pb`, and
+    ///      `grad_h_t_scratch_d` (OVERWRITE).
+    ///   2. `multi_head_policy_aux_prior` — adds β-weighted KL-prior grad
+    ///      to `grad_pi_logits_k_d`. (β=0 → no-op.) NOTE: Phase 2A-B does
+    ///      not back-propagate the aux contribution into weight grads; the
+    ///      aux term shapes the per-head LOGIT distribution only. This
+    ///      matches §R.4 of the spec (the aux is a regularizer on the head
+    ///      output distribution, not a chain through the full network).
+    ///      Phase 2A-C will wire the aux contribution into `grad_W_heads` if
+    ///      empirically needed.
+    ///   3. `multi_head_policy_backward_gate` — distributes
+    ///      `grad_gate_probs_d` through the gating softmax. Writes
+    ///      `grad_gate_logits_d`, per-batch `grad_W_gate_pb` +
+    ///      `grad_b_gate_pb`, and `grad_regime_h_d` (computed; not routed).
+    ///   4. `reduce_axis0` over B for all four per-batch grad scratches
+    ///      yields the reduced `grad_W_heads_d`, `grad_b_heads_d`,
+    ///      `grad_W_gate_d`, `grad_b_gate_d` ready for an Adam step.
+    ///
+    /// `grad_h_t_scratch_d` is the head's contribution to the encoder grad
+    /// and is exposed for the caller to fold via `grad_h_accumulate_scaled`
+    /// (Phase 2A-C wires this into the trainer's encoder backward chain).
+    pub fn backward(
+        &mut self,
+        grad_pi_logits_d: &CudaSlice<f32>,
+        h_t_d: &CudaSlice<f32>,
+        regime_h_d: &CudaSlice<f32>,
+        isv_dev_ptr: u64,
+    ) -> Result<()> {
+        let b = self.cfg.b_size;
+        let k = self.cfg.k;
+        debug_assert_eq!(
+            grad_pi_logits_d.len(),
+            b * N_ACTIONS,
+            "grad_pi_logits shape mismatch"
+        );
+        debug_assert_eq!(h_t_d.len(), b * HIDDEN_DIM, "h_t shape mismatch");
+        debug_assert_eq!(
+            regime_h_d.len(),
+            b * REGIME_DIM,
+            "regime_h shape mismatch"
+        );
+
+        let b_i = b as i32;
+        let k_i = k as i32;
+
+        // ── Step 1: backward through mixture + per-head softmax ───────
+        // Grid = (B), Block = (HIDDEN_DIM). Each thread covers one
+        // hidden-dim index across all (k, a).
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(grad_pi_logits_d.raw_ptr());
+            args.push_ptr(h_t_d.raw_ptr());
+            args.push_ptr(self.w_heads_d.raw_ptr());
+            args.push_ptr(self.gate_probs_d.raw_ptr());
+            args.push_ptr(self.pi_probs_k_d.raw_ptr());
+            args.push_i32(b_i);
+            args.push_i32(k_i);
+            args.push_ptr(self.grad_pi_logits_k_d.raw_ptr());
+            args.push_ptr(self.grad_gate_probs_d.raw_ptr());
+            args.push_ptr(self.grad_w_heads_pb_d.raw_ptr());
+            args.push_ptr(self.grad_b_heads_pb_d.raw_ptr());
+            args.push_ptr(self.grad_h_t_scratch_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.backward_pi_fn.cu_function(),
+                    (b as u32, 1, 1),
+                    (HIDDEN_DIM as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("multi_head_policy_backward_pi: {e:?}"))?;
+            }
+        }
+
+        // ── Step 2: aux KL prior (additive into grad_pi_logits_k_d) ──
+        // Grid = (B, K), Block = (N_ACTIONS). Runs AFTER step 1 so the
+        // base softmax-Jacobian grad is already in place when we add the
+        // β-weighted aux contribution. β=0 → kernel short-circuits.
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(self.pi_probs_k_d.raw_ptr());
+            args.push_ptr(self.priors_d.raw_ptr());
+            args.push_ptr(isv_dev_ptr);
+            args.push_i32(b_i);
+            args.push_i32(k_i);
+            args.push_ptr(self.grad_pi_logits_k_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.aux_prior_fn.cu_function(),
+                    (b as u32, k as u32, 1),
+                    (N_ACTIONS as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("multi_head_policy_aux_prior: {e:?}"))?;
+            }
+        }
+
+        // ── Step 3: backward through gating softmax ───────────────────
+        // Grid = (B), Block = (MAX_K_HEADS=8) — covers both K and REGIME_DIM
+        // (both ≤ MAX_K_HEADS). Single-stream hand-off from pi backward.
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(self.grad_gate_probs_d.raw_ptr());
+            args.push_ptr(self.gate_probs_d.raw_ptr());
+            args.push_ptr(regime_h_d.raw_ptr());
+            args.push_ptr(self.w_gate_d.raw_ptr());
+            args.push_i32(b_i);
+            args.push_i32(k_i);
+            args.push_ptr(self.grad_gate_logits_d.raw_ptr());
+            args.push_ptr(self.grad_w_gate_pb_d.raw_ptr());
+            args.push_ptr(self.grad_b_gate_pb_d.raw_ptr());
+            args.push_ptr(self.grad_regime_h_d.raw_ptr());
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.backward_gate_fn.cu_function(),
+                    (b as u32, 1, 1),
+                    (MAX_K_HEADS as u32, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("multi_head_policy_backward_gate: {e:?}"))?;
+            }
+        }
+
+        // ── Step 4: reduce per-batch grads across B → final shapes ────
+        // Standard foxhunt reduce_axis0 pattern (see trainer integrated.rs).
+        reduce_axis0_local(
+            &self.stream,
+            &self.reduce_axis0_fn,
+            &self.grad_w_heads_pb_d,
+            b,
+            k * N_ACTIONS * HIDDEN_DIM,
+            &mut self.grad_w_heads_d,
+        )?;
+        reduce_axis0_local(
+            &self.stream,
+            &self.reduce_axis0_fn,
+            &self.grad_b_heads_pb_d,
+            b,
+            k * N_ACTIONS,
+            &mut self.grad_b_heads_d,
+        )?;
+        reduce_axis0_local(
+            &self.stream,
+            &self.reduce_axis0_fn,
+            &self.grad_w_gate_pb_d,
+            b,
+            k * REGIME_DIM,
+            &mut self.grad_w_gate_d,
+        )?;
+        reduce_axis0_local(
+            &self.stream,
+            &self.reduce_axis0_fn,
+            &self.grad_b_gate_pb_d,
+            b,
+            k,
+            &mut self.grad_b_gate_d,
+        )?;
+
+        Ok(())
+    }
+}
+
+// ── pinned-staging upload helper ─────────────────────────────────────
+//
+// Mirrors `rl/ppo.rs::upload` and `rl/dueling_q.rs::upload`. Per
+// `feedback_no_htod_htoh_only_mapped_pinned`: weight init data stages
+// through a `MappedF32Buffer` (page-locked + mapped) then a DtoD copy
+// into the persistent device slice. No raw `memcpy_htod`.
+fn upload(stream: &Arc<CudaStream>, host: &[f32]) -> Result<CudaSlice<f32>> {
+    let n = host.len();
+    let staging = unsafe { MappedF32Buffer::new(n) }
+        .map_err(|e| anyhow::anyhow!("multi_head_policy upload staging: {e}"))?;
+    staging.write_from_slice(host);
+    let dst = stream
+        .alloc_zeros::<f32>(n)
+        .context("multi_head_policy upload alloc")?;
+    if n > 0 {
+        let nbytes = n * std::mem::size_of::<f32>();
+        unsafe {
+            let dst_ptr = dst.raw_ptr();
+            raw_memcpy_dtod_async(dst_ptr, staging.dev_ptr, nbytes, stream.cu_stream())
+                .map_err(|e| anyhow::anyhow!("multi_head_policy upload DtoD: {e:?}"))?;
+        }
+    }
+    Ok(dst)
+}
+
+// ── Per-head action priors ──────────────────────────────────────────
+//
+// Mirror the per-head init biases from `MultiHeadPolicy::new` so the aux
+// KL term does not fight the asymmetry-break initialization.
+//
+// Post-Phase 3D-A (2026-06-03): every head now also receives +log(4) on
+// action 2 (Hold) to counter the 4:1 open-vs-hold action prior. The
+// priors must mirror that elevation or the aux-KL gradient would push
+// the policy back toward the (over-opening) uniform distribution.
+//
+//   prior[0] = softmax([+0.5, 0, +log(4), 0, 0, 0, 0, 0, 0, 0, 0])  (SHORT + HOLD lift)
+//   prior[1] = softmax([0, 0, +log(4), 0, 0, +0.5, +0.5, 0, 0, 0, 0])  (LONG + HOLD lift)
+//   prior[2] = softmax([0, 0, +0.5+log(4), 0, 0, 0, 0, 0, 0, 0, 0])  (HOLD bias + lift)
+//   prior[k≥3] = softmax([0, 0, +log(4), 0, 0, 0, 0, 0, 0, 0, 0])  (HOLD lift only)
+//
+// Returns a `K × N_ACTIONS` flat row-major host buffer.
+fn build_priors(k: usize) -> Vec<f32> {
+    let mut priors = vec![0.0_f32; k * N_ACTIONS];
+    let hold_bias: f32 = (4.0_f32).ln();
+    for head in 0..k {
+        // Logit ramp matching the init bias (zero for unbiased actions).
+        let mut logit = vec![0.0_f32; N_ACTIONS];
+        match head {
+            0 => logit[0] = 0.5,
+            1 => {
+                logit[5] = 0.5;
+                logit[6] = 0.5;
+            }
+            2 => logit[2] = 0.5,
+            _ => {} // uniform — all zeros → Hold-lift below is the only bias
+        }
+        // Phase 3D-A: HOLD-action elevation (all heads).
+        logit[2] += hold_bias;
+        // softmax — single-batch row, no overflow risk at this scale.
+        let mx = logit.iter().cloned().fold(f32::NEG_INFINITY, f32::max);
+        let mut s = 0.0_f32;
+        let mut exps = [0.0_f32; N_ACTIONS];
+        for (i, &l) in logit.iter().enumerate() {
+            let e = (l - mx).exp();
+            exps[i] = e;
+            s += e;
+        }
+        for (i, e) in exps.iter().enumerate() {
+            priors[head * N_ACTIONS + i] = e / s;
+        }
+    }
+    priors
+}
+
+// ── reduce_axis0 launcher (local copy of the trainer's helper) ─────
+//
+// Sums `[B × N]` per-batch grad scratch to `[N]` final form. Single
+// block per output-tile column, 32×8 threads (REDAX0_TILE_J × REDAX0_TILE_B
+// matching `cuda/reduce_axis0.cu`). No host-side helper import to keep
+// `MultiHeadPolicy` independent of `trainer::integrated` internals.
+fn reduce_axis0_local(
+    stream: &Arc<CudaStream>,
+    reduce_fn: &CudaFunction,
+    per_batch: &CudaSlice<f32>,
+    b_size: usize,
+    n_tail: usize,
+    out: &mut CudaSlice<f32>,
+) -> Result<()> {
+    debug_assert_eq!(per_batch.len(), b_size * n_tail);
+    debug_assert_eq!(out.len(), n_tail);
+    let grid_x = (n_tail as u32).div_ceil(32);
+    let mut args = RawArgs::new();
+    args.push_ptr(per_batch.raw_ptr());
+    args.push_i32(b_size as i32);
+    args.push_i32(n_tail as i32);
+    args.push_ptr(out.raw_ptr());
+    let mut ptrs = args.build_arg_ptrs();
+    unsafe {
+        raw_launch(
+            reduce_fn.cu_function(),
+            (grid_x, 1, 1),
+            (32, 8, 1),
+            0,
+            stream.cu_stream(),
+            &mut ptrs[..args.len()],
+        )
+        .map_err(|e| anyhow::anyhow!("reduce_axis0 (multi_head_policy): {e:?}"))?;
+    }
+    Ok(())
+}

crates/ml-alpha/src/rl/outcome_head.rs

@@ -55,7 +55,17 @@ impl OutcomeHead {
     /// and sentinel -1 labels.
     ///
     /// `b_size` is the maximum batch size for pre-allocated activation buffers.
-    pub fn new(b_size: usize, stream: Arc<CudaStream>) -> Result<Self> {
+    /// `seed` installs a `scoped_init_seed` guard around the W draw so two
+    /// processes seeded with the same value produce bit-equal initial weights
+    /// (per `pearl_scoped_init_seed_for_reproducibility`). Diagnosed in
+    /// determinism Phase 2.6 (2026-06-02): without this guard, the
+    /// `near_zero_xavier` call fell back to the time+thread-id RNG path —
+    /// outcome_w differed by ~0.003 between same-seed runs at step 0, then
+    /// stayed dormant until the first `done` event activated a non-sentinel
+    /// label (step 2 in mid-smoke), at which point grad_h_t_outcome flowed
+    /// the divergent weights into the encoder gradient. Other heads (dqn,
+    /// iqn, policy, value, dueling_q) already installed this guard.
+    pub fn new(b_size: usize, seed: u64, stream: Arc<CudaStream>) -> Result<Self> {
         if b_size == 0 {
             return Err(anyhow!("OutcomeHead: b_size must be > 0"));
         }
@@ -116,9 +126,17 @@ impl OutcomeHead {
             .map_err(|e| anyhow!("OutcomeHead: fused kernel resolve: {e}"))?;
 
         // Xavier init W at 0.01x scale: near-zero for near-uniform softmax at init.
-        let w_d = ml_core::cuda_autograd::init::near_zero_xavier(
-            HIDDEN_DIM, K_CLASSES, &stream,
-        ).map_err(|e| anyhow!("OutcomeHead: W init: {e}"))?;
+        // Determinism Phase 2.6 fix (2026-06-02): install scoped_init_seed
+        // around the W draw so same-seed processes produce bit-equal weights.
+        // The `_seed_guard` drops at end of this block, restoring whatever
+        // (or no) RNG state was active before. Per
+        // `pearl_scoped_init_seed_for_reproducibility`.
+        let w_d = {
+            let _seed_guard = ml_core::cuda_autograd::init::scoped_init_seed(seed);
+            ml_core::cuda_autograd::init::near_zero_xavier(
+                HIDDEN_DIM, K_CLASSES, &stream,
+            ).map_err(|e| anyhow!("OutcomeHead: W init: {e}"))?
+        };
 
         // Bias: zeros.
         let b_d = ml_core::cuda_autograd::init::zeros(K_CLASSES, &stream)
@@ -455,7 +473,7 @@ mod tests {
             None => return,
         };
         assert!(
-            OutcomeHead::new(0, stream).is_err(),
+            OutcomeHead::new(0, 42, stream).is_err(),
             "b_size=0 must be rejected"
         );
     }
@@ -466,7 +484,7 @@ mod tests {
             Some(s) => s,
             None => return,
         };
-        let head = OutcomeHead::new(64, stream);
+        let head = OutcomeHead::new(64, 42, stream);
         assert!(head.is_ok(), "OutcomeHead should construct: {:?}", head.err());
     }
 }

crates/ml-alpha/src/rl/ppo.rs

@@ -45,13 +45,21 @@ use rand_chacha::ChaCha8Rng;
 
 use crate::heads::HIDDEN_DIM;
 use crate::pinned_mem::MappedF32Buffer;
-use crate::rl::common::N_ACTIONS;
+use crate::rl::common::{Action, N_ACTIONS};
 use crate::trainer::raw_launch::{RawArgs, raw_launch};
 
 const PPO_SURR_CUBIN: &[u8] = include_bytes!(concat!(
     env!("OUT_DIR"),
     "/ppo_clipped_surrogate.cubin"
 ));
+const PPO_DIAGNOSTIC_REDUCE_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/rl_ppo_diagnostic_stats_reduce.cubin"
+));
+const PPO_LOSS_REDUCE_CUBIN: &[u8] = include_bytes!(concat!(
+    env!("OUT_DIR"),
+    "/ppo_loss_reduce_b.cubin"
+));
 const V_HEAD_CUBIN: &[u8] =
     include_bytes!(concat!(env!("OUT_DIR"), "/v_head_fwd_bwd.cubin"));
 
@@ -83,10 +91,17 @@ pub struct PolicyHead {
     raw_stream: CUstream,
 
     _module: Arc<CudaModule>,
+    /// F4.1 reducer cubin module — kept alive while `loss_reduce_fn`
+    /// references it.
+    _loss_reduce_module: Arc<CudaModule>,
     /// Forward kernel: `ppo_clipped_surrogate_fwd`. Consumes new-policy
-    /// logits, old log π, advantages, returns + ISV[402,403] and writes
-    /// per-batch log π / entropy plus accumulated loss scalars.
+    /// logits, old log π, advantages + ISV[402,403,440] and writes
+    /// per-batch log π / entropy + per-batch loss slots (no atomicAdd).
     pub surrogate_fwd_fn: CudaFunction,
+    /// F4.1 reducer kernel: `ppo_loss_reduce_b`. Takes the per-batch
+    /// `[B]` loss buffers written by `surrogate_fwd_fn` and produces
+    /// the two scalar diagnostics the trainer / LR controller reads.
+    pub loss_reduce_fn: CudaFunction,
     /// Backward kernel: `ppo_clipped_surrogate_bwd`. Computes per-logit
     /// gradient with the clip-mask applied (zero outside the clip band).
     pub surrogate_bwd_fn: CudaFunction,
@@ -107,6 +122,15 @@ pub struct PolicyHead {
     /// caller's responsibility via `reduce_axis0`.
     pub grad_w_b_h_t_fn: CudaFunction,
 
+    /// B-10 (2026-06-01) G3+G4: cross-batch tree-reduce of per-batch
+    /// PPO advantage + ratio + surrogate observability scratches written
+    /// by `surrogate_fwd_fn`. Reads slot 612 (`var_pre_norm`) to compute
+    /// `σ_used = sqrt(var)` for the |A_unnorm| reconstruction. Writes
+    /// ISV slots 735-742. Pure observability — does not feed any
+    /// controller, does not perturb training dynamics.
+    pub ppo_diagnostic_reduce_fn: CudaFunction,
+    _ppo_diagnostic_reduce_module: Arc<CudaModule>,
+
     /// Online weights `[N_ACTIONS, HIDDEN_DIM]`, row-major. Each row is
     /// one action's projection vector.
     pub w_d: CudaSlice<f32>,
@@ -134,6 +158,12 @@ impl PolicyHead {
         let surrogate_bwd_fn = module
             .load_function("ppo_clipped_surrogate_bwd")
             .context("load ppo_clipped_surrogate_bwd")?;
+        let loss_reduce_module = ctx
+            .load_cubin(PPO_LOSS_REDUCE_CUBIN.to_vec())
+            .context("load ppo_loss_reduce_b cubin")?;
+        let loss_reduce_fn = loss_reduce_module
+            .load_function("ppo_loss_reduce_b")
+            .context("load ppo_loss_reduce_b")?;
         let policy_linear_fwd_fn = module
             .load_function("ppo_policy_logits_fwd")
             .context("load ppo_policy_logits_fwd")?;
@@ -141,6 +171,14 @@ impl PolicyHead {
             .load_function("ppo_grad_w_b_h_t")
             .context("load ppo_grad_w_b_h_t")?;
 
+        // B-10 (2026-06-01): PPO diagnostic stats reducer.
+        let ppo_diagnostic_reduce_module = ctx
+            .load_cubin(PPO_DIAGNOSTIC_REDUCE_CUBIN.to_vec())
+            .context("load rl_ppo_diagnostic_stats_reduce cubin")?;
+        let ppo_diagnostic_reduce_fn = ppo_diagnostic_reduce_module
+            .load_function("rl_ppo_diagnostic_stats_reduce")
+            .context("load rl_ppo_diagnostic_stats_reduce")?;
+
         // Per pearl_scoped_init_seed_for_reproducibility: install the
         // scoped seed guard BEFORE drawing any Xavier samples.
         let _seed_guard = scoped_init_seed(cfg.seed);
@@ -152,7 +190,24 @@ impl PolicyHead {
         let w_host: Vec<f32> = (0..n_out * n_in)
             .map(|_| rng.gen_range(-scale..scale))
             .collect();
-        let b_host: Vec<f32> = vec![0.0_f32; n_out];
+        // Phase 3D-A (2026-06-03): Hold-action logit bias.
+        //
+        // The 11-action grid (see `crate::rl::common::Action`) has 4 open
+        // variants (0=ShortLarge, 1=ShortSmall, 5=LongSmall, 6=LongLarge)
+        // vs 1 hold (2=Hold). At uniform random init the structural prior
+        // is P(open)=4/11≈36% and P(hold)=1/11≈9% BEFORE any learning —
+        // a 4:1 bias toward opening. Counter-balance by adding +log(4)≈1.386
+        // to the Hold action bias so the asymmetry-break probabilities
+        // are P(hold)=4/(4+10)≈28.6% and P(any specific open)=1/14≈7.1%,
+        // restoring near-uniform open-vs-hold mass at init.
+        //
+        // Per Cao et al. 2026 + Goodhart-Skalse 2024 literature on
+        // action-space prior bias, this is one of three concurrent fixes
+        // (B: quadratic impact cost; C: PPO surrogate restoration) for
+        // foxhunt's structural overtrading pathology.
+        let hold_bias: f32 = (4.0_f32).ln();
+        let mut b_host: Vec<f32> = vec![0.0_f32; n_out];
+        b_host[Action::Hold as usize] += hold_bias;
 
         let w_d = upload(&stream, &w_host)?;
         let b_d = upload(&stream, &b_host)?;
@@ -163,15 +218,67 @@ impl PolicyHead {
             stream,
             raw_stream,
             _module: module,
+            _loss_reduce_module: loss_reduce_module,
             surrogate_fwd_fn,
+            loss_reduce_fn,
             surrogate_bwd_fn,
             policy_linear_fwd_fn,
             grad_w_b_h_t_fn,
+            ppo_diagnostic_reduce_fn,
+            _ppo_diagnostic_reduce_module: ppo_diagnostic_reduce_module,
             w_d,
             b_d,
         })
     }
 
+    /// B-10 (2026-06-01) G3+G4: launch the cross-batch reducer over the
+    /// 4 per-batch observability scratches written by `surrogate_forward`.
+    /// Reads slot 612 (`var_pre_norm`) inside the kernel to compute
+    /// `σ_used = sqrt(var)` for the |A_unnorm| reconstruction. Writes
+    /// ISV slots 735-742. Pure observability; safe to call after any
+    /// `surrogate_forward` in the step.
+    #[allow(clippy::too_many_arguments)]
+    pub fn launch_ppo_diagnostic_stats_reduce(
+        &self,
+        isv_dev_ptr: &u64,
+        b_size: usize,
+        a_norm_pb: &CudaSlice<f32>,
+        ratio_dev_pb: &CudaSlice<f32>,
+        ratio_clipped_pb: &CudaSlice<f32>,
+        surrogate_pb: &CudaSlice<f32>,
+    ) -> Result<()> {
+        debug_assert_eq!(a_norm_pb.len(), b_size);
+        debug_assert_eq!(ratio_dev_pb.len(), b_size);
+        debug_assert_eq!(ratio_clipped_pb.len(), b_size);
+        debug_assert_eq!(surrogate_pb.len(), b_size);
+
+        // Power-of-2 block size, capped at 256; identity-padded shared
+        // mem ensures threads with no work don't pollute the reduce.
+        let block_dim = (b_size as u32).next_power_of_two().clamp(1, 256);
+        // 5 reductions × block_dim floats (matches kernel layout in
+        // rl_ppo_diagnostic_stats_reduce.cu).
+        let smem = (5 * block_dim as usize * std::mem::size_of::<f32>()) as u32;
+        let b_i = b_size as i32;
+        let mut args = RawArgs::new();
+        args.push_ptr(*isv_dev_ptr);
+        args.push_ptr(a_norm_pb.raw_ptr());
+        args.push_ptr(ratio_dev_pb.raw_ptr());
+        args.push_ptr(ratio_clipped_pb.raw_ptr());
+        args.push_ptr(surrogate_pb.raw_ptr());
+        args.push_i32(b_i);
+        let mut ptrs = args.build_arg_ptrs();
+        unsafe {
+            raw_launch(
+                self.ppo_diagnostic_reduce_fn.cu_function(),
+                (1, 1, 1), (block_dim, 1, 1), smem,
+                self.raw_stream,
+                &mut ptrs[..args.len()],
+            )
+            .map_err(|e| anyhow::anyhow!("rl_ppo_diagnostic_stats_reduce: {:?}", e))?;
+        }
+        Ok(())
+    }
+
     /// Stream used to launch all kernels owned by this head. Phase E's
     /// training loop reads this when scheduling the surrogate / Adam
     /// kernels.
@@ -222,9 +329,18 @@ impl PolicyHead {
     }
 
     /// Phase E.2 surrogate forward — runs `ppo_clipped_surrogate_fwd`
-    /// using the trainer-provided logits + advantages. Reads ε from
-    /// `isv[RL_PPO_CLIP_INDEX]` and entropy coef from
-    /// `isv[RL_ENTROPY_COEF_INDEX]`.
+    /// then `ppo_loss_reduce_b` to produce the two scalar loss
+    /// diagnostics. Reads ε from `isv[RL_PPO_CLIP_INDEX]` and entropy
+    /// coef from `isv[RL_ENTROPY_COEF_INDEX]`.
+    ///
+    /// F4.1 (2026-05-31) — replaces the prior atomicAdd-into-scalar
+    /// pattern. The fwd kernel writes per-batch loss values to the
+    /// `[B]` scratch buffers; the reducer then computes the batch mean
+    /// and stores it (single-writer, no accumulation) into the scalar
+    /// mapped-pinned slots the trainer reads. This eliminates the
+    /// step-count staleness bug that inflated `loss.pi` linearly in
+    /// step count (local 1k × ~9 ≈ 9080; cluster 20k × ~1200 ≈ 24M).
+    /// Per `feedback_no_atomicadd`.
     ///
     /// The V-loss path (formerly bundled with this surrogate forward) was
     /// canonicalised into the dedicated V-head kernels per
@@ -232,6 +348,7 @@ impl PolicyHead {
     /// longer accepts `returns` / `v_pred` / `loss_v` (greenfield removal
     /// 2026-05-22).
     #[allow(clippy::too_many_arguments)]
+    #[allow(clippy::too_many_arguments)]
     pub fn surrogate_forward(
         &self,
         logits: &CudaSlice<f32>,
@@ -242,8 +359,18 @@ impl PolicyHead {
         b_size: usize,
         pi_log_prob: &mut CudaSlice<f32>,
         entropy: &mut CudaSlice<f32>,
-        loss_pi_dev_ptr: &u64,
-        loss_entropy_dev_ptr: &u64,
+        loss_pi_per_b: &mut CudaSlice<f32>,
+        loss_entropy_per_b: &mut CudaSlice<f32>,
+        loss_pi_scalar_dev_ptr: &u64,
+        loss_entropy_scalar_dev_ptr: &u64,
+        // B-10 (2026-06-01) G3+G4: per-batch observability scratches
+        // consumed downstream by `launch_ppo_diagnostic_stats_reduce`.
+        // Pure observability — kernel writes alongside existing
+        // loss_pi_per_b without perturbing the loss reduction path.
+        ppo_a_norm_pb: &mut CudaSlice<f32>,
+        ppo_ratio_dev_pb: &mut CudaSlice<f32>,
+        ppo_ratio_clipped_pb: &mut CudaSlice<f32>,
+        ppo_surrogate_pb: &mut CudaSlice<f32>,
     ) -> Result<()> {
         debug_assert_eq!(logits.len(), b_size * N_ACTIONS);
         debug_assert_eq!(log_pi_old.len(), b_size);
@@ -251,6 +378,12 @@ impl PolicyHead {
         debug_assert_eq!(advantages.len(), b_size);
         debug_assert_eq!(pi_log_prob.len(), b_size);
         debug_assert_eq!(entropy.len(), b_size);
+        debug_assert_eq!(loss_pi_per_b.len(), b_size);
+        debug_assert_eq!(loss_entropy_per_b.len(), b_size);
+        debug_assert_eq!(ppo_a_norm_pb.len(), b_size);
+        debug_assert_eq!(ppo_ratio_dev_pb.len(), b_size);
+        debug_assert_eq!(ppo_ratio_clipped_pb.len(), b_size);
+        debug_assert_eq!(ppo_surrogate_pb.len(), b_size);
 
         let b_i = b_size as i32;
         {
@@ -263,8 +396,13 @@ impl PolicyHead {
             args.push_i32(b_i);
             args.push_ptr(pi_log_prob.raw_ptr());
             args.push_ptr(entropy.raw_ptr());
-            args.push_ptr(*loss_pi_dev_ptr);
-            args.push_ptr(*loss_entropy_dev_ptr);
+            args.push_ptr(loss_pi_per_b.raw_ptr());
+            args.push_ptr(loss_entropy_per_b.raw_ptr());
+            // B-10 G3+G4 scratch outputs.
+            args.push_ptr(ppo_a_norm_pb.raw_ptr());
+            args.push_ptr(ppo_ratio_dev_pb.raw_ptr());
+            args.push_ptr(ppo_ratio_clipped_pb.raw_ptr());
+            args.push_ptr(ppo_surrogate_pb.raw_ptr());
             let mut ptrs = args.build_arg_ptrs();
             unsafe {
                 raw_launch(
@@ -278,6 +416,30 @@ impl PolicyHead {
                 .map_err(|e| anyhow::anyhow!("ppo_clipped_surrogate_fwd: {:?}", e))?;
             }
         }
+        // ── F4.1 block tree-reduce [B] → [1] for both diagnostics ──
+        // Single block, 256 threads (matches BLOCK_X in
+        // ppo_loss_reduce_b.cu). Grid-strided over B so the same launch
+        // serves local b_size=16 and cluster b_size=1024 alike.
+        {
+            let mut args = RawArgs::new();
+            args.push_ptr(loss_pi_per_b.raw_ptr());
+            args.push_ptr(loss_entropy_per_b.raw_ptr());
+            args.push_i32(b_i);
+            args.push_ptr(*loss_pi_scalar_dev_ptr);
+            args.push_ptr(*loss_entropy_scalar_dev_ptr);
+            let mut ptrs = args.build_arg_ptrs();
+            unsafe {
+                raw_launch(
+                    self.loss_reduce_fn.cu_function(),
+                    (1, 1, 1),
+                    (256, 1, 1),
+                    0,
+                    self.raw_stream,
+                    &mut ptrs[..args.len()],
+                )
+                .map_err(|e| anyhow::anyhow!("ppo_loss_reduce_b: {:?}", e))?;
+            }
+        }
         Ok(())
     }