7883c5ca1be2883a1ad8119a59a13fe0d052d795
1190 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
jgrusewski
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7883c5ca1b |
docs(sp22): H6 Phase 2 spec — recenter state[121] to [-1, +1]
Post-mortem of the H6 Phase 1 smoke (WR = 50.21% verdict in `docs/dqn-wire-up-audit.md`) traced an actual pearl violation in the H6 implementation itself: state slot 121 uses the [0, 1] range (`aux_softmax[env, 1] = p_up`) with sentinel 0.5, while every OTHER state slot uses 0 as the "no signal" baseline (zero-padding, feature_mask, ofi-missing, mtf-missing). Per `pearl_first_observation_bootstrap`: "sentinel = 0; first observation replaces directly." The H6 design violated this for slot 121 alone. The encoder must learn TWO things about slot 121: (1) the directional mapping AND (2) the appropriate bias offset for the non-zero baseline — every other dim is single-step (mapping only). Phase 2 is the simplest possible amplification fix: rewrite the bridge to use the same convention as every other state slot. If the encoder can't gradient-couple even after this fix, H6 is truly falsified and we pivot to amplitude scaling or deeper hypothesis. Change scope (atomic per `feedback_no_partial_refactor`): - aux_softmax_to_per_env_kernel.cu: write `2*p_up - 1` instead of `p_up` - gpu_experience_collector.rs: cold-start + FoldReset sentinel 0.5 → 0.0 - experience_kernels.cu: NULL-fallback in 3 state-gather kernels 0.5f → 0.0f - state_layout.rs / state_layout.cuh: comment updates to reflect [-1, +1] range and 0 sentinel Estimated effort: ~45 min walltime (edits + verification gates) + ~25–40 min smoke wall-clock. Verdict criteria (cycle 1 WR + a_var [d/m/o/u] in HEALTH_DIAG[0]): - WR > 50.5% → recentering binding, H6 + Phase 2 sufficient → justify A2 - a_var for mag/ord/urg > 1e-3 → sub-branches learning under recentered signal - WR pinned at 50.1–50.2% → Phase 2 falsified, pivot to amplitude scaling or deeper hypothesis Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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ce1a81552b |
docs(sp22): H6 smoke verdict — falsified at cycle 1 (50.21% WR)
Workflow train-cr9hl on sp20-aux-h-fixed @
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jgrusewski
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7fc9799343 |
feat(sp22): H6 Phase 1 — aux→policy state bridge (atomic)
Wires the aux head's per-env directional probability into policy STATE
slot 121 (AUX_DIR_PROB_INDEX = PADDING_START + 0), preserving the trunk-
separation invariant from `pearl_separate_aux_trunk_when_shared_starves`.
H1 (label horizon) confirmed aux learns 78% dir-acc within-fold at H=200
but the policy was walled off; this commit conducts that signal through
the state input with a one-step lag.
Mechanism (rollout-time, collector-only)
────────────────────────────────────────
- State[env, t] reads `prev_aux_dir_prob[env]` (= p_up from step t-1).
- After aux forward at step t, the new copy kernel writes
`aux_softmax[env, 1]` → `prev_aux_dir_prob[env]` for step t+1.
- Cold-start + FoldReset seed the buffer to 0.5 (neutral; p_up = 50%)
via the pure-GPU `fill_f32` kernel — no HtoD per
`feedback_no_htod_htoh_only_mapped_pinned.md`.
- Launch sits in the same `isv_signals && trainer_params != 0` gate as
the aux forward, so when aux is skipped the cache keeps its previous
(sentinel or last-good) value instead of copying stale `alloc_zeros`.
Three state-gather kernels updated atomically (per
`feedback_no_partial_refactor.md`):
- `experience_state_gather` — training, reads `aux_dir_prob_per_env[i]`
- `backtest_state_gather` — eval (single-step), NULL → 0.5 (A3 fallback)
- `backtest_state_gather_chunk` — eval (chunked), NULL → 0.5 (A3 fallback)
`assemble_state` gained a 7th param `float aux_dir_prob` written to
`out[SL_PADDING_START + 0]`; the remaining 6 padding slots stay zero
for 8-alignment.
Phase 1 scope = training-side + eval A3 NULL fallback. A2 (aux trunk
forward in eval) is deferred per the runbook — gates on whether the
smoke moves WR off the 50.1–50.2% plateau.
New files
─────────
- crates/ml/src/cuda_pipeline/aux_softmax_to_per_env_kernel.cu
Modified
────────
- crates/ml-core/src/state_layout.rs (+AUX_DIR_PROB_INDEX)
- crates/ml/src/cuda_pipeline/state_layout.cuh (+assemble_state param)
- crates/ml/src/cuda_pipeline/experience_kernels.cu
(3 state-gather kernels + NULL-defensive sentinel)
- crates/ml/src/cuda_pipeline/gpu_experience_collector.rs
(per-env buffer + 2 kernel handles + cold-start fill + copy launch
+ FoldReset re-fill + state-gather arg)
- crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs
(NULL aux_dir_prob_per_env at all 3 launchers for A3)
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs
(SP22_AUX_SOFTMAX_TO_PER_ENV_CUBIN static)
- crates/ml/src/cuda_pipeline/gpu_action_selector.rs
(EPSILON_GREEDY_CUBIN → pub(crate) so collector reuses fill_f32)
- crates/ml/build.rs (register new kernel)
- docs/dqn-wire-up-audit.md
(## 2026-05-12 — SP22 H6 implementation: Phase 1 entry)
Verification (all three gates clean, no smoke yet)
──────────────────────────────────────────────────
- cargo check -p ml --features cuda: 0 errors
- gpu_backtest_validation: 4/4 expected-passing tests still pass
(the 2 PnL-assertion failures are pre-existing per the runbook)
- compute-sanitizer --tool=memcheck: 0 CUDA errors
Refs
────
- docs/plans/2026-05-12-sp22-h6-aux-policy-state-bridge.md
- docs/plans/2026-05-12-sp22-h6-next-session-prompt.md
- pearl_separate_aux_trunk_when_shared_starves
- pearl_first_observation_bootstrap (sentinel = 0.5 cold-start)
- feedback_no_htod_htoh_only_mapped_pinned (fill_f32 not HtoD)
- feedback_no_partial_refactor (3 state-gather kernels atomic)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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ff9ec76f18 |
docs(sp22): H6 implementation runbook + next-session prompt
Two new plan docs to enable clean session handoff: 1. docs/plans/2026-05-12-sp22-h6-aux-policy-state-bridge.md Detailed 10-step implementation runbook for H6 (aux→policy state bridge). Each step has file paths, kernel signatures, expected diff, and risk callouts. Estimated ~5hr for Phase 1 (training-side + A3 eval fallback). A2 (eval-side aux integration) is +1 day follow-up if H6 confirmed. 2. docs/plans/2026-05-12-sp22-h6-next-session-prompt.md Concise context-loading prompt to paste into next session. Includes state of the world, runbook pointer, verification gates, and start-here pointer. Why staged: H6 implementation crosses kernel-level state-layout contract (every consumer of STATE_DIM must migrate atomically per feedback_no_partial_refactor). Doing it RIGHT requires careful incremental verification with compute-sanitizer between steps — not safely batched into a tail-end session. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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f50a974fb6 |
docs(sp22): H1 falsified + H6 aux→policy state bridge design
H1 result (commit |
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jgrusewski
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e8814079d9 |
Revert "experiment(sp22): H1 — pin aux pred horizon at 200 bars (atomic)"
This reverts commit
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jgrusewski
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9adbca8262 |
experiment(sp22): H1 — pin aux pred horizon at 200 bars (atomic)
Hypothesis test for SP22 H1 (label horizon mismatch). Finding from v9/v10 HEALTH_DIAG: aux_dir_acc=28-47% (BELOW RANDOM) across all observed cycles. Root cause: adaptive aux_horizon_update collapses H back to ~1.7 bars (observed avg winning hold time), making the aux label HFT microstructure noise. Experiment: 1. Bump SENTINEL_AUX_PRED_HORIZON_BARS 60.0 → 200.0 2. Disable launch_aux_horizon_chain call so H stays at sentinel Predicted: if aux_dir_acc rises >50% → H1 confirmed; if stays ≤50% → escalate to H2/H4 per SP22 plan. Cost: 1 smoke ~30min, kill early on cycle 1-2 trend. Files changed: - crates/ml/src/cuda_pipeline/sp14_isv_slots.rs - crates/ml/src/trainers/dqn/trainer/training_loop.rs - docs/dqn-wire-up-audit.md (H1 experiment entry) Reverts if H1 falsified. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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07332bf057 |
docs(sp21): close-out + v10 findings + SP22 WR plateau plan
SP21 T2.2 status: cascade wiring COMPLETE.
- All E1-E8 enrichment producers wired to consumers
- Local compute-sanitizer clean on eval-baseline closure path
- v9 cycle 1 confirms cascade live: win_conc=1.72, curric_conc=0.31,
hindsight_mag=1.47e-5
- Eval pipeline now hard-fails on GPU error, no CPU fallback,
factored-action branch sizes + default ISV all wired
v10 hypothesis test (10 epochs, killed at E8 with clear answer):
- val_Sharpe peaks at E3 (174), monotonically degrades to E8 (66, -62%)
- WR pinned at 50.1-50.2% across ALL 8 epochs (no improvement)
- PF pinned at 1.00-1.01
- Cascade controllers stable but cannot move policy off the plateau
- Verdict: 3-epoch baseline structure IS optimal; longer training
monotonically degrades. WR plateau is upstream of the cascade.
Implication: SP21 T2.2 cascade is necessary but insufficient for
project_goal_wr_55_pf_2 (WR≥55%, PF≥2.0). Need new SP arc to address
the WR=50% plateau at its source.
New plan: docs/plans/2026-05-12-sp22-wr-plateau-investigation.md
Hypotheses (priority order):
H1: Label horizon mismatch (cheapest, most likely)
H2: Action-space pathology (Hold hiding directional signal)
H3: Reward shape (no directional gradient)
H4: Feature representation gap (MTF features zero-padded)
H5: Bar resolution itself is too noisy (longshot)
Each hypothesis tested as atomic smoke with one variable changed
vs v9 baseline (peak val=174, WR=50.1%).
Phase 1 milestone: WR ≥ 51% on val for ≥ 1 fold.
Phase 2: WR ≥ 53% across 3 folds.
Phase 3: WR ≥ 55% AND PF ≥ 2.0 (SP20+ goal achieved).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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d482efc416 |
fix(sp21): T2.2 Phase 8.4-fix — winner-concentration z-score separation (atomic)
v8 smoke (train-96wfk) confirmed win_conc=0.0000 across all 9 cycles
even when PF crossed 1.0. The Phase 8.2/8.4 threshold tweaks couldn't
fix it because the underlying formula `top_mean / all_mean` is
sign-unstable around `all_mean=0`. PER alpha boost path was dark for
any cold-start policy below PF=1 — exactly the regime where the
boost matters most.
Old: if all_mean ≤ (0.01 * pnl_std).max(0.0) { return 0.0; }
top_mean / all_mean
→ guard trips at PF≤1 → 0.0 (every v8 cycle)
New: ((top_mean - all_mean) / pnl_std).max(0.0)
→ z-score separation: how many pnl_stds above the overall mean
does the top decile sit? By construction top_mean ≥ all_mean,
so separation is non-negative even when all_mean is negative.
→ bounded [0, ∞), scale-invariant, profitability-agnostic.
Expected v9 magnitudes (v8 cycle-1-like inputs):
top_mean ≈ 5e-6, all_mean ≈ 1e-7, pnl_std ≈ 1.08e-5
separation = (5e-6 - 1e-7) / 1.08e-5 ≈ 0.45
Healthy PF>1 cycles likely 0.2..1.5 range.
Pearls honoured:
- pearl_controller_anchors_isv_driven: pnl_std is the signal-driven
scale anchor (replaces hardcoded all_mean denominator)
- feedback_isv_for_adaptive_bounds: z-score formulation removes the
hardcoded multiplier dependency that motivated 8.2 and 8.4's
threshold adjustments
- feedback_no_quickfixes: structural reformulation, not a threshold
tweak (8.2 and 8.4 already showed threshold tweaks couldn't fix
the sign-instability)
Verification:
cargo check -p ml --features cuda # clean
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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9f2d0fffb5 |
fix(sp21): T2.2 Phase 8.7 — default ISV buffer in evaluator (atomic)
v8 smoke (train-96wfk, commit
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jgrusewski
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cb7ace0063 |
feat(sp21): T2.2 Phase 8.6 — curriculum weights via z-score exp(-sharpe) (atomic)
v8 smoke (train-96wfk, commit
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jgrusewski
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5694eb4df2 |
fix(sp21): T2.2 Phase 8.5 — wire factored-action branch sizes into closure-based eval (atomic)
v7 smoke (train-fv4s8, commit
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jgrusewski
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5186701982 |
feat(sp21): T2.2 Phase 8.4 — v6 loose ends (win_conc / curric_conc / hindsight_mag display) (atomic)
Three targeted fixes for v6 smoke (train-x4m96) findings that Phase 8.2
left on the table. v6 cycle-by-cycle showed `win_conc=0.0000` and
`curric_conc=0.0000` pinned across all 9 cycles, and `hindsight_mag`
printed `0.0000` due to format-width rounding.
Fix 1: compute_winner_concentration guard threshold 0.1 → 0.01 × pnl_std
v6 had pnl_std ≈ 1e-5 and val-trade all_mean ≈ 1e-7..1e-6. At 0.1×
the threshold was 1e-6, still above typical all_mean → short-circuit
fired every cycle. At 0.01× (threshold 1e-7) healthy small-but-positive
policies emit a non-zero signal; degenerate-strategy guard preserved.
Fix 2: compute_curriculum_concentration formula
Was: 1 - entropy(weights) / log(n) (entropy-deficit, normalized)
Now: CV(weights) / sqrt(n − 1) (normalized coefficient of variation)
Entropy-deficit is ~weight_std² near uniform. v6's 8 contiguous segments
had per-segment Sharpes in a tight band, so normalized weights stayed
within ~0.5% of 1/n and deficit collapsed to <1e-4 (only cycle 9
reached 0.0001). CV scales linearly with weight_std/weight_mean,
dramatically more sensitive in the near-uniform regime. Cold-start
(uniform) still returns 0; one-hot returns 1.
Fix 3: hindsight_mag display format {:.4} → {:.2e}
pnl_std ≈ 1e-5 on volume bars → hindsight magnitudes are similar scale,
printed as 0.0000 under {:.4} even when the count is non-zero. Matches
pnl_std={:.2e} format already in the log.
Pearls honoured:
- feedback_isv_for_adaptive_bounds: thresholds derived from pnl_std
- pearl_first_observation_bootstrap: uniform/empty inputs → 0.0 sentinel
- pearl_controller_anchors_isv_driven: CV anchor (one-hot = sqrt(n-1))
is structural, not magic
- feedback_no_quickfixes: entropy → CV is a structural reformulation
Verification:
cargo check -p ml --features cuda # clean
Expected v8 smoke (when dispatched):
- win_conc rises to ~1.5..3.0 (top_decile_mean / all_mean ratio)
- curric_conc enters 0.05..0.20 range as segments develop differential
difficulty; grows toward ~0.4 with overfit divergence
- hindsight_mag prints as 5e-6 or similar (real value, not zero)
If these fire, Phase 7 (alpha boost via E6/E7/E8) is finally exercised
end-to-end on volume bars.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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23b89a90e9 |
fix(sp21): T2.2 Phase 8.3+9 — eval pipeline GPU-only, hard-fail, delete CPU path (atomic)
Combined Phase 8.3 (visibility + hard-fail) and Phase 9 (CPU path
removal) per pearl_no_deferrals_for_complementary_fixes. Surfaced by
v6 smoke (train-x4m96) where:
[DQN GPU] Fold 0 GPU eval failed: GpuBacktestEvaluator::evaluate failed
for fold 0. Falling back to CPU path.
[DQN] Fold 0 evaluation failed: Failed to create DQN state tensor for
bar 0: Dimension mismatch: expected 54, got 45
Both fold 0 and fold 1 hit this; workflow exited 0, masking eval
failure for every smoke run since STATE_DIM grew beyond legacy 54.
Root cause (silent GPU failure):
evaluate_dqn_fold_gpu calls evaluator.evaluate(closure, portfolio_dim: 3)
but GpuBacktestEvaluator initialises portfolio_dim = PORTFOLIO_BASE_DIM (8)
+ MTF_DIM (16) = 24 per canonical state layout. gather_states asserts
match → returns MLError::ConfigError. Caller wraps with .with_context()
+ warn!("... {}", e) — `{}` strips anyhow chain, hiding root cause.
The CPU fallback runs with a separate stale 45-dim state builder
(42 from extract_ml_features + 3 portfolio) → fails at GpuTensor::
from_host shape validation against the model's 54-feature default.
Fixes (all atomic):
1. portfolio_dim: 3 → 24 at all 4 call sites (DQN x2, PPO, supervised).
The GPU evaluator's gather_kernel handles full 128-dim state
assembly (Market 42 + OFI 32 + TLOB 16 + MTF 16 + Portfolio 8 +
PlanISV 7 + Padding 7); caller just declares correct portfolio_dim.
2. Surface anyhow chain: {} → {:#} in error messages.
3. Hard-fail on GPU eval failure: anyhow::bail! (no CPU fallback).
Per user directive: "hard fail on gpu panic, cpu path strictly
forbidden should be removed entirely!"
4. DELETE CPU DQN eval path entirely:
- fn evaluate_dqn_fold
- fn build_chunk_states (stale 45-dim state builder)
- fn simulate_chunk_trades
- fn compute_metrics + struct ComputedMetrics
- struct PortfolioState
5. DELETE coupled surrogate-noise machinery:
- struct SurrogateSampler + impl
- fn load_surrogate_marginals
- fn compute_pooled_sharpe
- Surrogate init blocks in main
- ACTION_MARGINALS / POOLED_SHARPE emission blocks
6. DELETE coupled CLI flags:
- --gpu-eval / --no-gpu-eval (GPU mandatory)
- --surrogate-mode, --surrogate-seed, --surrogate-marginals
- --emit-action-marginals, --emit-pooled-sharpe
7. Collapse `if args.gpu_eval { ... }` blocks to direct calls; cleaner
control flow, no gpu_handled tracking.
Pearls honoured:
- feedback_no_cpu_test_fallbacks: GPU oracle only
- feedback_no_partial_refactor: stale CPU layout from pre-STATE_DIM=128 era
- feedback_no_hiding: error chain now visible via {:#}
- feedback_no_legacy_aliases: no deprecated --no-gpu-eval wrapper
- pearl_no_deferrals_for_complementary_fixes: 8.3+9 combined
Files changed:
- crates/ml/examples/evaluate_baseline.rs:
−892 net lines (1066 del, 174 ins; 2817 → 1925)
- docs/dqn-wire-up-audit.md: 2026-05-12 audit entry
Verification:
- cargo check -p ml --example evaluate_baseline --features cuda # clean
- cargo check --workspace --features cuda # clean
- cargo test -p ml --lib --features cuda financials # 7/7
Note: OFI/TLOB/MTF feature-set fidelity is a separate concern. The GPU
gather_kernel handles state assembly; caller currently provides zeroed
OFI (LobBar.ofi = 0.0) and no MTF data. Eval will run, but on degraded
features. Faithful feature wiring deferred to a later Phase once
eval-runs-at-all is validated by v7 smoke.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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79d0c53034 |
feat(sp21): T2.2 Phase 8.2 — signal-drive E6/E7/E8 thresholds via pnl_std (atomic)
Three producers in enrichment.rs had hardcoded magnitude thresholds
sized for time-bar trades (per-trade pnl ≈ 1e-3..1e-2). Foxhunt's
volume bars (bars_per_day ≈ 34_496) produce per-trade pnl in
1e-7..1e-5 range, so the constants tripped every cycle:
- compute_winner_concentration: `all_mean <= 1e-6` → win_conc=0
- compute_hindsight_labels: `t.pnl < -0.001` → hindsight count=0
- compute_curriculum_weights: `(1/sharpe).clamp(0.1, 10.0)` →
similar small Sharpes saturate to 10 →
uniform weights → curric_conc=0
Surfaced by smoke v5 (train-vds7r, commit
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jgrusewski
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d1638959d3 |
fix(sp21): Return v3.1 — drop short-rollout guard for volume bars (atomic)
Single-file fix to `compute_epoch_financials`: remove the `if n_returns_f >= bars_per_year` short-rollout fallback that left v2 semantics in place for sub-year rollouts. For Foxhunt's volume bars, `bars_per_day ≈ 34_496` → `bars_per_year ≈ 8.69M`, while a training epoch produces `n_returns ≈ 4.10M`. The guard fired on every production epoch, so the v3 CAGR fix was a no-op. Diagnosis chain: - v3 commit ( |
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jgrusewski
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62b5a50e8b |
fix(eval): shape-mismatch on checkpoint load — read arch from safetensors metadata (atomic)
Smoke v1 (train-grfcw) evaluate phase failed with "Failed to load DQN
checkpoint" for fold 0 and fold 1. MinIO log inspection confirmed
checkpoints WERE saved (1431144 bytes each) — the failure was
eval-side shape mismatch.
Root cause:
- Training uses STATE_DIM=128 (ml_core::state_layout), num_actions=108
(factored b0*b1*b2*b3=4*3*3*3), num_order_types=3,
num_urgency_levels=3.
- evaluate_baseline CLI defaults: --feature-dim=54, --num-actions=5
(legacy from pre-branching DQN era).
- Loading 128-state-dim 108-action checkpoint into 54-feature 5-action
net → tensor shape mismatch → `load_from_safetensors` returned
parse error → `with_context(...)` wrapped it as the generic "Failed
to load DQN checkpoint" message, hiding the actual shape error.
- Both GPU and CPU eval paths hit the same root cause.
Fix:
Both eval paths now call `DQNConfig::from_safetensors_file(&ckpt_path)`
to read architecture-critical fields from the checkpoint's embedded
metadata (state_dim, num_actions, hidden_dims, num_order_types,
num_urgency_levels, dueling_hidden_dim, num_atoms, gamma). Eval-time
fields (LR, epsilon, buffer caps) overridden; hyperopt-derived gamma/
v_min/v_max applied if present in hyperopt config.
Older checkpoints without embedded metadata fall back to CLI-args-built
config + warn! log. All production SP21+ checkpoints embed metadata
via the existing DQNConfig::checkpoint_metadata path.
Files changed:
- crates/ml/examples/evaluate_baseline.rs: shape-aware config for both
dqn_eval_gpu_path (line ~1238) and dqn_eval_cpu_path (line ~1029)
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry
Verification:
- cargo check -p ml --examples --features cuda: 0 errors
- cargo test -p ml --lib financials: 7/7 (unchanged)
- cargo test -p ml --lib sp21_isv_slots: 4/4 (unchanged)
Behavioral gate: smoke v3 (train-psf86, in-flight on
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jgrusewski
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2937da8898 |
fix(sp21): inflated return + missing best.safetensors at training end (atomic)
Two smoke-driven fixes for issues surfaced by smoke v1 (train-grfcw).
Fix 1: inflated Return (financials.rs)
- Prior `exp(sum(log(1+r_i))) - 1` produced `Return=+8.730e19%` on
~4M step_returns/epoch. Math correct but metric meaningless.
- Fix: ANNUALIZED compounded return (CAGR). For n_returns ≥
bars_per_year, scale log_growth by `bars_per_year / n_returns`
then exp. Short rollouts (tests/warmup) fall back to total
compounded. Clamped to log-space `[-23, +20]` for display sanity.
- Smoke v1 epoch 3 with fix: 24.7% annualized (was +e19%).
- Documented v1→v2→v3 history in comment.
Fix 2: missing dqn_fold{N}_best.safetensors (training_loop.rs)
- Smoke v1 evaluate phase failed with "Failed to load DQN
checkpoint" for fold 0 and fold 1.
- Root cause: async best-worker swallowed errors non-fatally; with
3 epochs and checkpoint_frequency=10, periodic never fired; if
async failed, NO checkpoint existed.
- Fix: guaranteed final save at training end. After async drain,
restore_best_gpu_params + serialize + sync callback(is_best=true).
Idempotent if async already wrote; authoritative if it failed.
All errors here non-fatal (training succeeded; eval reports its
own missing-ckpt at proper boundary).
Files changed:
- crates/ml/src/trainers/dqn/financials.rs: v3 annualized return
- crates/ml/src/trainers/dqn/trainer/training_loop.rs: final save
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry
Verification (passing):
- cargo check -p ml --tests --features cuda: 0 errors
- cargo test -p ml --lib financials: 7/7
- cargo test -p ml --lib sp21_isv_slots: 4/4
- sp20_aggregate_inputs_test: 12/12
- sp20_phase1_4_wireup_test: 2/2
- sp20_emas_compute_test: 4/4
- sp20_controllers_compute_test: 7/7
- sp21_per_trade_predicted_q_test: 3/3
Total: 39 tests, 0 failures.
Smoke v2 (train-rl5x2) is on commit
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jgrusewski
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ad99b79e07 |
feat(sp21): T2.2 Phase 7.5 — E8 curriculum_weights → per-segment PER insert priority boost (atomic)
Closes the "true E8 per-segment PER sampling" deferral from Phase 7.
Phase 7 wired E8's SCALAR concentration to per_update_pa's alpha
boost; Phase 7.5 wires the FULL Vec<f32> of per-segment weights to
per_insert_pa's priority boost.
What lands:
1. 8 new ISV slots [528..536): CURRICULUM_WEIGHT_{0..8}_INDEX.
2. ISV_TOTAL_DIM 528 → 536 (bus extension); fingerprint adds 8 SLOT
entries; CURRICULUM_N_SEGMENTS=8 const + curriculum_weight_index
accessor.
3. per_insert_pa kernel reads isv[528 + seg_id] where seg_id = i % 8
(round-robin segment tag); effective priority × N_SEGMENTS ×
weight[seg_id]. Uniform weights → no-op (× 1.0); cold-start
sentinel → no-op; 0.1× floor against pathological zero-weight
segments preventing sticky exclusion.
4. Producer in training_loop writes 8 ISV slots from
result.curriculum_weights[0..8].
Segment tagging rationale:
- Naïve approach (tag tuples by val-curriculum-segment id) is
infeasible — val and training have separate coordinate systems
(same problem documented in Phase 5+6 audit re E6 winner indices).
- Round-robin via `i % 8` distributes experience-collector's typical
512+ tuple batch evenly across 8 segments. Over time buffer has
equal representation per segment; E8 weights redirect sampling
pressure toward "hard" segments at insert time.
- HEURISTIC mapping (doesn't preserve val-segment semantics) but
consumes the curriculum_weights vector for real PER priority
redistribution — Phase 7.5's stated goal.
Files changed:
- crates/ml/src/cuda_pipeline/sp21_isv_slots.rs: 8 new slot consts
+ N_SEGMENTS + curriculum_weight_index accessor + tests
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump
+ fingerprint
- crates/ml-dqn/src/per_kernels.cu: per_insert_pa per-segment boost
- crates/ml/src/trainers/dqn/trainer/training_loop.rs: producer wireup
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry
Verification (passing):
- cargo check -p ml --tests --features cuda: 0 errors
- cargo test -p ml --lib sp21_isv_slots: 4/4 (new curriculum_weight_
index test)
- sp20_aggregate_inputs_test: 12/12
- sp20_phase1_4_wireup_test: 2/2
- sp20_emas_compute_test: 4/4
- sp20_controllers_compute_test: 7/7
- sp21_per_trade_predicted_q_test: 3/3
Total: 35 tests, 0 failures.
SP21 T2.2 cascade — TRULY fully complete (13 atomic commits). Every
enrichment output E1-E8 wires to a real consumer. No remaining
deferrals or hardcoded controller anchors in SP21 T2.2 scope.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
||
|
jgrusewski
|
39d4577b77 |
feat(sp21): T2.2 Phase 8.1 — signal-drive agree_thr clamp bounds via val_sharpe_std (atomic)
Closes the last hardcoded anchor in compute_agreement_threshold per
pearl_controller_anchors_isv_driven. Smoke-driven motivation: the
9-cycle smoke run of commit
|
||
|
jgrusewski
|
1077f1e165 |
feat(sp21): T2.2 Phase 6.5b — hindsight synthetic injection producer wireup (atomic)
Closes Phase 6.5. The consumer-side infrastructure landed in 6.5a (val state retention + accessor); this commit adds the producer. What lands: 1. GpuReplayBuffer::insert_synthetic_via_pinned (ml-dqn) — raw-u64 dev_ptr mirror of insert_batch's scatter pipeline + per_insert_pa. Takes 7 device pointers + count; bridges from mapped-pinned scratch (in ml crate) to PER's scatter kernels. 2. HindsightScratch struct + MAX_SYNTHETIC_HINDSIGHT=32 constant in enrichment.rs. Holds 7 mapped-pinned buffers (states + next_states + actions + rewards + dones + aux_sign + aux_conf), lazy-allocated. 3. hindsight_scratch: Option<HindsightScratch> trainer field. 4. async fn inject_hindsight_experiences trainer helper: looks up val state at (window_index, bar_index) via 6.5a's read_retained_state, encodes factored action (dir × 27 + mag × 9 + 0 × 3 + 1 for Market/Normal defaults), maps optimal_direction to aux_sign (-1/0/+1), writes reward = counterfactual_pnl, done = 1.0 (terminal), aux_conf = 0.0, calls insert_synthetic_via_pinned. 5. Hook in post-enrichment block — non-fatal warn on infrastructure errors per feedback_kill_runs_on_anomaly_quickly. Design choices: - Terminal done=1: Bellman target reduces to target_q = reward. Avoids synthesizing a valid next_state (optimal counterfactual action would produce a DIFFERENT next state, unsimulable from val data alone). Pure value-target injection at (state, action). - Cap at 32 synthetic per epoch: prevents domination of PER buffer. Scratch alloc ≈ 30 KB pinned host RAM total. - Reward in pnl units: counterfactual_pnl is fraction-of-equity; training reward kernel handles natively (PopArt normalizes). Future scaling via ISV[PNL_REWARD_MAGNITUDE_EMA_INDEX=359] is a one-line follow-up if smoke surfaces gradient outliers. - Mapped-pinned bridge: ml-dqn doesn't have MappedF32Buffer (in ml crate). Raw-u64 API takes dev_ptrs directly — clean cross-crate boundary, no type duplication. Files changed: - crates/ml-dqn/src/gpu_replay_buffer.rs: insert_synthetic_via_pinned API - crates/ml/src/trainers/dqn/trainer/enrichment.rs: HindsightScratch struct + cap const - crates/ml/src/trainers/dqn/trainer/mod.rs: hindsight_scratch field - crates/ml/src/trainers/dqn/trainer/constructor.rs: hindsight_scratch: None init - crates/ml/src/trainers/dqn/trainer/training_loop.rs: inject_hindsight_experiences helper + post-enrichment hook - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification (passing): - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots: 3/3 - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 34 tests, 0 failures. SP21 T2.2 cascade FULLY COMPLETE (Phases 1.5, 2, 3, 4, 4.5, 5+6, 6.5a, 6.5b, 7, 8). All enrichment outputs (E1-E8) wire to real consumers. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
||
|
jgrusewski
|
f29dcc47c9 |
feat(sp21): T2.2 Phase 6.5a — val state retention infrastructure (mapped-pinned, atomic)
Lays the consumer-side infrastructure for true E7 hindsight synthetic injection. Phase 6.5b will follow with the producer wireup. What lands: 1. EvalTrade.window_index + HindsightExperience.window_index fields (host-side only; set in read_per_trade_tape from the w loop var and propagated by compute_hindsight_labels). 2. GpuBacktestEvaluator.retained_states_buf — mapped-pinned MappedF32Buffer sized [max_len × n_windows × state_dim_padded]. Populated by a DtoD copy after every launch_gather_chunk inside submit_dqn_step_loop_cublas; layout matches chunked_states_buf so the copy is a single contiguous block per chunk (no transpose). 3. pub fn read_retained_state(window_idx, bar_idx) — zero-copy host read via std::ptr::read_volatile on host_ptr (no memcpy_dtoh per feedback_no_htod_htoh_only_mapped_pinned). Mapped-pinned decision (jgrusewski review): - Initial draft used CudaSlice<f32> + memcpy_dtoh for host read, caught at review: violates feedback_no_htod_htoh_only_mapped_pinned. - Refactored to MappedF32Buffer (cuMemHostAlloc DEVICEMAP). The DtoD copy remains (rule forbids HtoD/DtoH, not DtoD; kernel writes via dev_ptr aliasing pinned host memory). Caller must sync eval stream before read_retained_state — production path's consume_metrics_after_event already does this. Memory cost at production cfg (max_len=200_000, n_windows=5, state_dim_padded≈128): ~512 MB pinned host RAM. Substantial but feasible on L40S host (192 GB+). Files changed: - crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs: +retained buffer + accessor; EvalTrade.window_index field - crates/ml/src/trainers/dqn/trainer/enrichment.rs: HindsightExperience .window_index field - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification (passing): - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots: 3/3 - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 34 tests, 0 failures. Infrastructure works without exercising it (accessor returns None until eval populates the retained buffer — graceful degradation for test scaffolds bypassing the full eval). After this commit (Phase 6.5b): - Mapped-pinned synthetic-tuple scratch on GpuReplayBuffer - New insert_synthetic_via_pinned API (raw dev_ptrs, no HtoD) - training_loop hindsight injection wireup (~300 LOC) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
||
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jgrusewski
|
1d2dd38a10 |
feat(sp21): T2.2 Phase 8 — signal-drive E2+E5 controller gains via val_sharpe_std (atomic)
Eliminates remaining hardcoded controller GAINS in enrichment.rs per pearl_controller_anchors_isv_driven. Both E2 (compute_adaptive_epsilon) and E5 (compute_agreement_threshold) now derive gain magnitudes from val_sharpe_std = √ISV[VAL_SHARPE_VAR_EMA_INDEX=351] — same signal source as the early-stopping pipeline. Phase 2 already signal-drove the anchors; this commit closes the GAIN half. NO new ISV slots. NO kernel changes. NO ISV_TOTAL_DIM bump. Pure value-driven refactor of two enrichment functions. E2 transformation: - Bracket anchors 2.0/0.5/-0.5 → 2.0×std / 0.5×std / -0.5×std - Multiplicative gains 0.8/0.95/1.2 → (1 ± gain_mag) and (1 - 0.5×gain_mag) - gain_mag = val_sharpe_std.clamp(0.05, 0.30) (Invariant 1 carve-out) - Cold-start (var_ema==0) → pass-through E5 transformation: - Tighten step 0.9 → (1 - gain_mag) - Loosen step 1.1 → (1 + gain_mag) - Same gain_mag formula as E2 (consistency) Invariant 1 carve-outs explicitly retained (project-wide priors): - [0.05, 0.30] gain_mag stability clamp (mirrors Wiener-α floor) - [0.85, 0.98] E3 gamma support range (trading-frequency prior) - [0.5, 2.0] E4 per-branch LR multiplier (collapse/divergence guard) Files changed: - crates/ml/src/trainers/dqn/trainer/enrichment.rs: E2 takes new val_sharpe_var_ema arg; both E2 and E5 derive gains from val_sharpe_std; run_enrichments call-site arg added - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification (passing): - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots: 3/3 - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 34 tests, 0 failures. SP21 T2.2 cascade COMPLETE — all 8 atomic phases landed (1.5, 2, 3, 4, 4.5, 5+6, 7, 8). Remaining future work out of T2.2 scope: - Phase 6.5 (deferred): true E7 hindsight synthetic injection - Phase 7.5 (deferred): true E8 per-segment PER sampling Next operational step: dispatch L40S smoke training run. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
||
|
jgrusewski
|
34d19955ff |
feat(sp21): T2.2 Phase 7 — E8 curriculum_concentration → PER alpha boost (atomic)
Wires E8's curriculum_weights distribution into the per_update_pa alpha boost composition via a new scalar signal: `compute_curriculum_concentration(weights) = 1 - entropy/log(n)`. Same pattern as Phases 5+6 (E6 winner_concentration + E7 hindsight_magnitude); all three feed the same boost_delta sum. Plan revision (mirrors Phase 5+6 pattern): - Original plan: "wire E8 (curriculum weights) → segment sampling weights." Literal interpretation requires new curriculum-segment abstraction in PER (segments don't exist — flat ring buffer today). - Resolution: signal-driven from the SHAPE of the weights distribution (entropy concentration), not the CONTENT (per-segment weighted sampling). Feeds existing per_update_pa kernel; no new segment-sampling kernel. - True per-segment PER sampling deferred to Phase 7.5 (mirrors Phase 6.5 deferral for E7's literal injection consumer). Signal semantics (compute_curriculum_concentration): - Input: Vec<f32> of E8's per-segment weights (sum=1). - Output: 1 - entropy/log(n) ∈ [0, 1]. - 0.0 = uniform (segments equally hard) - 1.0 = one segment dominates (concentrated difficulty) - Single-segment trivially → 1.0 - Cold start (empty input) → 0.0 sentinel - Zero-weight segments skipped (p log p → 0) ISV slot allocation: - CURRICULUM_CONCENTRATION_INDEX = 527 - ISV_TOTAL_DIM 527 → 528 (bus extension) - Layout fingerprint adds SLOT_527 entry Kernel change (4 lines, no ABI churn): - per_update_pa reads isv_signals[527] (already-existing arg from Phase 5+6) - curriculum_term = clamp(curric_conc, 0, 1) × 0.1 ∈ [0, 0.1] - boost_delta upper bound 0.4 → 0.5 to accommodate new term - Cold-start short-circuit predicate extended to all 3 signals Producer wireup: - enrichment.rs: new helper compute_curriculum_concentration; EnrichmentResult.curriculum_concentration field; run_enrichments populates it; log line extended - training_loop.rs: post-enrichment block writes ISV[527] Files changed: - crates/ml/src/cuda_pipeline/sp21_isv_slots.rs: +1 slot const - crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump + fingerprint - crates/ml-dqn/src/per_kernels.cu: 4-line boost composition extension - crates/ml/src/trainers/dqn/trainer/enrichment.rs: helper + field - crates/ml/src/trainers/dqn/trainer/training_loop.rs: write ISV - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification (passing): - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots: 3/3 - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 34 tests, 0 failures. After this commit (Phase 8 + 6.5 + 7.5): - Phase 8: signal-drive remaining controller GAINS in enrichment - Phase 6.5: true E7 hindsight synthetic injection (deferred) - Phase 7.5: true E8 per-segment PER sampling (deferred) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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|
jgrusewski
|
a6087a0b23 |
feat(sp21): T2.2 Phase 5+6 combined — E6/E7 signal-driven PER alpha scaling (atomic)
Wires E6 (compute_winner_indices) + E7 (compute_hindsight_labels) outputs into the PER priority update kernel via signal-driven ISV slots. Phases 5 and 6 combined into one atomic commit per feedback_no_deferrals_for_complementary_fixes — both attack the same consumer kernel (per_update_pa) with non-overlapping refactor scopes (E6 contributes one ISV-mediated scalar, E7 contributes another, kernel composes both into alpha_boost). Plan revision (briefed and accepted 2026-05-11): - E6's literal Vec<usize> of val bar indices CANNOT directly bump training-PER priorities — val and training have separate coord systems (no bar-index → buffer-slot mapping). - E7's true synthetic injection requires val state retention infrastructure (n_windows × max_len × state_dim scratch buffer) — significant scope expansion deferred to Phase 6.5. - The MEANINGFUL signal in both phases is scalar aggregations of the per-trade tape: E6 winner concentration (top-decile-mean P&L / all-mean P&L) and E7 hindsight magnitude (mean |counterfactual_pnl|). Both compose multiplicatively into per_update_pa's alpha_eff. ISV slot allocation: - WINNER_CONCENTRATION_INDEX = 525 - HINDSIGHT_MAGNITUDE_INDEX = 526 - ISV_TOTAL_DIM 525 → 527 (bus extension) - Layout fingerprint adds 2 SLOT entries - Compile-time test asserts SP21_SLOT_END (527) ≤ ISV_TOTAL_DIM Signal semantics: - winner_concentration: top_decile_mean_pnl / max(all_mean_pnl, EPS). > 1.0 = top decile dominates; ≈ 1.0 = uniform; ≤ 0 → 0.0 sentinel (losing strategy, signal ill-defined). - hindsight_magnitude: mean(|counterfactual_pnl|). Higher = larger missed opportunities. - Cold start: both at 0.0 sentinel; kernel short-circuits to alpha_eff = alpha (no-op). ABI surgery (minimal): - per_update_pa: ONE new arg `const float* __restrict__ isv_signals` at end. NULL-tolerant. Reads slots 525/526 device-side, composes boost_delta (bounded [0, 0.4]), applies alpha_eff = alpha + delta. - update_priorities_gpu launcher: passes existing self.isv_signals_dev_ptr (already on struct, settable via set_isv_signals_ptr — same infra per_insert_pa uses for recovery_oversample). Zero new public API. Producer wireup: - enrichment.rs: 2 new helpers (compute_winner_concentration, compute_hindsight_magnitude); EnrichmentResult gains 2 fields (winner_concentration, hindsight_magnitude); run_enrichments populates both; log line extended. - training_loop.rs: post-enrichment block writes both ISV slots via fused.trainer().write_isv_signal_at. Files changed: - crates/ml/src/cuda_pipeline/sp21_isv_slots.rs: +2 slot consts - crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump + fingerprint - crates/ml-dqn/src/per_kernels.cu: per_update_pa ABI + boost logic - crates/ml-dqn/src/gpu_replay_buffer.rs: launcher passes ISV ptr - crates/ml/src/trainers/dqn/trainer/enrichment.rs: 2 helpers + 2 fields + populate - crates/ml/src/trainers/dqn/trainer/training_loop.rs: write 2 slots - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification (passing): - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots: 3/3 - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 34 tests, 0 failures. Behavioral gate (alpha_eff lift on post-warmup val passes) is the upcoming smoke training run. Deferred follow-up (Phase 6.5): true E7 hindsight synthetic experience injection via val state retention + per_insert_pa extension. Significant infrastructure (n_windows × max_len × state_dim scratch + insert API extension). Documented in audit. After this commit (T2.2 Phases 7-8 + 6.5 deferred): - Phase 7: E8 curriculum weights → segment sampling - Phase 8: signal-drive remaining controller GAINS - Phase 6.5: synthetic hindsight injection (deferred — needs val state buffer infrastructure) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
||
|
jgrusewski
|
47e67011c9 |
feat(sp21): T2.2 Phase 4.5 — re-instate Pearl C engagement tracking for branches (atomic)
Closes the Phase 4 deferral. The 4 DqnBranches sub-launches now write
per-block engagement counts to 4 distinct ranges in
clamp_engage_per_block_buf; pearl_c_post_adam_engagement_check
aggregates all 4 ranges into one per-group rate-deficit EMA —
semantically equivalent to the pre-Phase-4 single-launch tracking.
Design: Option (b) sub-block offsetting, mirroring the existing
Curiosity pattern exactly. SP4_ENGAGE_EXTRA_BRANCHES_SUBLAUNCHES = 3
reserves 3 extra slots beyond Curiosity's tail; sub-launch 0 (Dir)
reuses the canonical DqnBranches slot 2; sub-launches 1/2/3 (Mag,
Order, Urgency) get extra slots 11/12/13. This keeps ParamGroup at
8 entries (no taxonomy growth, no 28 new ISV slot allocations).
SP4_ENGAGE_BUF_LEN: 11 → 14 × MAX_BLOCKS_PER_ADAM (45056 → 57344
i32 slots, +12 KiB on a non-hot-path mapped-pinned buffer).
Branch-to-offset mapping:
| Sub-launch | Offset constant | Slot | Buffer offset |
|------------|------------------------------------|------|---------------|
| Dir (b0) | SP4_ENGAGE_OFFSET_BRANCH_DIR | 2 | 8 192 |
| Mag (b1) | SP4_ENGAGE_OFFSET_BRANCH_MAG | 11 | 45 056 |
| Order (b2) | SP4_ENGAGE_OFFSET_BRANCH_ORDER | 12 | 49 152 |
| Urgency(b3)| SP4_ENGAGE_OFFSET_BRANCH_URGENCY | 13 | 53 248 |
pearl_c_post_adam_engagement_check generalized: a `multi_range` flag
covers both Curiosity (4 sub-launches W1/b1/W2/b2) and DqnBranches
(4 sub-launches Dir/Mag/Order/Urgency). Read AND zero-out paths use
the same flag — no duplication of branching logic.
Files changed:
- crates/ml/src/cuda_pipeline/sp4_isv_slots.rs: SP4_ENGAGE_EXTRA_
BRANCHES_SUBLAUNCHES const; SP4_ENGAGE_BUF_LEN formula extended;
SP4_ENGAGE_OFFSET_BRANCH_{DIR,MAG,ORDER,URGENCY}; layout test
updated to 14× MAX_BLOCKS_PER_ADAM
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: launch_adam_update
branch sub-launches use new offsets; pearl_c_post_adam_engagement_
check aggregates DqnBranches multi-range
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry
Verification (passing):
- cargo check -p ml --tests --features cuda: 0 errors
- cargo test -p ml --lib sp4_isv_slots: 2/2 (engage buf layout asserts
14× + branch offsets correct)
- cargo test -p ml --lib sp21_isv_slots: 3/3
- sp20_aggregate_inputs_test: 12/12
- sp20_phase1_4_wireup_test: 2/2
- sp20_emas_compute_test: 4/4
- sp20_controllers_compute_test: 7/7
- sp21_per_trade_predicted_q_test: 3/3
Total: 33 tests, 0 failures. Behavioral gate: HEALTH_DIAG emits
per-branch engagement-rate-deficit EMAs in upcoming smoke run.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
||
|
jgrusewski
|
b7c4f84ea0 |
feat(sp21): T2.2 Phase 4 — wire E4 branch_lr_scale → per-branch Adam (atomic)
Wires EnrichmentResult::branch_lr_scale (E4's [f32; 4] clamped [0.5,
2.0] per-branch LR multiplier) into the DQN Adam optimizer. Splits
the existing single DqnBranches Adam sub-launch into 4 per-branch
sub-launches, each consuming its own LR scale from ISV[521..525).
Plan amendment from on-paper design:
- Plan said "via existing per-group Adam infrastructure" but per-group
operates at PARAM_GROUP granularity (8 groups, all 4 action branches
lumped into DqnBranches). E4 needs per-action-BRANCH granularity.
- Resolution: split DqnBranches sub-launch into 4 per-branch sub-launches
using the already-canonical branch byte ranges (4 param tensors per
branch: Dir [17..21), Mag [21..25), Order [25..29), Urgency [29..33)).
Coverage invariant updated to 7-way (was 4-way).
- Pearl C engagement tracking on branches DEFERRED to Phase 4.5: the
shared DqnBranches engagement counter offset would collide on writes
if 4 sub-launches use the same offset. Pearl C is a diagnostic system
(not load-bearing) so its temporary unavailability for branches is
acceptable; Trunk + Value + Trunk-extras Pearl C still active.
Phase 4.5 follow-up will re-instate via ParamGroup expansion or
sub-block offsetting scheme.
ISV slot allocation:
- BRANCH_LR_SCALE_{DIR,MAG,ORDER,URGENCY}_INDEX = 521..525
- ISV_TOTAL_DIM 521 → 525 (bus extension)
- Layout fingerprint adds 4 SLOT entries
- New branch_lr_scale_index(branch_idx) accessor for clean mapping
- Cold-start floor: launcher reads ISV, floors at 1.0 if at sentinel
0.0 (per pearl_first_observation_bootstrap — first emit replaces
directly with no intermediate state)
ABI surgery:
- dqn_adam_update_kernel: ONE new arg float lr_scale at end of
signature; lr = *lr_ptr * lr_scale inside kernel
- 5 callers migrated atomically per feedback_no_partial_refactor:
- launch_adam_update (main DQN): 7 sub-launches with per-branch
lr_scale (Trunk + Value + 4 branch + Trunk-extras)
- 4 post-aux launchers (ofi_embed/aux_trunk/denoise/sel) pass 1.0
- decision_transformer Adam launch passes 1.0
Producer wireup (training_loop.rs post-enrichment block):
```rust
for (branch_idx, &scale) in result.branch_lr_scale.iter().enumerate() {
fused.trainer().write_isv_signal_at(
branch_lr_scale_index(branch_idx),
scale,
);
}
```
Files changed:
- crates/ml/src/cuda_pipeline/sp21_isv_slots.rs: +4 slots + accessor + tests
- crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump +
fingerprint + 7-way Adam split with per-branch lr_scale
- crates/ml/src/cuda_pipeline/dqn_utility_kernels.cu: lr_scale arg + apply
- crates/ml/src/cuda_pipeline/decision_transformer.rs: lr_scale=1.0
- crates/ml/src/trainers/dqn/trainer/training_loop.rs: write 4 ISV slots
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry
Verification (passing):
- cargo check -p ml --tests --features cuda: 0 errors
- cargo test -p ml --lib sp21_isv_slots --features cuda: 3/3 (bus bounds
+ slot uniqueness + branch index mapping)
- sp20_aggregate_inputs_test: 12/12
- sp20_phase1_4_wireup_test: 2/2
- sp20_emas_compute_test: 4/4
- sp20_controllers_compute_test: 7/7
- sp21_per_trade_predicted_q_test: 3/3
Total: 31 tests, 0 failures. Behavioral gate (per-branch LR divergence)
is the upcoming smoke training run.
After this commit (T2.2 Phases 5-7 + 8 + 4.5):
- Phase 5: E6 winner indices → PER priority bumps
- Phase 6: E7 hindsight → replay buffer injection
- Phase 7: E8 curriculum weights → segment sampling
- Phase 8: signal-drive remaining controller GAINS
- Phase 4.5: re-instate Pearl C engagement tracking for branches
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
||
|
jgrusewski
|
21f911151a |
feat(sp21): T2.2 Phase 3 — wire E1 q_correction → Bellman target offset (atomic)
Wires `EnrichmentResult::q_correction` (Phase 1.5+2's E1 clamp(-mean(predicted_q − pnl), ±10.0) from the per-trade tape) into the training loss kernels' Bellman target computation. Both mse_loss_batched and c51_loss_kernel::block_bellman_project_f apply q_correction as additive shift on the Bellman target — blended (1-α)·MSE + α·C51 sees identical Q-target shifts (symmetric application per feedback_no_partial_refactor). ISV slot allocation (per pearl_controller_anchors_isv_driven + feedback_isv_for_adaptive_bounds — adaptive Q-target shift IS adaptive bound, lives in ISV bus): - New Q_CORRECTION_INDEX = 520 in cuda_pipeline::sp21_isv_slots - ISV_TOTAL_DIM 520 → 521 (bus extension) - Layout fingerprint adds SLOT_520_Q_CORRECTION - New module registered in cuda_pipeline/mod.rs - Compile-time test verifies SP21_SLOT_END <= ISV_TOTAL_DIM Sign convention: q_correction is the additive correction (E1 already negates the bias). predicted_q > pnl → q_correction < 0 → "lower Q-targets". predicted_q < pnl → q_correction > 0 → "raise Q-targets". Cold-start sentinel 0.0 (no trades yet) is no-op until first val pass writes (per pearl_first_observation_bootstrap). ABI surgery (minimal): - mse_loss_batched: ONE new scalar arg (float q_correction) at end - c51_loss_batched: ZERO new args (block_bellman_project_f already takes isv_signals; reads slot 520 from there) - launch_mse_loss: reads ISV[520] host-side via existing read_isv_signal_at, passes scalar - training_loop.rs (post-enrichment): writes result.q_correction to ISV[520] via existing write_isv_signal_at Files changed: - crates/ml/src/cuda_pipeline/sp21_isv_slots.rs (NEW): slot const + bounds-check tests - crates/ml/src/cuda_pipeline/mod.rs: pub mod sp21_isv_slots - crates/ml/src/cuda_pipeline/gpu_dqn_trainer.rs: ISV_TOTAL_DIM bump + fingerprint update + launch_mse_loss launcher arg - crates/ml/src/cuda_pipeline/mse_loss_kernel.cu: q_correction arg + application to target_q - crates/ml/src/cuda_pipeline/c51_loss_kernel.cu: read isv_signals[520] in block_bellman_project_f, add to t_z - crates/ml/src/trainers/dqn/trainer/training_loop.rs: write_isv_signal_at( Q_CORRECTION_INDEX, result.q_correction) post-enrichment - docs/dqn-wire-up-audit.md: 2026-05-11 audit entry Verification: - cargo check -p ml --tests --features cuda: 0 errors - cargo test -p ml --lib sp21_isv_slots --features cuda: 2/2 (bus bounds + slot uniqueness) - sp20_aggregate_inputs_test: 12/12 - sp20_phase1_4_wireup_test: 2/2 - sp20_emas_compute_test: 4/4 - sp20_controllers_compute_test: 7/7 - sp21_per_trade_predicted_q_test: 3/3 Total: 30 tests, 0 failures. Behavioral gate (q_correction → non- zero ISV[520] → Q-target shift) is the upcoming smoke training run. After this commit (T2.2 Phases 4-8): - Phase 4: E4 per-branch LR scaling via per-group Adam - Phase 5: E6 winner indices → PER priority bumps - Phase 6: E7 hindsight → replay buffer injection - Phase 7: E8 curriculum weights → segment sampling - Phase 8: signal-drive remaining controller GAINS Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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fb01906ddc |
docs(claude): foxhunt agents & skills rollout — phase 1 close-out
Phase 1 of the foxhunt specialized agents/skills rollout is complete: 14 commits, 5 auditor agents, 7 workflow/maintenance skills, 2 helper scripts, warn-only PostToolUse hook router. All 8 acceptance criteria from the spec verified. Hook latency 11-13 ms per call (target <200 ms). Memory-write invariant held: only pearl-distiller and memory-curator are authorized writers, no agent-driven memory edits during rollout. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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bc3ebb5fb0 |
docs(claude): foxhunt agents & skills implementation plan — 14 tasks
14-task plan covering: foundation hook router (Task 1), 5 auditor agents (Tasks 2-5, 13), 5 workflow skills (Tasks 6-10), 2 maintenance skills (Tasks 11-12), end-to-end acceptance check (Task 14). Tasks 2-5, 6-8, 9-10, 11-12 fan out in parallel. Task 13 (sp-critical-reviewer) composes the four domain auditors and is built last. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
|
9e6637c065 |
docs(claude): foxhunt-aware agents & skills design — phase 1 (12 items)
Pattern-cluster auditors + workflow-skill hybrid that internalize accumulated project wisdom (15 feedback_*, 30+ pearl_*, 12+ project_* memory files; 30 SP specs) into foxhunt-namespaced agents and skills under .claude/agents/foxhunt/ and .claude/skills/foxhunt/. Phase 1: 5 auditor agents (isv-discipline, gpu-contract, reward-controller, code-hygiene, sp-critical-reviewer) + 5 workflow skills (sp-spec-writer, isv-slot-scaffolder, pearl-distiller, argo-deploy-helper, smoke-pilot) + 2 maintenance skills (memory-curator, stale-worktree-cleaner). Hook integration is warn-only PostToolUse via a single thin router; agents read memory but only pearl-distiller and memory-curator may write into memory/. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
|
26deaa5004 |
feat(sp21): T2.2 Phase 1.5 + Phase 2 — entry_q tracking + enrichment real-tape wireup (atomic)
Closes the multi-step T2.2 work. Phase 1.5 captures entry_q (predicted
Q at trade open) on the per-trade tape; Phase 2 wires
enrichment::run_enrichments to the real GpuBacktestEvaluator
per-trade tape and deletes the fake-trade synthesizer
(extract_eval_trades_from_metrics) per feedback_no_stubs.
Plan amendment from on-paper design:
- Audit caught plan's "portfolio_state[ps+6] is unused" claim was
wrong — slot 6 is in active use as cum_return. Replaced with a
dedicated entry_q_state_buf [n_windows] separate from
portfolio_state. Doesn't touch shmem layout, gather kernel, or
model state-dim.
- E5 design question resolved as option (2): quartile-spread Sharpe
with ISV-driven significance anchor read from
ISV[VAL_SHARPE_VAR_EMA_INDEX=351] (per
pearl_controller_anchors_isv_driven). Hardcoded 1.5σ/0.5σ
thresholds eliminated; the noise floor is the val_sharpe variance
EMA already produced per epoch by the early-stopping pipeline.
- Single-step evaluate() launcher passes NULL q_values_per_window
(forward_fn closure exposes only action indices, not Q-values);
same NULL-tolerant pattern as exploration_scale_ptr et al. The
production val pipeline (chunked path) DOES wire real Q-values.
Files (atomic per feedback_no_partial_refactor):
- backtest_env_kernel.cu: 4 new args at end of both kernels
(entry_q_state, q_values_per_window, num_actions,
per_trade_predicted_q_out); pre_entry_q snapshot + close emit +
open/reverse capture.
- gpu_backtest_evaluator.rs: entry_q_state_buf + per_trade_predicted_q_buf
allocated; both reset in reset_evaluation_state; both launchers
migrated; EvalTrade.predicted_q field added; read_per_trade_tape
populates it.
- trainer/enrichment.rs: EvalTrade is now pub(crate) use re-export
from gpu_backtest_evaluator (drops ensemble_var); E5 refactored
to quartile-spread Sharpe with ISV-driven anchor;
extract_eval_trades_from_metrics deleted; HindsightExperience
retained (Phase 6 wiring).
- trainer/training_loop.rs: enrichment block replaced with
evaluator.read_per_trade_tape() + ISV slot 351 read; val_bars /
real_trade_count / real_total_pnl / real_win_rate plumbing
dropped.
- trainer/{mod,constructor,metrics}.rs: last_val_metrics field
removed (last consumer gone — feedback_no_hiding).
- docs/dqn-wire-up-audit.md: 2026-05-11 audit entry.
Verification (passing):
- SQLX_OFFLINE=true cargo check -p ml --tests --features cuda
- sp20_aggregate_inputs_test (12/12)
- sp20_phase1_4_wireup_test (2/2)
- sp20_emas_compute_test (4/4)
- sp20_controllers_compute_test (7/7)
After-this scope (Phase 3-7 + Phase 8 in T2.2 multi-phase):
- E1 q_correction → ISV slot consumer
- E4 per-branch LR scaling via per-group Adam
- E6 winner indices → PER priority bumps
- E7 hindsight → replay buffer injection
- E8 curriculum weights → segment sampling
- Signal-drive remaining controller GAINS (0.9/1.1 in E5; 2.0/0.5/-0.5 in E2)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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c274b99ea9 |
docs(sp21): T2.2 Phase 1.5 + Phase 2 continuation plan + amendment
Adds the continuation plan for SP21 T2.2 Phase 1.5 (entry_q tracking
in portfolio_state slot 6) + Phase 2 (wire enrichment to real
per-trade tape from gpu_backtest_evaluator). Self-contained plan
that a fresh session can pick up cold:
- State-at-session-start summary with all 8 prior commits
- Phase 1.5 design (storage slot, capture site, plumbing,
EvalTrade extension)
- Phase 2 design (training_loop wire-up, enrichment refactor,
E5 alternate-signal options with recommendation)
- Hard rules carried from prior session (no NULLs, no stubs,
atomic per feedback_no_partial_refactor)
- Verification plan (5 GPU oracle test suites)
- Open design question (E5 alternate signal) with recommendation
- Multi-phase continuation map (Phases 3-7 + Phase 8)
- Final cascade verification (smoke run criteria)
Also amends the parent SP21 plan
(2026-05-10-sp21-train-eval-coherence-isv-defrost.md) with the
T2.2 multi-phase scope section that documents the full per-trade-tape
expansion the user committed to (option 3 — full wiring across
multiple sessions instead of the original recommended option (b)
aggregate-stats refactor).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
7d538d9304 |
feat(sp21): T2.2 Phase 1 Step B — per-trade tape buffers + readback (atomic)
Replaces Step A's NULL launcher passes with real device buffers.
Both kernel launch sites in gpu_backtest_evaluator.rs (backtest_env_step
and backtest_env_step_batch) now pass real per-trade tape pointers.
The kernel's per-trade emission block fires unconditionally on close
events — single-threaded per-window writes preserve event ordering and
enable race-free counter increment without atomicAdd.
New constants + types:
- MAX_TRADES_PER_WINDOW = 200_000 (typical eval window bar count;
per-window memory: 4 SoA buffers × 4 bytes × 200k = 3.2MB)
- pub struct EvalTrade with 5 fields: bar_index, pnl, holding_bars,
direction, magnitude. Does NOT include predicted_q / ensemble_var
— those need entry-time captures (entry_q, entry_var in portfolio
state) deferred to Phase 1.5.
New struct fields on GpuBacktestEvaluator:
- per_trade_pnl_buf: CudaSlice<f32> [n_windows × MAX_TRADES]
- per_trade_holding_bars_buf: CudaSlice<u32>
- per_trade_bar_index_buf: CudaSlice<u32>
- per_trade_dir_mag_buf: CudaSlice<u32> (packed dir/mag)
- per_trade_count_buf: CudaSlice<u32> [n_windows]
New methods:
- reset_per_trade_tape (folded into reset_evaluation_state): zeros
the count buffer at the start of each eval window. SoA value
buffers don't need zeroing — read up to count[w] only.
- pub fn read_per_trade_tape(&self) -> Result<Vec<EvalTrade>, MLError>:
reads count buffer first (cheap), early-returns empty if no trades,
else reads 4 SoA buffers (~16MB DtoH at PCIe ≈ 1ms) and flattens
window-major into chronological Vec<EvalTrade>.
Phase 2 follow-up (next commit) — wire read_per_trade_tape to the
enrichment caller in training_loop.rs:1510-1568, replacing
extract_eval_trades_from_metrics (the fake-trade synthesizer).
Phase 1.5 follow-up (if Phase 2 keeps E1+E5) — add entry_q + entry_var
to portfolio_state at trade open, extend per-trade tape with 6th/7th
SoA buffers.
Affected files:
- crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs
(constants, struct fields, alloc, construction, 2 launcher sites,
reset_evaluation_state addition, read_per_trade_tape method)
Verification:
- cargo check -p ml --tests: passes (warnings only)
- GPU oracle tests: behavior preserved by construction (existing
WindowMetrics aggregator unaffected — separate kernel)
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
T2.2 multi-phase scope; Phase 1 Step B closure.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
5d01190e19 |
feat(sp21): T2.2 Phase 1 Step A — per-trade tape kernel ABI (atomic)
Extends backtest_env_step + backtest_env_step_batch kernel signatures
with 6 new NULL-tolerant args for per-trade tape emission:
- float* per_trade_pnl_out
- unsigned int* per_trade_holding_bars_out
- unsigned int* per_trade_bar_index_out
- unsigned int* per_trade_dir_mag_out (packed hi-16 dir, lo-16 mag)
- unsigned int* per_trade_count
- int max_trades_per_window
Each kernel snapshots entry_price + hold_time BEFORE the
unified_env_step_core call, then post-call mirrors
record_kelly_trade_outcome's close-detection predicate
(is_exit || is_reversal with positive entry_price + valid pre-trade
equity guards) to recompute the realized return for per-trade tape
emission. Single thread per window writes its own slot — race-free
counter increment without atomicAdd per feedback_no_atomicadd.
Step A only — Step B (host alloc + readback + enrichment integration)
follows in a separate commit. This commit is the kernel ABI extension
with NULL launchers, bit-identical to pre-Phase-1 behavior.
NULL-tolerant ABI extension is the codebase's canonical phased-rollout
pattern. Same shape as alpha_per_env / is_win_per_env additive contracts
in sp20_aggregate_inputs_kernel. Per feedback_no_partial_refactor's
"consumer migrates with contract change" rule, the consumer (launcher)
MIGRATES here by passing NULL — output behavior preserved bit-identically.
Step B (next commit):
- Allocate per-trade buffers in GpuBacktestEvaluator constructor
- Pass real device pointers from launcher
- Reset per-window counter at fold start
- Host-side readback into Vec<EvalTrade>
- Wire to enrichment caller, replace extract_eval_trades_from_metrics
Affected files:
- crates/ml/src/cuda_pipeline/backtest_env_kernel.cu (both kernels)
- crates/ml/src/cuda_pipeline/gpu_backtest_evaluator.rs (both launchers)
Verification:
- cargo check -p ml --tests: passes (warnings only)
- GPU oracle tests: NULL-tolerance contract preserved by construction
(per_trade_count == NULL gates the entire emission block)
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
T2.2 multi-phase scope section.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
4ab1c132e8 |
feat(sp21): T2.1+T2.4 — Q-value early-stop + MIN_HOLD zombies deleted
Closes two architectural-debt items from SP21 Tier 2.
T2.1 — check_early_stopping(avg_q_value) deleted entirely:
- Combined two failed mechanisms: (a) Q-value floor — not a learning
signal (high Q can mean edge OR value explosion, indistinguishable);
(b) Sharpe plateau with hardcoded `improvement < 0.01` threshold,
structurally meaningless against typical val-sharpe deltas O(1-10).
- Both subsumed by the SP21 T1.1a+T1.1b val-loss patience early-stop
with signal-driven min_delta from VAL_SHARPE_VAR_EMA.
- Legacy `old_should_stop` branch + function body deleted.
- Per feedback_no_legacy_aliases.
T2.4 — MIN_HOLD_TARGET / MIN_HOLD_PENALTY_MAX #defines deleted:
- Investigation: macros referenced ONLY in comments and the defining
line itself — no actual code use. The SP12 v3 production callers
were removed in SP20 Phase 2 Task 2.2.
- HEALTH_DIAG line at training_loop.rs:5159 updated to drop the dead
30.0/3.0 literals.
- Scope boundary: MIN_HOLD_TEMPERATURE_* chain is NOT a zombie —
actively wired (kernel producer + SP16 controller consumer).
- Per feedback_no_legacy_aliases.
T2.5 — PER hyperparams disposition (no code change):
- per_alpha=0.6, per_beta_start=0.6 are paper-canonical (Schaul et al.).
Per the SP21 plan recommendation, kept fixed for SP21. Filed for a
separate SP if later identified as a leverage point.
Affected files:
- crates/ml/src/trainers/dqn/trainer/metrics.rs:435-488
(check_early_stopping body deleted)
- crates/ml/src/trainers/dqn/trainer/training_loop.rs (7253 caller +
7291-7322 old_should_stop branch + 5159-5167 HEALTH_DIAG line)
- crates/ml/src/cuda_pipeline/state_layout.cuh:317-318
(#defines deleted)
Verification:
- cargo check -p ml --tests: passes (warnings only)
Cumulative SP21 Tier 2 status: T2.1 ✓, T2.4 ✓, T2.5 ✓ (deferred-doc).
T2.2+T1.3 (enrichment.rs constants soup, ~400 LOC) remaining.
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
c90553953c |
feat(sp21): T1.2+T1.4 — enrichment real metrics + backtracking signal-driven (atomic)
Closes the remaining SP21 Tier 1 hardcoded-constant items.
T1.2 — enrichment fed real metrics, not placeholders:
- was: extract_eval_trades_from_metrics(_, 60000.0, 0.0, 0.5, ...)
with hardcoded trade_count=60000, total_pnl=0.0, win_rate=0.5
- now: reads from self.last_val_metrics: Option<[f32; 14]> populated
by val backtest pass at metrics.rs:868. Layout [2]=win_rate,
[4]=total_trades, [7]=total_pnl. Cold-start fallback (None)
is (0.0, 0.0, 0.0) — preferable to fabricated 60000-trade
signal that biased E2/gamma/ensemble from epoch 0.
- Per feedback_no_todo_fixme + feedback_no_stubs.
T1.4 — backtracking thresholds signal-driven:
- Three hardcoded thresholds in run_backtracking_epoch_end replaced
with sigma = sqrt(ISV[VAL_SHARPE_VAR_EMA_INDEX=351]) derivatives:
a) Save trigger (improvement_rate > 0.01) → > 0.5σ.
The 0.01 fired on every epoch (any tiny change > 0.01);
0.5σ requires a meaningful move (typical sigma O(1-10)).
b) Plateau-detection frozen check (abs(delta) < 0.01) → < 0.5σ.
The 0.01 ~never fired; 0.5σ correctly identifies stagnation.
c) Route acceptance (>= min_improvement_rate=0.1) → >= 1.5σ.
Stricter than save-trigger as designed.
- BacktrackingState::min_improvement_rate field deleted — replaced
by per-call signal-driven computation. Floor 0.5 covers cold-start
before var_ema bootstraps from sentinel per
pearl_blend_formulas_must_have_permanent_floor.
- Per feedback_isv_for_adaptive_bounds + feedback_adaptive_not_tuned.
Affected files:
- crates/ml/src/trainers/dqn/trainer/training_loop.rs:1510-1530
(T1.2 enrichment) + :7458-7530 (T1.4 sigma + 3 threshold sites)
- crates/ml/src/trainers/dqn/trainer/mod.rs:108,142
(T1.4 min_improvement_rate field deletion)
Verification:
- cargo check -p ml --tests: passes (warnings only)
- cargo test -p ml --lib early_stopping: 8/8 pass
Cumulative SP21 Tier 1 status: T1.1a ✓, T1.1b ✓, T1.2 ✓, T1.4 ✓,
T2.3 ✓ — Tier 1 closed. Tier 2 (check_early_stopping(avg_q_value)
deletion + enrichment.rs constants soup) is next.
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
74c7a80114 |
feat(sp21): T1.1a+T1.1b+T2.3 — signal-driven early-stopping (atomic)
Closes the patience-based early-stopping bug that ran xmd6b 30 epochs
past peak val performance (epoch 2: val_Sharpe=90, total_pnl=0.44 →
epoch 30: val_Sharpe=26, total_pnl=0.16) — a 70% loss of alpha to
training-induced overfitting.
Two intertwined bugs, fixed atomically:
T1.1a (wrong-source) at training_loop.rs:7234:
- was: self.early_stopping.should_stop(-log_output.epoch_sharpe, epoch)
reading the TRAINING ROLLOUT Sharpe (Thompson-noisy, in-sample,
oscillates even when the model is frozen)
- now: self.early_stopping.should_stop(log_output.val_loss, min_delta, epoch)
reading the deterministic-backtest val_loss
- The comment 5733 lines earlier (line 1499) explicitly says "Use
val_Sharpe (deterministic backtest), NOT epoch_sharpe" — patience
path was the inconsistency, backtracking already honored it.
T1.1b (hardcoded threshold) in early_stopping.rs:
- was: EarlyStopping::new(patience, min_delta) with min_delta=0.001
constructor-set, struct field, structurally meaningless
against the val_loss noise floor (typical val_sharpe deltas
are O(1-10), so 0.001 essentially never gates)
- now: EarlyStopping::new(patience), should_stop(val_loss, min_delta,
epoch) with min_delta computed per-call from
ISV[VAL_SHARPE_VAR_EMA_INDEX=351] as
sqrt(var_ema).max(0.5)
- Floor 0.5 covers cold-start before var_ema bootstraps from sentinel
per pearl_blend_formulas_must_have_permanent_floor.
- Per feedback_isv_for_adaptive_bounds + feedback_adaptive_not_tuned.
T2.3 (test signature update) absorbed:
- 6 existing unit tests migrated to new should_stop signature.
- 1 NEW test (test_min_delta_can_change_per_call) verifying per-call
threshold change works correctly.
- EarlyStopping::min_delta struct field deleted.
- Atomic per feedback_no_partial_refactor.
Affected files:
- crates/ml/src/trainers/dqn/early_stopping.rs (struct + tests)
- crates/ml/src/trainers/dqn/trainer/constructor.rs (new() arg)
- crates/ml/src/trainers/dqn/trainer/training_loop.rs (call site)
Verification:
- cargo check -p ml --tests: passes
- cargo test -p ml --lib early_stopping: 8/8 pass
Behavioral expectation post-fix: xmd6b-shape runs (val_Sharpe rising
31→90 epochs 0-2, declining 90→26 epochs 3-30) will trigger early-stop
near the peak. With patience=5 and var_ema bootstrapping by epoch 2-3,
the controller detects "no improvement of ≥ 1σ for 5 consecutive
epochs" by ~epoch 7-8 and stops, saving ~22 epochs of overfitting.
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
Tier 1 status: T1.1a ✓, T1.1b ✓, T2.3 ✓ (this commit). T1.2 + T1.4 next.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
|
4d4cd996db |
feat(sp21): T3.3 ISV defrost — hold_reward_ema (atomic Phase 3.2 wireup)
Closes the Phase 3.2 forward-reference loop in the SP20 aggregator.
Previously `out_inputs->per_bar_hold_reward = 0.0f` was hardcoded; the
per-bar Hold opportunity-cost producer existed
(experience_kernels.cu:3823 — `per_bar_opp_cost = -aux_conf × cost_scale`)
and wrote to `hold_baseline_buffer` and `r_micro` directly, but never
reached HOLD_REWARD_EMA. Result: HOLD_REWARD_EMA frozen at sentinel 0.0
across all observed epochs; the SP20 reward centering loop
(`r_micro += per_bar_opp_cost - HOLD_REWARD_EMA`) stayed uncentered,
biasing the policy's reward signal away from zero-mean.
T3.3 wireup mirrors the T2.2 alpha refactor: a per-env scratch buffer
that the producer writes at every step (alongside the existing
`hold_baseline_buffer` write), and the aggregator reads at the same
step. Sums opp_cost over Hold-direction envs only; emits the mean as
`per_bar_hold_reward`. The HOLD_REWARD_EMA's gate (`hold_fraction > 0.5f`
from T3.2) preserves the strict-majority semantic from before.
Atomic across producer site, kernel signature, aggregator, launcher,
collector, and tests (per feedback_no_partial_refactor):
- experience_kernels.cu — new `float* per_bar_opp_cost_per_env`
kernel arg, NULL-tolerant write at line ~3823.
- sp20_aggregate_inputs_kernel.cu — new arg, 6th shmem stripe
(`sh_opp_cost_sum`), per-thread Hold-gated accumulation, tree
reduction extended to 6 stripes, output `per_bar_hold_reward =
opp_cost_sum / hold_count` when hold_count > 0 else 0.
- sp20_aggregate_inputs.rs — launcher signature, dynamic_shmem_bytes
5→6 stripes, doc table, internal test.
- gpu_experience_collector.rs — new `per_bar_opp_cost_per_env:
CudaSlice<f32>` field, alloc, struct construction, kernel-arg
pass at both experience_env_step and sp20_aggregate_inputs
launches (raw_ptr).
- sp20_aggregate_inputs_test.rs — helper renamed
`run_kernel_with_is_win_and_opp_cost`, 4 existing sites pass
NULL, 2 NEW oracle tests verifying real producer + NULL fallback.
- sp20_phase1_4_wireup_test.rs — NULL fallback at the wireup site;
HOLD_REWARD_EMA-stays-at-zero assertion remains valid.
Verification:
- cargo check -p ml --tests: passes (warnings only)
- cargo test -p ml --test sp20_aggregate_inputs_test --features cuda
-- --ignored: 12/12 GPU oracle tests pass on RTX 3050 Ti, including
both new T3.3 tests (per_bar_hold_reward_means_over_hold_envs_only,
null_per_bar_opp_cost_emits_zero).
- cargo test -p ml --test sp20_phase1_4_wireup_test --features cuda
-- --ignored: 2/2 pass under the new NULL-tolerant contract.
Plan reference: docs/plans/2026-05-10-sp21-train-eval-coherence-isv-defrost.md
Tier 3 status: T3.1 ✓, T3.2 ✓, T3.3 ✓ (this commit), T3.4 withdrawn,
T3.5 cascade-pending, T3.6 withdrawn.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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1790a31b66 |
feat(sp21): T3.1+T3.2 ISV defrost — wr_ema + hold_pct_ema (atomic)
SP21 Tier-3 foundation: defrost two production-frozen ISV slots that
pinned at 0 across every observed training epoch (d7bj7, xmd6b). Both
bugs in the same aggregator kernel, same structural shape: per-step
binary majority-vote indicators feeding fractional EMAs.
T3.1 — WR_EMA defrost (sp20_aggregate_inputs_kernel.cu):
- was: is_win_out = (2 * wins_count >= closed_count) ? 1 : 0
binary "majority won this step" indicator
- now: win_fraction_out = (float)wins_count / (float)closed_count
fractional in [0, 1]
- With actual val WR≈0.46, the binary signal was 0 most of the time,
pinning WR_EMA at 0 across 30+ epochs in xmd6b. EMA now converges
to population win rate.
T3.2 — HOLD_PCT_EMA defrost (same kernel, same pattern):
- was: action_is_hold_out = (hold_count * 2 > n_envs) ? 1 : 0
strict-majority indicator
- now: hold_fraction_out = (float)hold_count / (float)n_envs
- Cascade: HOLD_COST_SCALE controller compared hold_pct_ema=0 to
tgt±0.05, always saw < lower, ramped × 0.95 → clamped at floor
0.01 (the hold_cost_scale=0.0100 observation in d7bj7 logs).
T3.5 expected to cascade-fix in next training run.
- HOLD_REWARD_EMA gate preserves strict-majority semantic via
hold_fraction > 0.5f test in the consumer kernel.
Atomic across struct fields, kernel logic, Rust mirror, byte
serialization, doc tables, and 4 test files (per
feedback_no_partial_refactor):
- sp20_aggregate_inputs_kernel.cu (struct + 2 computations)
- sp20_emas_compute_kernel.cu (struct + reader + gate)
- sp20_aggregate_inputs.rs (doc table)
- sp20_emas_compute.rs (Rust struct + serialize + 3 tests)
- sp20_aggregate_inputs_test.rs (reader sig + 4 test assertions)
- sp20_emas_compute_test.rs (5 struct literal updates)
- sp20_phase1_4_wireup_test.rs (HOLD_PCT_EMA expected 0.625)
Verification:
- cargo check -p ml --tests: passes (warnings only)
- cargo test -p ml --lib sp20_emas: 6/6 unit tests pass
Pearl candidate: binary-majority aggregator over a fractional
underlying signal cannot serve as input to a fractional-target EMA.
The previous fix (commit
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jgrusewski
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6df44e4c6d |
docs(sp21): plan + revert sp20-aux-h-fixed experiment
Reverts the forced H=30 diagnostic in aux_horizon_update_kernel.cu
(commit
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jgrusewski
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c78c4766ca |
experiment(sp20-aux-h-fixed): force H=30 to test bootstrap failure hypothesis
Throwaway diagnostic edit on aux_horizon_update_kernel.cu. Tests whether the adaptive horizon's self-defeating loop (WR=50% → H~2 → noise horizon → 53.5% acc → WR=50%) is the actual bottleneck. If aux_dir_acc rises to 58%+ at fixed H=30, bootstrap failure confirmed and the proper fix is constraint-based (min hold time during exploration). Audit-doc updated. DO NOT merge to mainline — branch is throwaway after the experiment. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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d6bfad7033 |
docs(sp20): consolidate Phase 5 audit-doc + close-out
Replaces the per-commit audit-doc entries from commits 1-3 with a single
consolidated Phase 5 close-out entry. The consolidated entry covers:
- The full design rationale: gate the REWARD (not the target); avoids
needing q_mean_a entirely. At low aux confidence, r_used → 0 ⇒
Bellman target collapses to gamma * Q(s', a').
- All 5 components: trainer buffer, FusedTrainerCtx accessor, training
loop wire-up, kernel signature + gate, launcher arg.
- NULL-tolerance contract: aux_conf_at_state == NULL OR isv_signals
== NULL ⇒ gate = 1.0 (identity).
- Default-state semantics: alloc_zeros 0.0 sentinel → gate ≈ 0.12 →
reward mostly suppressed pre-population (graceful degradation).
- reward_bias interaction (composes cleanly — gate damps reward
pre-projection, reward_bias lifts target Q-mean per-branch).
- Plan accuracy errata: the user spec's "add aux_conf_at_state_buf
field to GpuBatch struct" was unnecessary — GpuBatch doesn't
carry the SP13 B1.1b aux_sign_labels_ptr either; both follow the
"trainer-only buffer + direct-gather" pattern.
- Test coverage: 3 CPU math tests + 1 GPU behavioral integration test.
- Confidence: medium-high that the gate fires correctly on real data;
end-to-end smoke validation deferred (no smokes dispatched per
controller instruction).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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ab4a7db33c |
feat(sp20): c51_loss launcher aux_conf arg + Phase 5 gate tests
Threads `self.aux_conf_at_state_buf` into the `c51_loss_batched` launch
in `GpuDqnTrainer::launch_c51_loss`. Position matches the kernel's
appended trailing arg from the previous commit.
Tests added in `crates/ml-dqn/src/gpu_replay_buffer.rs::tests`:
- `aux_gate_high_confidence_passes_full_target` (CPU pure-math):
gate(aux_conf=0.5, threshold=0.10, temp=0.05) > 0.99 proves
high-confidence reward pass-through.
- `aux_gate_low_confidence_attenuates_reward` (CPU pure-math):
gate(aux_conf=0.02, threshold=0.10, temp=0.05) < 0.20 proves
the uncertain-state neutralizer semantic.
- `aux_gate_temp_floor_keeps_gate_finite` (CPU pure-math):
sweeps {temp, aux_conf, threshold} and asserts finite gate ∈ [0,1]
across the ISV-controllable parameter range — proves the
fmaxf(temp, 1e-3) floor keeps the kernel numerically safe.
- `aux_conf_direct_to_trainer_gather_populates_destination` (GPU
behavioral): wires a fresh CudaSlice<f32> as the trainer
destination, inserts 8 transitions with strictly-positive distinct
aux_conf values, samples 1, asserts the trainer destination
buffer post-sample holds a value from the inserted set (NOT the
alloc_zeros sentinel) — proves the direct-gather wiring actually
populates the trainer buffer with non-trivial data.
All 3 CPU math tests + 1 GPU integration test pass on RTX 3050.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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96b76d9298 |
feat(sp20): c51_loss_batched aux_conf_at_state reward gate
Adds the Phase 5 consumer kernel-side gate. New kernel arg `const float* __restrict__ aux_conf_at_state` appended to `c51_loss_batched`'s signature. Gate computation runs once per sample at the kernel-entry reward-setup site (after the #27 ensemble- disagreement adjustment), then the gated `reward` propagates through every branch's `block_bellman_project_f` call without per-branch changes. Formula: gate = sigmoid((aux_conf - threshold) / temp) reward = gate * reward where: threshold = ISV[AUX_CONF_THRESHOLD_INDEX=518] temp = max(ISV[AUX_GATE_TEMP_INDEX=519], 1e-3) Mathematical interpretation: at low aux confidence (gate→0), `r_used → 0`, so the Bellman target becomes `gamma * Q(s', a')`. The Q value at the current state collapses toward `gamma * Q(s', a')` — model gets no reward feedback on uncertain transitions. Effectively "don't update Q on uncertain transitions" — the "uncertain-state neutralizer" semantic from the Phase 3 Task 3.4 audit doc spec §4.4. NULL-tolerant: `aux_conf_at_state == NULL` OR `isv_signals == NULL` ⇒ gate skipped (identity, no-op = pre-Phase-5 behaviour). Test scaffolds without a wired aux head still work. Out of scope: `iqn_dual_head_kernel.cu` — IQN is the auxiliary loss, C51 is production. Gating IQN is more complexity for marginal gain. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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d3a057af4f |
feat(sp20): allocate trainer aux_conf_at_state_buf + wire PER direct-gather
Phase 5 plumbing — consumer-side wire-up. Allocates `aux_conf_at_state_buf: CudaSlice<f32>` ([batch_size]) on `GpuDqnTrainer`, exposes the raw_ptr via `aux_conf_at_state_buf_ptr()` and the `FusedTrainerCtx` delegating accessor `trainer_aux_conf_at_state_buf_ptr()`, and invokes `GpuReplayBuffer::set_trainer_aux_conf_ptr` at both fused_ctx init sites in training_loop.rs (init + re-init, atomic per `feedback_no_partial_refactor`). The PER `gather_f32_scalar` now writes the SAMPLED bar's per-batch aux_conf directly into the trainer's f32 buffer on every step — same direct-to-trainer pattern as the SP13 B1.1b `aux_nb_label_buf` (i32) wire-up immediately above the new call. The c51_loss_batched reward gate (lands in the next commit) reads this buffer to compute `gate = sigmoid((aux_conf - ISV[AUX_CONF_THRESHOLD]) / ISV[AUX_GATE_TEMP])` and applies `r_used = gate * reward` at the Bellman projection. `alloc_zeros` cold-start: 0.0 sentinel → at threshold ≈ 0.10 and temp ≈ 0.05 the gate is `sigmoid(-2) ≈ 0.12` → reward is mostly suppressed pre-population. This is the "graceful degradation" semantic from the Phase 3 Task 3.4 audit doc spec §4.4. Once PER's direct-gather populates from the producer ring on the first sample step, the per-bar aux_conf values drive the gate as designed. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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d1a8ec206f |
fix(sp20): bump MAX_UPLOAD_BYTES 2GB → 8GB + audit doc
L40S (48GB) and H100 (80GB) have plenty of headroom; the 2GB cap was a conservative leftover that tripped on workflow zgjgc with 17.8M imbalance bars (3.2GB). 8GB budget leaves ~28GB free on L40S after model + activations + workspace. Updates both call sites: - DqnGpuData::upload_slices (training data, the failing one on zgjgc) - PpoGpuData::upload (market data, same constant) Error message format strings updated 2.0 GB → 8.0 GB. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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jgrusewski
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6289710463 |
merge(sp20): restore is_win_per_env across struct/launcher/registry after Phase 3 cherry-pick
Cherry-picking Phase 3 ( |
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jgrusewski
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dd9c70df98 |
feat(sp20): Phase 3 Task 3.4 — replay buffer schema for per-bar aux_conf
Lands the producer→ring→consumer schema plumbing for per-bar aux_conf
(the K=2 peak-softmax-above-uniform confidence value the Phase 5
Aux→Q gate consumes at the Bellman target). Atomic across all struct
boundaries per `feedback_no_partial_refactor`.
Data flow (TWO struct boundaries, not one — plan errata Gap 11):
ExperienceCollector → GpuExperienceBatch → insert_batch()
(.aux_conf field) (8th arg)
→ ring → sample() → GpuBatchPtrs → Trainer
(.aux_conf_ptr) (Phase 5 consumer)
Phase 5 lands the consumer (Aux→Q gate kernel at the Bellman target);
this commit is the producer-side schema plumbing only.
Spec §4.4 Phase 5 forward-reference contract:
At each replay batch step:
aux_conf = ptrs.aux_conf_ptr[k] # SAMPLED bar
threshold = ISV[AUX_CONF_THRESHOLD_INDEX] # [0.01, 0.20]
temp = ISV[AUX_GATE_TEMP_INDEX]
gate = sigmoid((aux_conf - threshold) / temp) # ∈ [0, 1]
Q_target = gate × Q_full + (1 - gate) × mean_a Q(s, a)
Producer (experience_env_step):
- 1 new kernel arg `aux_conf_per_sample: float* [N×L×cf_mult]`.
- Per-bar write at kernel entry: `aux_conf_per_sample[out_off] =
sp20_compute_per_bar_aux_conf_k2(aux_logits + i*K)`.
- CF slot write: `aux_conf_per_sample[cf_off] =
aux_conf_per_sample[out_off]` (CF state shares the same env state
so shares the same aux signal).
- NULL-tolerant: defaults to 0.0f (K=2 uniform-prior sentinel).
GpuExperienceCollector:
- +`aux_conf_per_sample: CudaSlice<f32>` field.
- alloc with `total_output * cf_mult` for both on-policy + CF.
- Threads as kernel arg of experience_env_step.
- Clones into `GpuExperienceBatch.aux_conf` at end of
collect_experiences_gpu (size `total = base_total × 2`).
GpuExperienceBatch: +`aux_conf: CudaSlice<f32>` field.
GpuReplayBuffer (crates/ml-dqn):
- +`GpuBatchPtrs.aux_conf_ptr: u64`.
- +ring storage `aux_conf: CudaSlice<f32>` [capacity].
- +sample buffer `sample_aux_conf: CudaSlice<f32>` [max_batch_size].
- +`trainer_aux_conf_ptr: u64` for direct path.
- +`set_trainer_aux_conf_ptr` setter + `trainer_aux_conf_ptr`
accessor (mirrors `set_isv_signals_ptr` pattern).
- `insert_batch` adds 8th arg `aux_conf_in: &CudaSlice<f32>` —
scatters via `scatter_insert_f32` (reuses the rewards/dones
scatter kernel).
- `sample_proportional` adds gather: direct-to-trainer if
`trainer_aux_conf_ptr != 0`, else fallback into
`sample_aux_conf`. Both paths populate `GpuBatchPtrs.aux_conf_ptr`.
Atomic caller updates (insert_batch arg from 7 to 8):
- training_loop.rs:2522 (production)
- gpu_residency.rs:77 (smoke)
- performance.rs:144 (smoke)
- training_stability.rs:154+201 (smoke ×2)
- gpu_per_integration_test.rs:128 (integration)
- sp15_phase1_oracle_tests.rs:2170+2189+2356 (oracle ×3)
- 3 inline tests in gpu_replay_buffer.rs
Tests:
- test_aux_conf_schema_round_trip (GPU): inserts 8 transitions with
distinct aux_conf [0.0, 0.05, ..., 0.35]; samples 1; asserts the
gathered slot value matches one of the inserted values
(round-trip integrity invariant).
- test_aux_conf_trainer_ptr_wiring_contract (CPU): asserts
set_trainer_aux_conf_ptr / trainer_aux_conf_ptr setter+accessor
behavior matches the SP15 Phase 3.5.5.b mirror pattern.
Verification:
SQLX_OFFLINE=true cargo check -p ml --tests --features cuda # green
SQLX_OFFLINE=true cargo check -p ml-dqn --tests --features cuda # green
SQLX_OFFLINE=true cargo test -p ml --lib sp20 # 21/21 pass
SQLX_OFFLINE=true cargo test -p ml-dqn test_aux_conf_trainer_ptr_wiring_contract # CPU pass
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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jgrusewski
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06dbb78ffc |
feat(sp20): Phase 3 Task 3.2 — Hold opportunity-cost dual emission (Component 2)
Lands the per-bar Hold opportunity-cost dual emission at
experience_env_step's per-bar branches (positioned-non-event ~3650 +
flat-non-event ~3737), atomically with the trade-close consumer
wiring at the segment_complete branch (~3289 — replaces the Phase 2
Task 2.2 forward-reference placeholder `hold_baseline = 0.0f`) per
`feedback_no_partial_refactor`.
Spec §4.2 dual-emission contract:
per_bar_opp_cost = -aux_conf × cost_scale
Path 1 (Hold-only): r_micro/r_opp_cost += per_bar_opp_cost
- ISV[HOLD_REWARD_EMA]
(centered for Q-target stability)
Path 2 (always): hold_baseline_buffer[env, t % 30] = per_bar_opp_cost
(uncentered, consumed at trade close)
At trade close:
hold_baseline = sp20_sum_hold_baseline_over_trade(buf, env, 30,
current_t,
segment_hold_time)
alpha = R_event - hold_baseline # replaces Phase 2 placeholder
The summation walks backwards `min(30, segment_hold_time)` slots from
`(current_t - 1) % 30` in env i's row of the per-env circular buffer.
The trade-close bar's segment_complete branch does NOT write to the
buffer, so the most recent per-bar write is at current_t - 1.
Layout decision (plan errata Gap 9): per-env stride
`[N_envs × HOLD_BASELINE_BUFFER_SIZE = 30]` row-major. The kernel is
per-env-parallel; a single global ring would interleave bars across
envs and break trade-attribution semantic.
Trade-open tracking decision (plan errata Gap 10): NO new state slot
needed. The existing `segment_hold_time` (= saved_hold_time captured
before PS_HOLD_TIME reset at experience_kernels.cu:2618) plus
current_t suffice — walk backwards in the buffer.
Replaces SP18 D-leg `compute_sp18_hold_opportunity_cost` calls at
experience_kernels.cu:3672 and :3783. The device function in
trade_physics.cuh:655 is RETAINED — still called by
sp18_hold_opp_test_kernel.cu (oracle test surface). Per
`feedback_no_stubs`: only production callers migrate; the helper
stays for the test surface.
New device helpers (sp20_hold_baseline.cuh):
- sp20_compute_per_bar_aux_conf_k2(logits) — bit-identical to the
formula in sp20_stats_compute_kernel.cu Pass A.
- sp20_sum_hold_baseline_over_trade(buf, env, size, current_t,
segment_hold_time) — walks backwards with modulo wrap-around.
New buffer + reset infrastructure:
- GpuExperienceCollector.hold_baseline_buffer field
- HOLD_BASELINE_BUFFER_SIZE = 30 constant (re-exported)
- StateResetRegistry FoldReset entry + invariant test
- reset_named_state dispatch arm
Six new kernel args appended to experience_env_step signature:
aux_logits_per_env, hold_baseline_buffer, hold_buffer_size, aux_k,
hold_cost_scale_idx, hold_reward_ema_idx. All NULL-tolerant.
HOLD_REWARD_EMA forward-reference: ISV[516] is updated by
sp20_emas_compute_kernel reading per_bar_hold_reward from
sp20_aggregate_inputs_kernel which currently emits 0.0f as a Phase
3.2 forward-ref placeholder (line 292). The parallel `sp20-phase-2-fix`
agent owns wiring the real producer; Task 3.2's centering math
references the ISV slot (not a hardcoded 0), so when the parallel
branch lands, EMA starts updating and centering becomes load-bearing
automatically. No additional Task 3.2 work needed post-merge.
Tests (sp20_hold_baseline_test.rs, 4 GPU oracle tests):
1. aux_conf_k2_bounds_and_fixed_points — bounds, uniform/saturated/
spec-warmup/spec-confident/symmetry fixed points.
2. sum_hold_baseline_over_trade_indexing — basic indexing,
hold_time>size clamp, defensive guards, modulo wrap-around.
3. sum_hold_baseline_per_env_stride — env-stride correctness across
row-major buffer.
4. dual_emission_hold_vs_non_hold — full Path 1 + Path 2 contract,
mirrors plan §3.2 reference fixture.
Verification:
SQLX_OFFLINE=true cargo check -p ml --tests --features cuda # green
SQLX_OFFLINE=true cargo test -p ml --lib sp20 # 21/21 pass
SQLX_OFFLINE=true cargo build -p ml # cubin compile
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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